This patch series does some bug fixes and code cleanup in the MIPS
target, and then does some optimizations.
Changes v1 -> v2:
- patch 1: new patch
- patch 2: new patch
- patch 5: new patch to address Richard Henders comments
- patch 6: update following patch 5 addition
- patch 7: new patch to address Richard Henders comments
- patch 9: new patch to address Richard Henders comments
- patch 16: spare one register by reusing the output of setcond to assign
the value 1
- patch 17: remove the buggy (lsb > msb) case
- patch 18: fixed indentation
--
Aurelien Jarno (19):
target-mips: correctly restore btarget upon exception
target-mips: do not save CPU state when using retranslation
softfloat: implement fused multiply-add NaN propagation for MIPS
target-mips: use the softfloat floatXX_muladd functions
target-mips: keep softfloat exception set to 0 between instructions
target-mips: fix FPU exceptions
target-mips: cleanup float to int conversion helpers
target-mips: use softfloat constants when possible
target-mips: restore CPU state after an FPU exception
target-mips: cleanup load/store operations
target-mips: optimize load operations
target-mips: simplify load/store microMIPS helpers
target-mips: implement unaligned loads using TCG
target-mips: don't use local temps for store conditional
target-mips: implement movn/movz using movcond
target-mips: optimize ddiv/ddivu/div/divu with movcond
target-mips: use deposit instead of hardcoded version
target-mips: fix TLBR wrt SEGMask
target-mips: don't flush extra TLB on permissions upgrade
fpu/softfloat-specialize.h | 27 ++
target-mips/helper.h | 12 +-
target-mips/op_helper.c | 824 ++++++++++++++++----------------------------
target-mips/translate.c | 391 ++++++++++-----------
4 files changed, 520 insertions(+), 734 deletions(-)
--
1.7.10.4
