Re: [openib-general] [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-23 Thread Grant Grundler
On Fri, Jun 23, 2006 at 04:04:31PM +0200, Arjan van de Ven wrote: > > I thought the posted write WILL eventually get to adapter memory. Not > > stall forever cached in a bridge. I'm wrong? > > I'm not sure there is a theoretical upper bound I'm not aware of one either since MMIO writes can

Re: [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-23 Thread Arjan van de Ven
> > > + /* Tell HW to xmit */ > > > + __raw_writeq(cpu_to_be64(mapaddr), elem->hw_desc + C2_TXP_ADDR); > > > + __raw_writew(cpu_to_be16(maplen), elem->hw_desc + C2_TXP_LEN); > > > + __raw_writew(cpu_to_be16(TXP_HTXD_READY), elem->hw_desc + C2_TXP_FLAGS); > > > > or here > > > > No need here. T

Re: [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-23 Thread Arjan van de Ven
On Fri, 2006-06-23 at 08:56 -0500, Steve Wise wrote: > On Fri, 2006-06-23 at 15:48 +0200, Arjan van de Ven wrote: > > > > > + /* Tell HW to xmit */ > > > > > + __raw_writeq(cpu_to_be64(mapaddr), elem->hw_desc + C2_TXP_ADDR); > > > > > + __raw_writew(cpu_to_be16(maplen), elem->hw_desc +

Re: [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-23 Thread Steve Wise
> > Also on a related note, have you checked the driver for the needed PCI > posting flushes? > > > + > > + /* Disable IRQs by clearing the interrupt mask */ > > + writel(1, c2dev->regs + C2_IDIS); > > + writel(0, c2dev->regs + C2_NIMR0); > > like here... This code is followed by a call

Re: [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-23 Thread Steve Wise
On Fri, 2006-06-23 at 15:48 +0200, Arjan van de Ven wrote: > > > > + /* Tell HW to xmit */ > > > > + __raw_writeq(cpu_to_be64(mapaddr), elem->hw_desc + C2_TXP_ADDR); > > > > + __raw_writew(cpu_to_be16(maplen), elem->hw_desc + C2_TXP_LEN); > > > > + __raw_writew(cpu_to_be16(T

Re: [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-21 Thread Steve Wise
> ok pci posting... > > basically, if you use writel() and co, the PCI bridges in the middle are > allowed (and the more fancy ones do) cache the write, to see if more > writes follow, so that the bridge can do the writes as a single burst to > the device, rather than as individual writes. This i

Re: [openib-general] [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-21 Thread Grant Grundler
On Wed, Jun 21, 2006 at 11:32:51AM -0500, Steve Wise wrote: > Um, what's a 'PCI posting flush'? Can you point me where its > described/used so I can see if we need it? Thanx. I've written this up before: http://iou.parisc-linux.org/ols_2002/4Posted_vs_Non_Posted.html grant - To unsubscr

Re: [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-21 Thread Arjan van de Ven
> 0; > > > + > > > + __raw_writew(0, elem->hw_desc + C2_RXP_STATUS); > > > + __raw_writew(0, elem->hw_desc + C2_RXP_COUNT); > > > + __raw_writew(0, elem->hw_desc + C2_RXP_LEN); > > > > you seem to be a fan of the __raw_write() functions... any reason why? > > __raw_ is not

Re: [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-21 Thread Steve Wise
On Tue, 2006-06-20 at 22:43 +0200, Arjan van de Ven wrote: > On Tue, 2006-06-20 at 15:30 -0500, Steve Wise wrote: > > > +/* > > + * Allocate TX ring elements and chain them together. > > + * One-to-one association of adapter descriptors with ring elements. > > + */ > > +static int c2_tx_ring_alloc

Re: [PATCH v3 1/7] AMSO1100 Low Level Driver.

2006-06-20 Thread Arjan van de Ven
On Tue, 2006-06-20 at 15:30 -0500, Steve Wise wrote: > +/* > + * Allocate TX ring elements and chain them together. > + * One-to-one association of adapter descriptors with ring elements. > + */ > +static int c2_tx_ring_alloc(struct c2_ring *tx_ring, void *vaddr, > + dma_ad