On Fri, Jun 23, 2006 at 04:04:31PM +0200, Arjan van de Ven wrote: > > I thought the posted write WILL eventually get to adapter memory. Not > > stall forever cached in a bridge. I'm wrong? > > I'm not sure there is a theoretical upper bound....
I'm not aware of one either since MMIO writes can travel across many other chips that are not constrained by PCI ordering rules (I'm thinking of SGI Altix...) > (and if it's several msec per bridge, then you have a lot of latency > anyway) That's what my original concern was when I saw you point this out. But MMIO reads here would be expensive and many drivers tolerate this latency in exchange for avoiding the MMIO read in the performance path. grant - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
