> ok pci posting... > > basically, if you use writel() and co, the PCI bridges in the middle are > allowed (and the more fancy ones do) cache the write, to see if more > writes follow, so that the bridge can do the writes as a single burst to > the device, rather than as individual writes. This is of course great... > ... except when you really want the write to hit the device before the > driver continues with other actions. > > Now the PCI spec is set up such that any traffic in the other direction > (basically readl() and co) will first flush the write through the system > before the read is actually sent to the device, so doing a dummy readl() > is a good way to flush any pending posted writes. > > Where does this matter? > it matters most at places such as irq enabling/disabling, IO submission > and possibly IRQ acking, but also often in eeprom-like read/write logic > (where you do manual clocking and need to do delays between the > write()'s). But in general... any place where you do writel() without > doing any readl() before doing nothing to the card for a long time, or > where you are waiting for the card to do something (or want it done NOW, > such as IRQ disabling) you need to issue a (dummy) readl() to flush > pending writes out to the hardware. > > > does this explanation make any sense? if not please feel free to ask any > questions, I know I'm not always very good at explaining things.
Yep. I get it. I believe we're ok in this respect, but I'll review the code again with an eye for this issue... Steve. - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
