> If I remember the Marvell specs correctly, there was some bit to switch the
> complete register set to fibre mode.
Hi Heiner
The Marvell PHY has a second page for Fibre. It mostly mirrors the
normal registers, and you need to look at both pages to determine if
copper or fibre has link, etc. Fib
On 04.06.2019 18:54, Andrew Lunn wrote:
>> So it seems like what is missing is the ability of genphy_config_init to
>> detect the bits in the extended status register for 1000Base-X and add
>> the corresponding mode flags. It appears bit 15 for 1000Base-X full
>> duplex is standardized in 802.3 Cla
On 2019-06-04 10:54 a.m., Andrew Lunn wrote:
>> So it seems like what is missing is the ability of genphy_config_init to
>> detect the bits in the extended status register for 1000Base-X and add
>> the corresponding mode flags. It appears bit 15 for 1000Base-X full
>> duplex is standardized in 802.
> So it seems like what is missing is the ability of genphy_config_init to
> detect the bits in the extended status register for 1000Base-X and add
> the corresponding mode flags. It appears bit 15 for 1000Base-X full
> duplex is standardized in 802.3 Clause 22, so I would expect Linux
> should be
On 2019-06-03 11:37 p.m., Heiner Kallweit wrote:
>> +/* Xilinx PHY wrongly indicates BMSR_ESTATEN = 0 even though
>> + * extended status registers are supported. So we force the PHY
>> + * features to PHY_GBIT_FEATURES in order to allow gigabit support
>> + * to be detected.
>> +
On 04.06.2019 01:12, Robert Hancock wrote:
> This adds a driver for the PHY device implemented in the Xilinx PCS/PMA
> Core logic. This is mostly a generic gigabit PHY, except that the
> features are explicitly set because the PHY wrongly indicates it has no
> extended status register when it actua
+Heiner, Andrew,
On 6/3/2019 4:12 PM, Robert Hancock wrote:
> This adds a driver for the PHY device implemented in the Xilinx PCS/PMA
> Core logic. This is mostly a generic gigabit PHY, except that the
> features are explicitly set because the PHY wrongly indicates it has no
> extended status regi
On Mon, 3 Jun 2019 17:12:04 -0600
Robert Hancock wrote:
> This adds a driver for the PHY device implemented in the Xilinx PCS/PMA
> Core logic. This is mostly a generic gigabit PHY, except that the
> features are explicitly set because the PHY wrongly indicates it has no
> extended status registe
This adds a driver for the PHY device implemented in the Xilinx PCS/PMA
Core logic. This is mostly a generic gigabit PHY, except that the
features are explicitly set because the PHY wrongly indicates it has no
extended status register when it actually does.
This version is a simplified version of
