+Heiner, Andrew,
On 6/3/2019 4:12 PM, Robert Hancock wrote:
> This adds a driver for the PHY device implemented in the Xilinx PCS/PMA
> Core logic. This is mostly a generic gigabit PHY, except that the
> features are explicitly set because the PHY wrongly indicates it has no
> extended status register when it actually does.
>
> This version is a simplified version of the GPL 2+ version from the
> Xilinx kernel tree.
For future submission, please use scripts/get_maintainer.pl so the
appropriate maintainers can be copied and give a chance to review this.
>
> Signed-off-by: Robert Hancock <hanc...@sedsystems.ca>
> ---
>
[snip]
> +/* Mask used for ID comparisons */
> +#define XILINX_PHY_ID_MASK 0xfffffff0
> +
> +/* Known PHY IDs */
> +#define XILINX_PHY_ID 0x01740c00
> +
> +static struct phy_driver xilinx_drivers[] = {
> +{
> + .phy_id = XILINX_PHY_ID,
> + .phy_id_mask = XILINX_PHY_ID_MASK,
You can use PHY_ID_MATCH_MODEL to declare the first two fields here.
> + .name = "Xilinx PCS/PMA PHY",
> + /* Xilinx PHY wrongly indicates BMSR_ESTATEN = 0 even though
> + * extended status registers are supported. So we force the PHY
> + * features to PHY_GBIT_FEATURES in order to allow gigabit support
> + * to be detected.
> + */
A PHY fixup might have worked too, but I suppose this is equally fine.
--
Florian
