Re: [Mesa-dev] [PATCH v3 1/4] nir: set default lod to texture opcodes that needed it but don't provide it

On Wednesday, October 18, 2017 8:11:01 AM CEST Jason Ekstrand wrote: > On October 18, 2017 12:54:48 AM Samuel Iglesias Gonsálvez > > wrote: > > v2: > > - Use helper to add a new source to the texture instruction. > > > > Signed-off-by: Samuel Iglesias Gonsálvez > > --- > > > > src/compiler/ni

Re: [Mesa-dev] [PATCH] glsl/linker: outputs in the same location must share interpolation

On Thu, 2017-10-19 at 17:14 +1100, Timothy Arceri wrote: > > On 19/10/17 16:57, Iago Toral Quiroga wrote: > >  From ARB_enhanced_layouts: > > > > "[...]when location aliasing, the aliases sharing the location > >   must have the same underlying numerical type (floating-point or > >   integer) and

[Mesa-dev] [PATCH] isl: Fix width check in isl_gen7_choose_msaa_layout.

The restriction is supposed to apply if the width *field* is >= 8192, meaning the actual width *value* is >= 8193. The code also incorrectly used == for some reason. --- src/intel/isl/isl_gen7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl_gen7.c b/src/int

Re: [Mesa-dev] [PATCH] glsl/linker: outputs in the same location must share interpolation

On 19/10/17 16:57, Iago Toral Quiroga wrote: From ARB_enhanced_layouts: "[...]when location aliasing, the aliases sharing the location must have the same underlying numerical type (floating-point or integer) and the same auxiliary storage and interpolation qualification.[...]" Add code

[Mesa-dev] [PATCH] ac: move some code out of loop in store_tcs_output()

--- src/amd/common/ac_nir_to_llvm.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 7424cc93f9..75fdc774fb 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -2

Re: [Mesa-dev] [PATCH 3/4] i965: Remove the intel_miptree_prepare_fb_fetch wrapper.

On Wed, Oct 18, 2017 at 10:42:59PM -0700, Kenneth Graunke wrote: > Now that intel_miptree_prepare_texture takes levels and layers, there's > not much use in this anymore. > --- > src/mesa/drivers/dri/i965/brw_draw.c | 6 -- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 ---

[Mesa-dev] [PATCH] etnaviv: keep track of buffer valid ranges

This allows a write to proceed to an uninitialized part of a buffer even when the GPU is using the previously-initialized portions. Same is done for freedreno, nouveau and radeon. Signed-off-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/etnaviv_resource.c | 3 +++ src/gallium/drivers/et

[Mesa-dev] [PATCH] glsl/linker: outputs in the same location must share interpolation

From ARB_enhanced_layouts: "[...]when location aliasing, the aliases sharing the location must have the same underlying numerical type (floating-point or integer) and the same auxiliary storage and interpolation qualification.[...]" Add code to the linker to validate that aliased locations do

Re: [Mesa-dev] [PATCH] i965/sbe: fix active components for SSO programs with over 16 inputs

On Friday, October 13, 2017 2:10:15 AM PDT Iago Toral Quiroga wrote: > When we have up to 16 FS inputs, the SF unit will reorder our inputs > to be consecutive, however, when we have more than 16 we need to > to read our inputs from the URB exactly as they have been > output from the previous stage

[Mesa-dev] [PATCH 1/4] i965: Make intel_miptree_prepare_texture() take level/layer arguments.

This effectively exports intel_miptree_prepare_texture_slices() as intel_miptree_prepare_texture(). The hope is to avoid resolves for when using texture views that access a subset of the levels/layers. For now, we pass the same arguments to separate the mechanical change from the one that actuall

[Mesa-dev] [PATCH 2/4] i965: Only resolve texture levels/layers that are accessed.

This should avoid unnecessary resolves when working with texture views. --- src/mesa/drivers/dri/i965/brw_draw.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index f9a8264f27f..5

[Mesa-dev] [PATCH 4/4] i965: Don't disable aux buffers for non-overlapping miplevels.

Meta's GenerateMipmap implementation binds the same image for both sampling and rendering - but it samples from one miplevel while rendering the next. This is a false self-dependency, and there's no need to disable auxiliary buffers in this case. In fact, we really want to leave it enabled so the

[Mesa-dev] [PATCH 3/4] i965: Remove the intel_miptree_prepare_fb_fetch wrapper.

Now that intel_miptree_prepare_texture takes levels and layers, there's not much use in this anymore. --- src/mesa/drivers/dri/i965/brw_draw.c | 6 -- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 -- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 + 3 files

[Mesa-dev] [PATCH v2 29/32] disk_cache: Fix issue reading GLSL metadata

This would cause the read of the metadata content to fail, which would prevent the linking from being skipped. Seen on Rocket League with i965 shader cache. Cc: Timothy Arceri Signed-off-by: Jordan Justen --- src/util/disk_cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --g

[Mesa-dev] [PATCH v2 28/32] glsl/shader_cache: Save fs (BlendSupport) metadata

Fixes many GL 4.5 CTS blend tests, such as: * GL45-CTS.blend_equation_advanced.extension_directive_enable * GL45-CTS.blend_equation_advanced.extension_directive_warn * GL45-CTS.blend_equation_advanced.blend_all.GL_MULTIPLY_KHR_all_qualifier * GL45-CTS.blend_equation_advanced.blend_specific.GL_COLO

[Mesa-dev] [PATCH v2 24/32] i965: add support for cached shaders with xfb qualifiers

From: Timothy Arceri For now this disables the shader cache when transform feedback is enabled via the GL API as we don't currently allow for it when generating the sha for the shader. --- src/mesa/drivers/dri/i965/brw_disk_cache.c | 8 1 file changed, 8 insertions(+) diff --git a/src/

[Mesa-dev] [PATCH v2 04/32] compiler/types: Support [de]serializing void types

From: Jason Ekstrand --- src/compiler/glsl_types.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp index a7fc7ff7f6..704b63c5cf 100644 --- a/src/compiler/glsl_types.cpp +++ b/src/compiler/glsl_types.cpp @@ -2149,6 +2149,8 @@ enco

[Mesa-dev] [PATCH v2 23/32] mesa/glsl: add api_enabled flag to gl_transform_feedback_info

From: Timothy Arceri This will be used to disable the shader cache when xfb is enabled via the api as we don't currently allow for it when generating the sha for the shader. --- src/compiler/glsl/link_varyings.cpp | 5 - src/mesa/main/mtypes.h | 3 +++ 2 files changed, 7 inserti

[Mesa-dev] [PATCH v2 31/32] i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false

Double negative FTW! For now, the shader cache is disabled by default on i965 to allow us to verify its stability. In other words, to enable the shader cache on i965, set MESA_GLSL_CACHE_DISABLE to false or 0. If the variable is unset, then the shader cache will be disabled. We use the build-id

[Mesa-dev] [PATCH v2 26/32] i965: Don't link when the program was found in the disk cache

Signed-off-by: Jordan Justen Cc: Timothy Arceri --- src/mesa/drivers/dri/i965/brw_link.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 2d10325e4a..b5b84dec63 100644 --- a/src/mesa/drivers/dri/i965/b

[Mesa-dev] [PATCH v2 32/32] disk_cache: Add support for MESA_GLSL_CACHE_TIMESTAMP in debug builds

The MESA_GLSL_CACHE_TIMESTAMP environment variable can be set to override the driver timestamp. Usually the driver will specify a hash of their driver build so the cache items become invalid with each driver build. We don't guarantee a stable serialized shader cache format, so changing the timesta

[Mesa-dev] [PATCH v2 22/32] i965: Add shader cache support for compute

v2: * Use MAYBE_UNUSED. (Matt) Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_cs.c | 24 --- src/mesa/drivers/dri/i965/brw_cs.h | 3 +++ src/mesa/drivers/dri/i965/brw_disk_cache.c | 36 +++- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH v2 03/32] nir/intrinsics: Set the correct num_indices for load_output

From: Jason Ekstrand Cc: mesa-sta...@lists.freedesktop.org --- src/compiler/nir/nir_intrinsics.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_intrinsics.h b/src/compiler/nir/nir_intrinsics.h index 0de7080bfa..cefd18be90 100644 --- a/src/compiler/nir/n

[Mesa-dev] [PATCH v2 20/32] i965: add shader cache support for geometry shaders

From: Timothy Arceri v2: * Use MAYBE_UNUSED. (Matt) [jordan.l.jus...@intel.com: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_disk_cache.c | 25 + src/mesa/drivers/dri/i965/brw_gs.c | 22 +++

[Mesa-dev] [PATCH v2 30/32] dri drivers: Always add the sha1 build-id

Cc: Dylan Baker Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/Makefile.am | 1 + src/mesa/drivers/dri/meson.build | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/Makefile.am b/src/mesa/drivers/dri/Makefile.am index 95c637d0cd..5cb2127501 100644

[Mesa-dev] [PATCH v2 06/32] nir: Zero local_size const struct for valgrind & nir_serialize

Signed-off-by: Jordan Justen --- src/compiler/nir/nir_lower_system_values.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/nir/nir_lower_system_values.c b/src/compiler/nir/nir_lower_system_values.c index ba20d3083f..39b1a260bd 100644 --- a/src/compiler/nir/nir_lower_system_valu

[Mesa-dev] [PATCH v2 21/32] i965: add shader cache support for tess stages

From: Timothy Arceri v2: * Use MAYBE_UNUSED. (Matt) [jordan.l.jus...@intel.com: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_disk_cache.c | 49 ++ src/mesa/drivers/dri/i965/brw_tcs.c| 23 ++

[Mesa-dev] [PATCH v2 27/32] i965: Initialize sha1 hash of dri config options

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.c | 4 src/mesa/drivers/dri/i965/brw_context.h | 1 + 2 files changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 609d815064..6a88d8bb48 100644 -

[Mesa-dev] [PATCH v2 12/32] nir: Add hooks for testing serialization

From: Jason Ekstrand --- src/compiler/nir/nir.h | 17 + src/compiler/nir/nir_serialize.c | 19 +++ 2 files changed, 36 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index dd833cf183..87c725625d 100644 --- a/src/compiler/nir/

[Mesa-dev] [PATCH v2 11/32] nir: add serialization and deserialization

From: Connor Abbott v2 (Jason Ekstrand): - Various whitespace cleanups - Add helpers for reading/writing objects - Rework derefs - [de]serialize nir_shader::num_* - Fix uses of blob_reserve_bytes - Use a bitfield struct for packing tex_instr data v3: - Zero nir_variable struct on deserial

[Mesa-dev] [PATCH v2 25/32] i965: add cache fallback support using serialized nir

If the i965 gen program cannot be loaded from the cache, then we fallback to using a serialized nir program. This is based on "i965: add cache fallback support" by Timothy Arceri . Tim's version was written to fallback to compiling from source, and therefore had to be much more complex. After Conn

[Mesa-dev] [PATCH v2 17/32] intel/compiler: add new field for storing program size

From: Carl Worth This will be used by the on disk shader cache. v2: * Set in brw_compile_* rather than brw_codegen_*. (Jason) Signed-off-by: Timothy Arceri [jordan.l.jus...@intel.com: Only add to brw_stage_prog_data] Signed-off-by: Jordan Justen --- src/intel/compiler/brw_compiler.h

[Mesa-dev] [PATCH v2 08/32] nir: Zero nir_load_const_instr::value for valgrind & nir_serialize

Signed-off-by: Jordan Justen --- src/compiler/nir/nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c index fe48451694..cbba9c8749 100644 --- a/src/compiler/nir/nir.c +++ b/src/compiler/nir/nir.c @@ -481,6 +481,7 @@ nir_load_const_instr_create

[Mesa-dev] [PATCH v2 10/32] glsl_to_nir: Zero nir_constant in constant_copy for valgrind & nir_serialize

Signed-off-by: Jordan Justen --- src/compiler/glsl/glsl_to_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 1d1085ffbc..c659a25ca7 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compi

[Mesa-dev] [PATCH v2 13/32] main: Add nir serialization fields to gl_program

These fields can be used to optionally save off a nir serialized form of the program. Signed-off-by: Jordan Justen --- src/mesa/main/mtypes.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 2802a0e360..a5a1398698 100644 --- a/src/mesa/m

[Mesa-dev] [PATCH v2 16/32] i965: Don't rely on nir for uses_texture_gather

When a program is restored from the shader cache, prog->nir will be NULL, but prog->info will be restored. Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_wm.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 ++-- 2 files changed, 8 insertion

[Mesa-dev] [PATCH v2 14/32] glsl/shader_cache: Save and restore serialized nir in gl_program

Signed-off-by: Jordan Justen --- src/compiler/glsl/shader_cache.cpp | 16 1 file changed, 16 insertions(+) diff --git a/src/compiler/glsl/shader_cache.cpp b/src/compiler/glsl/shader_cache.cpp index ca90cfde35..f43bd6b17e 100644 --- a/src/compiler/glsl/shader_cache.cpp +++ b/src

[Mesa-dev] [PATCH v2 18/32] i965: add initial implementation of on disk shader cache

From: Timothy Arceri This uses the recently-added disk_cache.c to write out the final linked binary for vertex and fragment shader programs. This is based off the initial implementation done by Carl Worth. v2: * Squash 'i965: add image param shader cache support' * Squash 'i965: add shader ca

[Mesa-dev] [PATCH v2 15/32] i965/link: Serialize program to nir after linking for shader cache

If the shader cache is enabled, after linking the program, we serialize the program to nir. This will be saved out by the glsl shader cache support. Later, if the same program is found in the cache, we can use the nir for a fallback in the unlikely case that the gen binary program is not found in

[Mesa-dev] [PATCH v2 09/32] glsl_to_nir: Zero nir_variable struct for valgrind & nir_serialize

Signed-off-by: Jordan Justen --- src/compiler/glsl/glsl_to_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 63694fd41f..1d1085ffbc 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compi

[Mesa-dev] [PATCH v2 01/32] glsl: move shader_cache type handling to glsl_types

From: Connor Abbott Not sure if this is the best place to put it, but we're going to need this for NIR too. --- src/compiler/glsl/shader_cache.cpp | 171 - src/compiler/glsl_types.cpp| 171 + src/compiler/glsl_types.

[Mesa-dev] [PATCH v2 05/32] glsl: Zero per_vertex_accumulator::fields for valgrind & nir_serialize

Signed-off-by: Jordan Justen --- src/compiler/glsl/builtin_variables.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/glsl/builtin_variables.cpp b/src/compiler/glsl/builtin_variables.cpp index ea2d897cc8..d3cf12475b 100644 --- a/src/compiler/glsl/builtin_variables.cpp +++ b/s

[Mesa-dev] [PATCH v2 07/32] intel/nir: Zero local index const struct for valgrind & nir_serialize

Signed-off-by: Jordan Justen --- src/intel/compiler/brw_nir_lower_cs_intrinsics.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c index f9322654e7..d27727624c 100644 --- a/src/intel/compiler/b

[Mesa-dev] [PATCH v2 02/32] nir: Get rid of nir_shader::stage

From: Jason Ekstrand It's redundant with nir_shader::info::stage. --- src/amd/common/ac_nir_to_llvm.c| 30 ++--- src/amd/common/ac_shader_info.c| 2 +- src/amd/vulkan/radv_shader.c | 4 +- src/compiler/glsl/glsl_to_nir.cpp

[Mesa-dev] [PATCH v2 00/32] i965 disk shader cache

git://people.freedesktop.org/~jljusten/mesa i965-shader-cache-v2 The series adds support for a disk shader cache for i965, but it does not enable it by default. To enable the i965 shader cache you need to set the environment variable MESA_GLSL_CACHE_DISABLE=0. v2: * Fallback now uses Connor & J

[Mesa-dev] [PATCH v2 19/32] i965: Add shader cache support for vertex and fragment stages

From: Timothy Arceri This enables the cache on vertex and fragment shaders only. v2: * Use MAYBE_UNUSED. (Matt) [jordan.l.jus...@intel.com: reword subject] [jordan.l.jus...@intel.com: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw

Re: [Mesa-dev] [PATCH 04/21] intel: Rewrite the world of push/pull params

On Fri, Sep 29, 2017 at 2:25 PM, Jason Ekstrand wrote: > diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c > b/src/mesa/drivers/dri/i965/gen6_constant_state.c > index b2e357f..93a12c7 100644 > --- a/src/mesa/drivers/dri/i965/gen6_constant_state.c > +++ b/src/mesa/drivers/dri/i965/gen6_

Re: [Mesa-dev] [PATCH 3/4] meson: build libEGL

Quoting Eric Engestrom (2017-10-18 17:25:05) > On Wednesday, 2017-10-18 23:56:00 +, Dylan Baker wrote: > > This is based heavily on Daniel Stone's work for the same, rebased on > > master and with a number of TODO's fixed. > > > > This does not implement glvnd (which is coming in a later patch

[Mesa-dev] [PATCH] radv: fix CLEAR_STATE packet length.

From: Dave Airlie Looking at shader traces I noticed some registers were missing, one of them was being eaten by the wrong clear state length. Fixes: 4f42ea4dc (radv: use CLEAR_STATE for initializing some registers) Signed-off-by: Dave Airlie --- src/amd/vulkan/si_cmd_buffer.c | 2 +- 1 file c

Re: [Mesa-dev] [PATCH 2/2] drirc: Group a few games in the glthread whitelist together.

I pushed the series, thanks! Marek On Mon, Oct 16, 2017 at 12:22 AM, Darren Salt wrote: > --- > src/util/drirc | 27 +-- > 1 file changed, 21 insertions(+), 6 deletions(-) > > diff --git a/src/util/drirc b/src/util/drirc > index 3cf3d8dc69..39ac3c858c 100644 > --- a/src/

[Mesa-dev] [PATCH 14/16] radv: Add GFX9 HS emitting code.

--- src/amd/vulkan/radv_cmd_buffer.c | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 3e31fbafd34..a746777ca40 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv

[Mesa-dev] [PATCH 13/16] radv: Remove remaining hard coded references to VS.

--- src/amd/vulkan/radv_cmd_buffer.c | 19 ++- src/amd/vulkan/radv_pipeline.c | 14 -- src/amd/vulkan/radv_private.h| 2 ++ 3 files changed, 28 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7

[Mesa-dev] [PATCH 15/16] radv: Set correct registers for merged shader rings.

We need different regs to end up in s0/s1. --- src/amd/vulkan/radv_device.c | 36 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index fd705fe726d..125498809ec 100644 --- a/src/amd/vul

[Mesa-dev] [PATCH 12/16] radv: Update GFX9 user data regs for GS/tess.

--- src/amd/vulkan/radv_cmd_buffer.c | 14 +++--- src/amd/vulkan/radv_pipeline.c | 2 +- src/amd/vulkan/radv_shader.c | 19 +++ src/amd/vulkan/radv_shader.h | 4 ++-- 4 files changed, 25 insertions(+), 14 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer

[Mesa-dev] [PATCH 10/16] ac/nir: Add LS-HS input VGPR workaround.

--- src/amd/common/ac_nir_to_llvm.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index cb011bd88bb..242675654d2 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -6377,6

[Mesa-dev] [PATCH 16/16] radv: Modify rsrc1/rsrc2 generation for merged tess.

No OC_LDS_EN for HS, and the included LS vgpr_comp_cnt is at a different offset. --- src/amd/vulkan/radv_shader.c | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index a7836543998..a86ba2a01c0

[Mesa-dev] [PATCH 09/16] ac/nir: Compile the bodies of multiple shaders.

--- src/amd/common/ac_nir_to_llvm.c | 133 +--- 1 file changed, 83 insertions(+), 50 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 67945a353e8..cb011bd88bb 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/sr

[Mesa-dev] [PATCH 02/16] ac/nir: Add HS calling convention.

Needed for GFX9 merged shaders. --- src/amd/common/ac_nir_to_llvm.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 3ba3ebf051e..1df97b59a2e 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/co

[Mesa-dev] [PATCH 05/16] ac/nir: Make scan_shader_output_decl less dependent on the context.

--- src/amd/common/ac_nir_to_llvm.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 38f47b34e10..f01ca8799b9 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/comm

[Mesa-dev] [PATCH 08/16] ac/nir: Expand user SGPR descriptions a bit.

To prevent VS/TCS collisions in merged shaders. --- src/amd/common/ac_nir_to_llvm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h index 66d539dec47..360d613d58d 100644 --- a/src/amd/common/ac_nir_to_llvm.

[Mesa-dev] [PATCH 07/16] ac/nir: Don't write to the dynamic HS word on GFX9.

--- src/amd/common/ac_nir_to_llvm.c | 27 --- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index c6c56f30b81..67945a353e8 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/a

[Mesa-dev] [PATCH 04/16] ac/nir: Allow ac_shader_variant_info to contain info about multiple stages.

--- src/amd/common/ac_nir_to_llvm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h index 8a1e64ce7e1..66d539dec47 100644 --- a/src/amd/common/ac_nir_to_llvm.h +++ b/src/amd/common/ac_nir_to_llvm.h @@ -154,7 +154

[Mesa-dev] [PATCH 11/16] radv: Add code to compile merged shaders.

--- src/amd/common/ac_nir_to_llvm.h | 1 + src/amd/vulkan/radv_pipeline.c | 29 + src/amd/vulkan/radv_shader.c| 17 ++--- src/amd/vulkan/radv_shader.h| 5 +++-- 4 files changed, 39 insertions(+), 13 deletions(-) diff --git a/src/amd/common/ac_nir

[Mesa-dev] [PATCH 03/16] ac/nir: Change interface to allow multiple source shaders.

--- src/amd/common/ac_nir_to_llvm.c | 82 ++--- src/amd/common/ac_nir_to_llvm.h | 3 +- src/amd/vulkan/radv_shader.c| 2 +- 3 files changed, 48 insertions(+), 39 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c i

[Mesa-dev] [PATCH 01/16] ac: Parse the new HS RSRC1 register.

--- src/amd/common/ac_binary.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c index 1bf52c78328..cf0125c415f 100644 --- a/src/amd/common/ac_binary.c +++ b/src/amd/common/ac_binary.c @@ -252,6 +252,7 @@ void ac_shader_binary_read_config(s

[Mesa-dev] [PATCH 06/16] ac/nir: Add function creation for merged LS+HS.

--- src/amd/common/ac_nir_to_llvm.c | 254 1 file changed, 178 insertions(+), 76 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index f01ca8799b9..c6c56f30b81 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/s

Re: [Mesa-dev] [PATCH 2/2] i965: Use is_scheduling_barrier instead of schedule_node::is_barier.

On Wed, Oct 18, 2017 at 4:59 PM, Kenneth Graunke wrote: > Commit a73116ecc60414ade89802150b tried to make add_barrier_deps() > walk to the next barrier, and stop. To accomplish that, it added an > is_barrier flag. Unfortunately, this only works half of the time. > > The issue is that add_barrier

Re: [Mesa-dev] [PATCH 3/4] meson: build libEGL

On Wednesday, 2017-10-18 23:56:00 +, Dylan Baker wrote: > This is based heavily on Daniel Stone's work for the same, rebased on > master and with a number of TODO's fixed. > > This does not implement glvnd (which is coming in a later patch) > > Meson builds egl slightly differently than autot

Re: [Mesa-dev] [PATCH 2/2] i965: Use is_scheduling_barrier instead of schedule_node::is_barier.

typo in subject "is_barier" -> "is_barrier" Quoting Kenneth Graunke (2017-10-18 16:59:12) > Commit a73116ecc60414ade89802150b tried to make add_barrier_deps() > walk to the next barrier, and stop. To accomplish that, it added an > is_barrier flag. Unfortunately, this only works half of the time.

Re: [Mesa-dev] [PATCH 1/4] meson: Don't allow glx to be built without platform_x11

On Wednesday, 2017-10-18 23:56:05 +, Dylan Baker wrote: > Previously this failed to change with_glx to disabled from auto if > platform_x11 was unset or if no opengl apis were being built. > > Signed-off-by: Dylan Baker > --- > meson.build | 8 ++-- > 1 file changed, 6 insertions(+), 2 d

Re: [Mesa-dev] Upstream support for FreeSync / Adaptive Sync

On Wed, Oct 18, 2017 at 03:20:57PM -0400, Harry Wentland wrote: > On 2017-10-18 04:10 AM, Daniel Vetter wrote: > > On Tue, Oct 17, 2017 at 09:01:52PM +0200, Nicolai Hähnle wrote: > >> On 17.10.2017 19:16, Daniel Vetter wrote: > >>> On Tue, Oct 17, 2017 at 5:40 PM, Michel Dänzer wrote: > On 17

[Mesa-dev] [PATCH 2/2] i965: Use is_scheduling_barrier instead of schedule_node::is_barier.

Commit a73116ecc60414ade89802150b tried to make add_barrier_deps() walk to the next barrier, and stop. To accomplish that, it added an is_barrier flag. Unfortunately, this only works half of the time. The issue is that add_barrier_deps() walks both backward (to the previous barrier), and forward

[Mesa-dev] [PATCH 1/2] i965: Move fs_inst::has_side_effects()'s eot check to the parent class.

This eliminates a layer of wrapping, and makes a backend_instruction sufficient. The downside is that it exposes 'eot' to the vec4 backend, which it doesn't need, but can basically happily ignore. --- src/intel/compiler/brw_fs.cpp | 6 -- src/intel/compiler/brw_ir_fs.h | 2

[Mesa-dev] [PATCH 4/4] meson: Add support for EGL glvnd

Signed-off-by: Dylan Baker --- src/egl/meson.build | 46 -- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/src/egl/meson.build b/src/egl/meson.build index ade6810bf91..8ea8a5bbb69 100644 --- a/src/egl/meson.build +++ b/src/egl/meson.buil

[Mesa-dev] [PATCH 3/4] meson: build libEGL

This is based heavily on Daniel Stone's work for the same, rebased on master and with a number of TODO's fixed. This does not implement glvnd (which is coming in a later patch) Meson builds egl slightly differently than autotools, namely it doesn't build an intermediate shared library. It doesn't

[Mesa-dev] [PATCH 0/4] meson egl support

This small series adds support to the meson build system for building EGL in both the glvnd and traditional configurations. I have tested it against the i965 using piglit and didn't see any regressions in the egl tests. This work is based on work that Daniel Stone started, although I rewrote the p

[Mesa-dev] [PATCH 2/4] meson: move wayland_drm_protocol generation to wayland-drm

These files are needed by both vulkan wayland-wsi and by egl wayland-wsi, since the XML file is in src/egl/wayland/wayland-drm and we can include this directory in such a way that it will be loaded before egl and vulkan this allows us to avoid multiple calls to the same generator. Signed-off-by: D

[Mesa-dev] [PATCH 1/4] meson: Don't allow glx to be built without platform_x11

Previously this failed to change with_glx to disabled from auto if platform_x11 was unset or if no opengl apis were being built. Signed-off-by: Dylan Baker --- meson.build | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/meson.build b/meson.build index 82c4d2ed12c..13d

Re: [Mesa-dev] [PATCH v2] docs: add documentation for building with meson

Quoting Eric Engestrom (2017-10-18 15:27:39) > On Wednesday, 2017-10-18 18:09:22 +, Dylan Baker wrote: > > v2: - Add information about CC, CXX, CFLAGS, and CXXFLAGS (Nicolai) > > - Add message at top that meson for mesa is still a work in progress > > - Add trailing "/" to directories (

Re: [Mesa-dev] Upstream support for FreeSync / Adaptive Sync

On 2017-10-18 04:10 AM, Daniel Vetter wrote: > On Tue, Oct 17, 2017 at 09:01:52PM +0200, Nicolai Hähnle wrote: >> On 17.10.2017 19:16, Daniel Vetter wrote: >>> On Tue, Oct 17, 2017 at 5:40 PM, Michel Dänzer wrote: On 17/10/17 05:04 PM, Daniel Vetter wrote: > On Tue, Oct 17, 2017 at 03:46:

Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

On Wednesday, 2017-10-18 22:08:04 +, Dylan Baker wrote: > Quoting Eric Engestrom (2017-10-18 14:48:49) > > On Wednesday, 2017-10-18 18:45:19 +, Nicholas Miell wrote: > > > On 10/17/2017 12:21 PM, Dylan Baker wrote: > > > > + > > > > +To see a description of your options you can run "meson c

Re: [Mesa-dev] [PATCH v2 4/8] egl: add dri2_egl_surface_update_buffer_age() helper (v2)

The comment "we don't use get_back_bo() since ..." only makes sense in context on droid_swap_buffers. Why aren't you calling this helper in dri2_drm_swap_buffers and dri2_wl_swap_buffers_with_damage? It seems like you can. On Tue, Oct 17, 2017 at 7:38 AM, Emil Velikov wrote: > On 6 October 20

Re: [Mesa-dev] [PATCH mesa] egl: set UseFallback if LIBGL_ALWAYS_SOFTWARE is set

Reviewed-by: Gurchetan Singh On Wed, Oct 18, 2017 at 9:09 AM, Eric Engestrom wrote: > Suggested-by: Emil Velikov > Signed-off-by: Eric Engestrom > --- > src/egl/drivers/dri2/platform_surfaceless.c | 3 +-- > src/egl/drivers/dri2/platform_wayland.c | 3 +-- > src/egl/drivers/dri2/platform

Re: [Mesa-dev] [PATCH v2 1/8] egl: add dri2_egl_surface_free_outdated_buffers_and_update_size() helper (v2)

> Then again, I'd suggest keeping that as separate series. These patches > started as a way to minimise the duplication we have in drivers/dri2. I'm fine with dri2_$action_$object. We can modify the existing functions later, but I recommend adopting more concise conventions in this patchset, i.e:

Re: [Mesa-dev] [PATCH 1/2] radv: stop redundent setting of active_stages

Whoops I've fixed redundent -> redundant locally ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2] docs: add documentation for building with meson

On Wednesday, 2017-10-18 18:09:22 +, Dylan Baker wrote: > v2: - Add information about CC, CXX, CFLAGS, and CXXFLAGS (Nicolai) > - Add message at top that meson for mesa is still a work in progress > - Add trailing "/" to directories (Eric E.) > - Fix a number of spelling/grammar/sty

[Mesa-dev] [PATCH 2/2] radv: copy indirect lowering settings from radeonsi

It looks the original indirect mask was probably copied from ANV. Sascha Willems demo results: tessellation ~4000 -> ~4200 fps V2: continue lowering local indirect due to llvm deficiencies. Cc: Alex Smith --- src/amd/vulkan/radv_shader.c | 27 ++- 1 file changed, 26 in

[Mesa-dev] [PATCH 1/2] radv: stop redundent setting of active_stages

We already set it when above in the nir compilation loop. --- src/amd/vulkan/radv_pipeline.c | 4 1 file changed, 4 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 7102d07a03..15ef428be4 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd

Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

Quoting Nicholas Miell (2017-10-18 11:45:19) > On 10/17/2017 12:21 PM, Dylan Baker wrote: > > + > > +To see a description of your options you can run "meson configure". This > > will > > +show your meson project configuration options as well as your local > > +configuration options. One meson opti

Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

Quoting Eric Engestrom (2017-10-18 14:48:49) > On Wednesday, 2017-10-18 18:45:19 +, Nicholas Miell wrote: > > On 10/17/2017 12:21 PM, Dylan Baker wrote: > > > + > > > +To see a description of your options you can run "meson configure". This > > > will > > > +show your meson project configurati

Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

On Wednesday, 2017-10-18 18:45:19 +, Nicholas Miell wrote: > On 10/17/2017 12:21 PM, Dylan Baker wrote: > > + > > +To see a description of your options you can run "meson configure". This > > will > > +show your meson project configuration options as well as your local > > +configuration optio

Re: [Mesa-dev] [PATCH] tgsi: fix tgsi_util_get_inst_usage_mask

Reviewed-by: Marek Olšák Marek On Wed, Oct 18, 2017 at 11:17 PM, wrote: > From: Roland Scheidegger > > The logic for handling shadow coords was completely broken. > Fixes be3ab867bd444594f9d9e0f8e59d305d15769afd. > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103265 > --- > src/gal

[Mesa-dev] [PATCH] tgsi: fix tgsi_util_get_inst_usage_mask

From: Roland Scheidegger The logic for handling shadow coords was completely broken. Fixes be3ab867bd444594f9d9e0f8e59d305d15769afd. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103265 --- src/gallium/auxiliary/tgsi/tgsi_util.c | 12 ++-- 1 file changed, 6 insertions(+), 6 dele

Re: [Mesa-dev] [PATCH] radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite it

Quite bad fix.. I will have a better look tomorrow. Please ignore. On 10/18/2017 10:15 PM, Samuel Pitoiset wrote: Only on CIK and later. We should only update VGT_INDEX_TYPE but it seems easier to re-emit all the index buffer packets. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_c

[Mesa-dev] [PATCH] radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite it

Only on CIK and later. We should only update VGT_INDEX_TYPE but it seems easier to re-emit all the index buffer packets. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 8 1 file changed, 8 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulk

Re: [Mesa-dev] [PATCH 02/15] i965/screen: Add basic support for rendering 10 bpc/depth 30 framebuffers. (v2)

On 10/10/2017 12:51 PM, Tapani Pälli wrote: On 10/06/2017 07:11 PM, Mario Kleiner wrote: Expose formats which are supported at least back to Gen 5 Ironlake, possibly further. Allow creation of 10 bpc winsys buffers for drawables. glxinfo now lists new RGBA 10 10 10 2/0 formats. Works correctly

Re: [Mesa-dev] [PATCH 2/2] radv: do not re-emit the index buffer for every draw call

On 10/18/2017 09:54 PM, Dave Airlie wrote: On 19 October 2017 at 04:56, Bas Nieuwenhuizen wrote: Interesting that we already had RADV_CMD_DIRTY_INDEX_BUFFER. r-b for the series. On Wed, Oct 18, 2017 at 2:17 PM, Samuel Pitoiset wrote: It can only be changed when CmdBindIndexBuffer() is call

Re: [Mesa-dev] [PATCH 2/2] radv: do not re-emit the index buffer for every draw call

On 19 October 2017 at 04:56, Bas Nieuwenhuizen wrote: > Interesting that we already had RADV_CMD_DIRTY_INDEX_BUFFER. r-b for the > series. > > On Wed, Oct 18, 2017 at 2:17 PM, Samuel Pitoiset > wrote: >> It can only be changed when CmdBindIndexBuffer() is called >> or when a secondary buffer is

Re: [Mesa-dev] [PATCH] docs: add documentation for building with meson

On Wednesday, 2017-10-18 17:29:20 +, Dylan Baker wrote: > Quoting Eric Engestrom (2017-10-18 04:02:07) > > On Tuesday, 2017-10-17 19:21:10 +, Dylan Baker wrote: > > > Signed-off-by: Dylan Baker > > > --- > > > > > > I'm sending this out now so that others can look at it, review it, and >

Re: [Mesa-dev] Upstream support for FreeSync / Adaptive Sync

On Wed, Oct 18, 2017 at 6:59 PM, Michel Dänzer wrote: > On 18/10/17 12:15 PM, Nicolai Hähnle wrote: >> On 18.10.2017 10:10, Daniel Vetter wrote: >>> On Tue, Oct 17, 2017 at 09:01:52PM +0200, Nicolai Hähnle wrote: On 17.10.2017 19:16, Daniel Vetter wrote: > On Tue, Oct 17, 2017 at 5:40 PM,

  1   2   3   >