llvmbot wrote:
@llvm/pr-subscribers-mlir-vector
Author: Andrzej Warzyński (banach-space)
Changes
- **[[mlir][linalg] Refactor vectorization hooks to improve code reuse**
- **[mlir][linalg] Simplify `createWriteOrMaskedWrite` (NFC)**
---
Full diff: https://github.com/llvm/llvm-project/pul
llvmbot wrote:
@llvm/pr-subscribers-mlir-llvm
Author: Andrzej Warzyński (banach-space)
Changes
- **[[mlir][linalg] Refactor vectorization hooks to improve code reuse**
- **[mlir][linalg] Simplify `createWriteOrMaskedWrite` (NFC)**
---
Full diff: https://github.com/llvm/llvm-project/pull/
https://github.com/banach-space edited
https://github.com/llvm/llvm-project/pull/141567
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llvmbot wrote:
@llvm/pr-subscribers-mlir-linalg
Author: Andrzej Warzyński (banach-space)
Changes
- **[[mlir][linalg] Refactor vectorization hooks to improve code reuse**
- **[mlir][linalg] Simplify `createWriteOrMaskedWrite` (NFC)**
---
Full diff: https://github.com/llvm/llvm-project/pul
@@ -665,3 +724,9 @@ def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd,
IntRegs:$rs1, G0), 0>, Re
// sir -> sir 0
def : InstAlias<"sir", (SIR 0), 0>;
+
+// pause reg_or_imm -> wrasr %g0, reg_or_imm, %asr27
+let Predicates = [HasOSA2011] in {
+def : InstAlias<"pause $rs2",
@@ -141,6 +147,26 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
return 0;
}
+unsigned SparcMCCodeEmitter::getSImm5OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl &Fixups,
+
@@ -331,6 +331,25 @@ multiclass reg_cond_alias {
Requires<[Is64Bit]>;
}
+// Instruction aliases for compare-and-branch.
+multiclass cwb_cond_alias {
+ def : InstAliashttps://github.com/llvm/llvm-project/pull/138403
_
@@ -408,6 +427,46 @@ defm : reg_cond_alias<"ne", 0b101>;
defm : reg_cond_alias<"gz", 0b110>;
defm : reg_cond_alias<"gez", 0b111>;
+defm : cwb_cond_alias<"ne", 0b1001>;
+defm : cwb_cond_alias<"e",0b0001>;
+defm : cwb_cond_alias<"g",0b1010>;
+defm : cwb_cond_alias
@@ -102,6 +102,49 @@ class F2_4 pattern = [], InstrItinClass itin = NoItinerary>
+ : InstSP {
s-barannikov wrote:
```suggestion
: InstSP {
```
https://github.com/llvm/llvm-project/pull/138403
___
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@@ -217,6 +243,18 @@ unsigned SparcMCCodeEmitter::getBranchOnRegTargetOpValue(
return 0;
}
+unsigned SparcMCCodeEmitter::getCompareAndBranchTargetOpValue(
+const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups,
+const MCSubtargetInfo &STI) const {
+ const MCOpera
@@ -50,6 +50,15 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t
Value) {
return (d16hi << 20) | d16lo;
}
+ case ELF::R_SPARC_WDISP10: {
+// 7.17 Compare and Branch
+// Inst{20-19} = d10hi;
+// Inst{12-5} = d10lo;
+unsigned d10hi = (Value >>
@@ -102,6 +102,49 @@ class F2_4 pattern = [], InstrItinClass itin = NoItinerary>
+ : InstSP {
+ bits<10> imm10;
+ bits<5> rs1;
+ bits<5> rs2;
+ bits<4> cond;
+
+ let op = 0; // op = 0
+
+ let Inst{29}= cond{3};
+ let Inst{28}= 1;
+ let Inst{27-25} = c
@@ -0,0 +1,267 @@
+! RUN: llvm-mc -triple=sparcv9 -mattr=+osa2011 -filetype=obj %s | llvm-objdump
--mattr=+osa2011 --no-print-imm-hex -d - | FileCheck %s --check-prefix=BIN
+
+!! SPARCv9/SPARC64 BPr branches have different offset encoding from
the others,
---
skachkov-sc wrote:
Gentle ping
https://github.com/llvm/llvm-project/pull/140721
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https://github.com/llvm/llvm-project/pull/141567
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Author: Jan Patrick Lehr
Date: 2025-05-27T11:14:59+02:00
New Revision: 0412d56eaebb747cc77bd025969ed46e2b5cb12d
URL:
https://github.com/llvm/llvm-project/commit/0412d56eaebb747cc77bd025969ed46e2b5cb12d
DIFF:
https://github.com/llvm/llvm-project/commit/0412d56eaebb747cc77bd025969ed46e2b5cb12d.di
arsenm wrote:
ping
https://github.com/llvm/llvm-project/pull/140607
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https://github.com/llvm/llvm-project/pull/141567
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arsenm wrote:
ping
https://github.com/llvm/llvm-project/pull/140608
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@@ -0,0 +1,92 @@
+//===- TargetImpl.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132806
>From 597b0e0514f26f22e9425f25652657194aa48fc0 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 06:17:42 -0700
Subject: [PATCH] [Driver] Fix link order of BareMetal toolchain object
The
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 08e30252fc4bd87d84decc81161c081c774d398e Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/134442
>From 46b1136d0bab3cfc30029070597b76b4c2cbcbcf Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 4 Apr 2025 12:51:19 -0700
Subject: [PATCH] [RISCV][Driver] Add riscv emulation mode to linker job of
B
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/141589?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/141589
None
>From e5f24775ff988e5c6ac302f36b010fc0421eca34 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/140608
>From 6e7ab227c9d12cf82958ea0dd11461ec49bc4945 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 15 May 2025 10:51:39 +0200
Subject: [PATCH] AMDGPU: Fix tracking subreg defs when folding through
reg_seque
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/140878
>From 609dc72abf36343e62c4bb0bc149f9ba453f4236 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 19 May 2025 21:51:06 +0200
Subject: [PATCH] AMDGPU: Handle folding vector splats of inline split f64
inline
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/140587
>From c3f0ed4891b6cc34dc808e8673da5ff86a903df0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 19 May 2025 20:02:54 +0200
Subject: [PATCH 1/2] AMDGPU: Remove redundant operand folding checks
This was pr
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/140607
>From 8a6cb7bba02c0c6638a9b1789cf0feccd229f8b3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 May 2025 08:50:59 +0200
Subject: [PATCH] AMDGPU: Add baseline tests for #139317
---
.../CodeGen/AMDGPU/
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/140607
>From 8a6cb7bba02c0c6638a9b1789cf0feccd229f8b3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 May 2025 08:50:59 +0200
Subject: [PATCH] AMDGPU: Add baseline tests for #139317
---
.../CodeGen/AMDGPU/
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/140878
>From 609dc72abf36343e62c4bb0bc149f9ba453f4236 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 19 May 2025 21:51:06 +0200
Subject: [PATCH] AMDGPU: Handle folding vector splats of inline split f64
inline
https://github.com/Pierre-vh edited
https://github.com/llvm/llvm-project/pull/141589
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Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/141590?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/141590
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https://github.com/qinkunbao edited
https://github.com/llvm/llvm-project/pull/141540
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@@ -975,6 +977,62 @@ void AArch64::relocateAlloc(InputSectionBase &sec, uint8_t
*buf) const {
}
}
+static std::optional getControlTransferAddend(InputSection &is,
+Relocation &r) {
+ // Identify a control transfer rel
https://github.com/SLTozer approved this pull request.
https://github.com/llvm/llvm-project/pull/134650
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smithp35 wrote:
Thanks for the updates. I don't have any more comments.
https://github.com/llvm/llvm-project/pull/138366
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/141591
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-llvm-globalisel
Author: Pierre van Houtryve (Pierre-vh)
Changes
This
---
Patch is 38.92 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/141591.diff
8 Files Affected:
-
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-backend-amdgpu
Author: Pierre van Houtryve (Pierre-vh)
Changes
They're relatively safe to use there I believe. The only new registers
they may create are the constants for the BFX. For those, borrow the
RC from the so
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Pierre van Houtryve (Pierre-vh)
Changes
NFC
---
Full diff: https://github.com/llvm/llvm-project/pull/141589.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCombine.td (+13-1)
- (modified) llvm/lib/Target/AMDGP
https://github.com/Pierre-vh edited
https://github.com/llvm/llvm-project/pull/141591
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/140587
>From c3f0ed4891b6cc34dc808e8673da5ff86a903df0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 19 May 2025 20:02:54 +0200
Subject: [PATCH 1/2] AMDGPU: Remove redundant operand folding checks
This was pr
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/141591?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/qinkunbao updated
https://github.com/llvm/llvm-project/pull/141540
>From d5508cc217f413b3bbb7a301b2110cfc0c2c6cbc Mon Sep 17 00:00:00 2001
From: Qinkun Bao
Date: Tue, 27 May 2025 03:24:26 +
Subject: [PATCH 1/2] Format SpecialCaseList.h
Created using spr 1.3.6
---
llvm/i
mstorsjo wrote:
So, this backport in itself should be clean, but running libcxx CI on the 20.x
release branch is broken and would require a few other backports, that are
entangled. So it's basically up to @ldionne if he thinks it's ok to merge
despite the unrelated CI failures. (It is tricky b
https://github.com/Pierre-vh edited
https://github.com/llvm/llvm-project/pull/141591
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mstorsjo wrote:
Closing this one. Backporting the extra changes turned out to be a bit messy
and entangled. (It's not impossible to do though, but it would require buy-in
from libcxx maintainers that we do want to fix up the CI on the 20.x branch.)
The original backport in #136449 should be fi
https://github.com/mstorsjo closed
https://github.com/llvm/llvm-project/pull/139468
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https://github.com/qinkunbao edited
https://github.com/llvm/llvm-project/pull/141540
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 687bf11493d38ba323e90c1b40ae6919d48ed016 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH] [AMDGPU] Add KnownBits simplification combines to
RegBankCombiner
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 150fe8c86c080a075fef344b20cd15b1097d3f29 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/lib/Ta
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 687bf11493d38ba323e90c1b40ae6919d48ed016 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH] [AMDGPU] Add KnownBits simplification combines to
RegBankCombiner
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 150fe8c86c080a075fef344b20cd15b1097d3f29 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/lib/Ta
@@ -151,6 +151,17 @@ def zext_of_shift_amount_combines : GICombineGroup<[
canonicalize_zext_lshr, canonicalize_zext_ashr, canonicalize_zext_shl
]>;
+// Early select of uniform BFX into S_BFE instructions.
+// These instructions encode the offset/width in a way that requires
@@ -392,6 +394,55 @@ void
AMDGPURegBankCombinerImpl::applyCanonicalizeZextShiftAmt(
MI.eraseFromParent();
}
+bool AMDGPURegBankCombinerImpl::lowerUniformBFX(MachineInstr &MI) const {
+ assert(MI.getOpcode() == TargetOpcode::G_UBFX ||
+ MI.getOpcode() == TargetOpcod
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/117037
>From 6a12be2c5b60a95a06875b0b2c4f14228d1fa882 Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Wed, 12 Mar 2025 23:30:01 +
Subject: [PATCH] Fix EOF newlines.
Created using spr 1.3.6-beta.1
---
clang/test/Dri
https://github.com/JDevlieghere approved this pull request.
https://github.com/llvm/llvm-project/pull/141461
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https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/117036
>From b7fbe09b32ff02d4f7c52d82fbf8b5cd28138852 Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Wed, 23 Apr 2025 04:05:47 +
Subject: [PATCH] Address review comments.
Created using spr 1.3.6-beta.1
---
clang/l
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/141324
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@@ -1019,8 +1019,14 @@ LowerTypeTestsModule::importTypeId(StringRef TypeId) {
return C;
};
- if (TIL.TheKind != TypeTestResolution::Unsat)
-TIL.OffsetedGlobal = ImportGlobal("global_addr");
+ if (TIL.TheKind != TypeTestResolution::Unsat) {
+auto *GV = ImportGlo
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/141324
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@@ -33,8 +34,11 @@ PreservedAnalyses EmbedBitcodePass::run(Module &M,
ModuleAnalysisManager &AM) {
std::string Data;
raw_string_ostream OS(Data);
+ // Clone the module with with Thin LTO, since ThinLTOBitcodeWriterPass
changes
nikic wrote:
```suggestio
https://github.com/nikic approved this pull request.
Okay, let's go with this for now.
Compile-time impact of cloning the module is about 0.2% when building clang
with fat LTO:
https://llvm-compile-time-tracker.com/compare.php?from=11a01e851a06188ae946ace1140f866d7a667221&to=46e037d763e7997a83
https://github.com/nikic edited https://github.com/llvm/llvm-project/pull/13
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https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/141591
None
>From d102621b16b8c893c4b56248d9c4cf59b3e1bf6e Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH] [AMDGPU] Add KnownBits simplification combines to
RegBankCom
pcc wrote:
I'm fixing the code generation for the test cases that I'm adding
(inhibit-zext-constant-hoist.ll) which were all extracted from a build of a
large internal program built with CFI. Previously f1 looked like this where
align was hoisted:
```
f1: #
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/137975
>From ec1655b1fab18e3c2e13bc7b35ac1e151af4b615 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Wed, 30 Apr 2025 16:08:10 +0300
Subject: [PATCH] [BOLT] Gadget scanner: account for BRK when searching f
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/137975
>From ec1655b1fab18e3c2e13bc7b35ac1e151af4b615 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Wed, 30 Apr 2025 16:08:10 +0300
Subject: [PATCH] [BOLT] Gadget scanner: account for BRK when searching f
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/137224
>From 11094a446c4b193d5b5e3023cdd01de0e619 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Tue, 22 Apr 2025 21:43:14 +0300
Subject: [PATCH 1/2] [BOLT] Gadget scanner: detect untrusted LR before t
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/138884
>From 65f42b50bc58d2e5b78946bf82be3db9f5d63230 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Tue, 6 May 2025 11:31:03 +0300
Subject: [PATCH] [BOLT] Gadget scanner: prevent false positives due to ju
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/136183
>From 1bd54289ecbb513831c9b94adfc1822abf3deb73 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Thu, 17 Apr 2025 20:51:16 +0300
Subject: [PATCH 1/3] [BOLT] Gadget scanner: improve handling of unreacha
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/138883
>From daff3ce49a0272612af7d94d6be176a2c65e305c Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Wed, 7 May 2025 16:42:00 +0300
Subject: [PATCH] [BOLT] Introduce helpers to match `MCInst`s one at a tim
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/137224
>From 11094a446c4b193d5b5e3023cdd01de0e619 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Tue, 22 Apr 2025 21:43:14 +0300
Subject: [PATCH 1/2] [BOLT] Gadget scanner: detect untrusted LR before t
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/139778
>From d6536f26399b2c385821c65af779fc694e8eee72 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Tue, 13 May 2025 19:50:41 +0300
Subject: [PATCH] [BOLT] Gadget scanner: optionally assume auth traps on
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/138883
>From daff3ce49a0272612af7d94d6be176a2c65e305c Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Wed, 7 May 2025 16:42:00 +0300
Subject: [PATCH] [BOLT] Introduce helpers to match `MCInst`s one at a tim
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/139778
>From d6536f26399b2c385821c65af779fc694e8eee72 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Tue, 13 May 2025 19:50:41 +0300
Subject: [PATCH] [BOLT] Gadget scanner: optionally assume auth traps on
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/138884
>From 65f42b50bc58d2e5b78946bf82be3db9f5d63230 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Tue, 6 May 2025 11:31:03 +0300
Subject: [PATCH] [BOLT] Gadget scanner: prevent false positives due to ju
https://github.com/atrosinenko created
https://github.com/llvm/llvm-project/pull/141665
Perform trivial syntactical cleanups:
* make use of structured binding declarations
* use LLVM utility functions when appropriate
* omit braces around single expression inside single-line LLVM_DEBUG()
This p
atrosinenko wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/141665?utm_source=stack-comment-downstack-mergeability-warni
https://github.com/atrosinenko ready_for_review
https://github.com/llvm/llvm-project/pull/141665
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https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/136151
>From 25fda06fe3c11cd52ee67e0bbd42b6f8dc44921d Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Tue, 15 Apr 2025 21:47:18 +0300
Subject: [PATCH] [BOLT] Gadget scanner: do not crash on debug-printing C
@@ -534,8 +534,18 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
CmdArgs.push_back("-Bstatic");
- if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+ if (Triple.isRISCV()) {
+CmdAr
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 7b4708f1ddcd76bd8ba94b0c85317e86bab36ef7 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/125432
>From 7ba3e69a759f59bf746cb14640ea8ea426fa09fd Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 31 Jan 2025 13:12:56 -0500
Subject: [PATCH] [SelectionDAG][X86] Remove unused elements from atomic
vector.
After spl
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From ac4069c8fa8e69173b203824f4db5fbd73ecb5a4 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/138635
>From 109bc6009d93645b42e0be8fbf858368770f49e7 Mon Sep 17 00:00:00 2001
From: jofernau_amdeng
Date: Tue, 6 May 2025 01:48:11 -0400
Subject: [PATCH] [X86] Remove extra MOV after widening atomic load
This change ad
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/125432
>From 7ba3e69a759f59bf746cb14640ea8ea426fa09fd Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 31 Jan 2025 13:12:56 -0500
Subject: [PATCH] [SelectionDAG][X86] Remove unused elements from atomic
vector.
After spl
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From 39f039e23b95204affb61d1ac004c562f08222c5 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG] Widen <2 x T> vector types for atomic load
Vector types of
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/125432
>From 7ba3e69a759f59bf746cb14640ea8ea426fa09fd Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 31 Jan 2025 13:12:56 -0500
Subject: [PATCH] [SelectionDAG][X86] Remove unused elements from atomic
vector.
After spl
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From f91634795e4dbfd6e081f0b096b872411051ff0f Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG] Split vector types for atomic load
Vector types that aren'
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 85e5dc5e42cfe0f2f4875cb4db990f92b68295ed Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 87d478c96fa8e64c4a5035c467cc800d0c55df2c Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atom
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From f91634795e4dbfd6e081f0b096b872411051ff0f Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG] Split vector types for atomic load
Vector types that aren'
https://github.com/qinkunbao updated
https://github.com/llvm/llvm-project/pull/141640
>From cddba024f55d52e30d9c74369b3707b5fce64a20 Mon Sep 17 00:00:00 2001
From: Qinkun Bao
Date: Tue, 27 May 2025 17:34:51 +
Subject: [PATCH] Add some comments.
Created using spr 1.3.6
---
clang/lib/Basic/
https://github.com/qinkunbao edited
https://github.com/llvm/llvm-project/pull/141640
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https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 7b4708f1ddcd76bd8ba94b0c85317e86bab36ef7 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From 39f039e23b95204affb61d1ac004c562f08222c5 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG] Widen <2 x T> vector types for atomic load
Vector types of
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From ac4069c8fa8e69173b203824f4db5fbd73ecb5a4 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
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