================
@@ -102,6 +102,49 @@ class F2_4<bit annul, bit pred, dag outs, dag ins,
let Inst{13-0} = imm16{13-0};
}
+class F2_5<bit cc, dag outs, dag ins, string asmstr,
+ list<dag> pattern = [], InstrItinClass itin = NoItinerary>
+ : InstSP<outs, ins, asmstr, pattern, itin> {
+ bits<10> imm10;
+ bits<5> rs1;
+ bits<5> rs2;
+ bits<4> cond;
+
+ let op = 0; // op = 0
+
+ let Inst{29} = cond{3};
+ let Inst{28} = 1;
+ let Inst{27-25} = cond{2-0};
+ let Inst{24-22} = 0b011;
+ let Inst{21} = cc;
+ let Inst{20-19} = imm10{9-8};
+ let Inst{18-14} = rs1;
+ let Inst{13} = 0; // i = 0
+ let Inst{12-5} = imm10{7-0};
+ let Inst{4-0} = rs2;
+}
+
+class F2_6<bit cc, dag outs, dag ins, string asmstr,
+ list<dag> pattern = [], InstrItinClass itin = NoItinerary>
+ : InstSP<outs, ins, asmstr, pattern, itin> {
----------------
s-barannikov wrote:
```suggestion
: InstSP<outs, ins, asmstr, pattern, itin> {
```
https://github.com/llvm/llvm-project/pull/138403
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