https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 2d75ec2eb1a927513bb92bcb26e313a3831426ef Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/133627
>From bded004e4d4dbaf311de6d1bfbb2d443bad023cc Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 24 Mar 2025 14:33:36 +0700
Subject: [PATCH 1/2] llvm-reduce: Reduce with early return of arguments
Extend t
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 9d2612c4379eb827406642b508f2dce32fc13e59 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 2d75ec2eb1a927513bb92bcb26e313a3831426ef Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87574
>From 1d7ee612e408ee7e64e984eb08e6d7089a435d09 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Sun, 2 Feb 2025 00:58:49 +
Subject: [PATCH 1/4] Simplify MIR test.
Created using spr 1.3.6-beta.1
---
@@ -95,14 +95,24 @@ static MachineInstr *FindDominatedInstruction(MachineInstr
&New,
return Old;
}
+static bool isCodeMotionBarrier(MachineInstr &MI) {
+ return MI.hasUnmodeledSideEffects() && !MI.isPseudoProbe();
+}
+
/// Builds Instruction to its dominating order number
@@ -12603,6 +12603,18 @@ struct AAAddressSpaceImpl : public AAAddressSpace {
auto CheckAddressSpace = [&](Value &Obj) {
if (isa(&Obj))
return true;
+ // Some targets relax the requirement for alloca to be in an exact
address
+ // space, allowing it
shiltian wrote:
> In the real world, people emit address space 0 allocas all over the place and
> then report backend bugs when it fails in codegen
Technically we can avoid that by just hard error
https://github.com/llvm/llvm-project/pull/136865
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OCHyams wrote:
> Seems fine; although why's it needed for key instructions, I have a vague
> recollection that LLVM doesn't actually care about the source locations
> attached to PHIs?
The motivation came from reviewing code duplication sites to update for Key
Instructions, finding this, tryi
damyanp wrote:
Is this ready to retarget to main?
https://github.com/llvm/llvm-project/pull/136747
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@@ -4723,20 +4723,25 @@ def HLSLResourceBinding: InheritableAttr {
private:
RegisterType RegType;
- unsigned SlotNumber;
+ int SlotNumber; // -1 if the register slot was not specified
hekota wrote:
Good catch! DXC actually ignores the regist
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87575
>From 1a8d810d352fbe84c0521c7614689b60ade693c8 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Tue, 19 Nov 2024 15:25:34 -0800
Subject: [PATCH 1/5] Fixed the tests and addressed most of the review
comm
https://github.com/jmorse edited
https://github.com/llvm/llvm-project/pull/133495
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@@ -594,6 +599,25 @@ struct RootConstants {
sys::swapByteOrder(Num32BitValues);
}
};
+struct RootDescriptor_V1_0 {
inbelic wrote:
Having poked a bit more in `DXContainer.h`, maybe it would be best to follow
how it is done for `RuntimeInfo`? Defining a n
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 9d2612c4379eb827406642b508f2dce32fc13e59 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
jmorse wrote:
It can't hurt, let's making things slightly more correct!
https://github.com/llvm/llvm-project/pull/133492
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https://github.com/bogner approved this pull request.
https://github.com/llvm/llvm-project/pull/136751
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https://github.com/steakhal edited
https://github.com/llvm/llvm-project/pull/136589
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steakhal wrote:
Since I did the update to this PR the way I wanted, I invite another code owner
to approve. /cc @Xazax-hun
https://github.com/llvm/llvm-project/pull/136589
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https:
@@ -1867,6 +1867,30 @@ static StringRef getMIMnemonic(const MachineInstr &MI,
MCStreamer &Streamer) {
return Name;
}
+void AsmPrinter::emitIndirectCalleeLabels(
+FunctionInfo &FuncInfo,
+const MachineFunction::CallSiteInfoMap &CallSitesInfoMap,
+MachineInstr &MI
@@ -356,6 +356,13 @@ class AsmPrinter : public MachineFunctionPass {
DwarfUsesRelocationsAcrossSections = Enable;
}
+ /// Generate and emit labels for callees of the indirect callsites which will
+ /// be used to populate the .callgraph section.
+ void emitIndirectCal
@@ -1867,6 +1867,30 @@ static StringRef getMIMnemonic(const MachineInstr &MI,
MCStreamer &Streamer) {
return Name;
}
+void AsmPrinter::emitIndirectCalleeLabels(
+FunctionInfo &FuncInfo,
+const MachineFunction::CallSiteInfoMap &CallSitesInfoMap,
+MachineInstr &MI
@@ -95,14 +95,24 @@ static MachineInstr *FindDominatedInstruction(MachineInstr
&New,
return Old;
}
+static bool isCodeMotionBarrier(MachineInstr &MI) {
+ return MI.hasUnmodeledSideEffects() && !MI.isPseudoProbe();
+}
+
/// Builds Instruction to its dominating order number
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Diana Picus (rovka)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/136847.diff
2 Files Affected:
- (modified) llvm/lib/CodeGen/PrologEpilogInserter.cpp (+4-4)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterIn
@@ -0,0 +1,19 @@
+;; Tests that call site callee type ids can be extracted and set from
+;; callee_type metadata for indirect tail calls.
+
+;; Verify the exact calleeTypeId value to ensure it is not garbage but the
value
+;; computed as the type id from the callee_type metadata.
Author: Diana Picus
Date: 2025-04-23T13:04:37+02:00
New Revision: 334e3a844e6b02e400cc83fed2f71b3fe273a42e
URL:
https://github.com/llvm/llvm-project/commit/334e3a844e6b02e400cc83fed2f71b3fe273a42e
DIFF:
https://github.com/llvm/llvm-project/commit/334e3a844e6b02e400cc83fed2f71b3fe273a42e.diff
L
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
https://github.com/kbeyls edited
https://github.com/llvm/llvm-project/pull/134146
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@@ -0,0 +1,78 @@
+# RUN: llc %s --start-after=livedebugvalues --dwarf-use-key-instructions
--filetype=obj -o - \
+# RUN: | llvm-objdump -d - --no-show-raw-insn \
+# RUN: | FileCheck %s --check-prefix=OBJ
+
+# RUN: llc %s --start-after=livedebugvalues --dwarf-use-key-instructions
@@ -0,0 +1,117 @@
+; RUN: llc %s --filetype=obj -o - --dwarf-use-key-instructions \
+; RUN: | llvm-objdump -d - --no-show-raw-insn \
+; RUN: | FileCheck %s --check-prefix=OBJ
+
+; RUN: llc %s --filetype=obj -o - --dwarf-use-key-instructions \
+; RUN: | llvm-dwarfdump - --debug-lin
https://github.com/jmorse commented:
Tests: I'd personally prefer the input source and explanation at the top of the
file, although this is a style thing.
My understanding of this code is that within a basic block, it should be
possible for there to be two sequences of instructions of equal gr
@@ -339,6 +369,183 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
}
+ std::optional>
+ getAuthCheckedReg(BinaryBasicBlock &BB) const override {
+// Match several possible hard-coded sequences of instructions which can be
+// emitted by LLVM backend to
@@ -150,15 +138,11 @@ define amdgpu_kernel void @static_alloca_kernel(ptr %p) {
; GI-NEXT:v_mov_b32_e32 v1, s15
; GI-NEXT:s_mov_b32 s14, s16
; GI-NEXT:s_movk_i32 s32, 0x400
-; GI-NEXT:s_mov_b32 s36, 0
shiltian wrote:
That's why I explicitly add
https://github.com/jmorse approved this pull request.
I continued my ramblings inline; I see the potential for some slightly
unexpected stepping behaviour, but still strictly better than todays
"everything is a breakpoint" approach. I don't think I can put my finger on a
specific bad behaviour
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From b5f7d3d1f11da0b48fa5b634700c1bc539f4f413 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
@@ -1243,6 +1243,140 @@ TEST_F(DILocationTest, Merge) {
auto *M2 = DILocation::getMergedLocation(A2, B);
EXPECT_EQ(M1, M2);
}
+
+#ifdef EXPERIMENTAL_KEY_INSTRUCTIONS
+#define EXPECT_ATOM(Loc, Group, Rank)
\
+ EXPECT_EQ(Group,
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From b5f7d3d1f11da0b48fa5b634700c1bc539f4f413 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/jmorse approved this pull request.
LGTM with the style nits
https://github.com/llvm/llvm-project/pull/133478
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/136863
Backport 1ce709c
Requested by: @NickGuy-Arm
>From b1cf8e2bf71cd71ce8f5e3499563747bdd3e0b18 Mon Sep 17 00:00:00 2001
From: Nicholas Guy
Date: Wed, 23 Apr 2025 13:19:18 +0100
Subject: [PATCH] [LV] Fix crash when
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/136863
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llvmbot wrote:
@fhahn What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/136863
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@@ -1619,9 +1619,12 @@ class CodeGenModule : public CodeGenTypeCache {
llvm::Metadata *CreateMetadataIdentifierGeneralized(QualType T);
/// Create and attach type metadata to the given function.
- void CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD,
+ void cre
@@ -2860,9 +2861,25 @@ static void setLinkageForGV(llvm::GlobalValue *GV, const
NamedDecl *ND) {
GV->setLinkage(llvm::GlobalValue::ExternalWeakLinkage);
}
+static bool HasExistingGeneralizedTypeMD(llvm::Function *F) {
+ llvm::MDNode *MD = F->getMetadata(llvm::LLVMContext
@@ -73,24 +75,50 @@ struct ShaderHash {
std::vector Digest;
};
-#define ROOT_ELEMENT_FLAG(Num, Val) bool Val = false;
-
struct RootConstantsYaml {
uint32_t ShaderRegister;
uint32_t RegisterSpace;
uint32_t Num32BitValues;
};
+#define ROOT_DESCRIPTOR_FLAG(Num, Val
@@ -89,6 +111,15 @@ DXContainerYAML::RootSignatureYamlDesc::create(
return RootSigDesc;
}
+uint32_t DXContainerYAML::RootDescriptorYaml::getEncodedFlags() const {
+ uint64_t Flag = 0;
+#define ROOT_DESCRIPTOR_FLAG(Num, Val)
\
+ if (
@@ -594,6 +599,25 @@ struct RootConstants {
sys::swapByteOrder(Num32BitValues);
}
};
+struct RootDescriptor_V1_0 {
inbelic wrote:
IIUC, this is how the structs were defined and planned to be extended in DXC.
And I believe it was also documented there th
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/136732
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shiltian wrote:
> The A field does not assert anything about the content of the module. It does
> not assert that any alloca with a non-A valued alloca can be replaced with an
> A address space alloca. An alloca that does not match this address space is
> not invalid, and you cannot say anythi
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Sam Tebbs (SamTebbs33)
Changes
This PR adds support for extensions of different signedness to
VPMulAccumulateReductionRecipe and allows such partial reductions to be bundled
into that class.
---
Patch is 25.75 KiB, truncated t
https://github.com/jdoerfert commented:
Looks reasonable to me. I left one comment and I believe you can verify what is
best yourself.
https://github.com/llvm/llvm-project/pull/118878
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nikic wrote:
@shiltian I'm not entirely sure what you're asking here. As @arsenm said, the
alloca address space in the data layout is merely a hint on the address space
to use when materializing allocas "out of thin air". There are targets that use
multiple alloca address spaces, this just spe
https://github.com/jdoerfert edited
https://github.com/llvm/llvm-project/pull/118878
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@@ -9406,6 +9406,14 @@ StmtResult
TreeTransform::TransformOMPInformationalDirective(
D->getBeginLoc(), D->getEndLoc());
}
+template
+StmtResult TreeTransform::TransformOMPCompoundRootDirective(
+OMPCompoundRootDirective *D) {
+ // This function should never be fou
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
https://github.com/jmorse edited
https://github.com/llvm/llvm-project/pull/133495
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@@ -2087,13 +2095,18 @@ void DwarfDebug::beginInstruction(const MachineInstr
*MI) {
// If we have an ongoing unspecified location, nothing to do here.
if (!DL)
return;
-// We have an explicit location, same as the previous location.
-// But we might be co
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
https://github.com/jmorse commented:
I get the impression that `GroupCandidates` and `KeyInstructions` are being
kept strictly in sync; thus couldn't one instead just load KeyInstructions from
GroupCandidates once the scan is complete? This avoids filling up the dense map
with tombstones.
Am
https://github.com/SamTebbs33 created
https://github.com/llvm/llvm-project/pull/136997
This PR adds support for extensions of different signedness to
VPMulAccumulateReductionRecipe and allows such partial reductions to be bundled
into that class.
>From 10c4727074a7f5b4502ad08dc655be8fa5ffa3d2
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
Author: Diana Picus
Date: 2025-04-23T13:19:46+02:00
New Revision: be7adaf7ee21096215578816514b119da68e4cc8
URL:
https://github.com/llvm/llvm-project/commit/be7adaf7ee21096215578816514b119da68e4cc8
DIFF:
https://github.com/llvm/llvm-project/commit/be7adaf7ee21096215578816514b119da68e4cc8.diff
L
shiltian wrote:
> The address space should just come directly from the alloca. You don't know
> if it's correct to just replace the addrspace with whatever the datalayout
> says is the alloca addrspace. The datalayout value is for new allocas where
> the code has no additional context
If the
https://github.com/banach-space commented:
Thanks Momchil - this is great!
I skimmed through the pattern logic, and it's very neatly written. It's
actually quite easy to follow, despite the underlying logic being a bit
convoluted - well done! I've left a few minor suggestions, but nothing majo
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s -o -
| FileCheck %s
+
+declare void @bar(ptr)
+
+define i32 @static_alloca() {
+; CHECK-LAB
https://github.com/kbeyls commented:
Apologies for only reviewing piece-meal. I'm struggling a bit at the time to
reserve longer blocks of time to review this fully in one go.
I hope my comments still make sense though
https://github.com/llvm/llvm-project/pull/134146
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shiltian wrote:
> This looks like an attempt to fix up broken IR producers, but I guess that's
> not it?
Yeah, I initially thought that was broken IR too. At first, I was in favor of
not allowing alloca in AS0 at all and just making it a verifier error, like
what was done in
https://github.c
@@ -1129,13 +1130,17 @@ static void
cloneInstructionsIntoPredecessorBlockAndUpdateSSAUses(
Instruction *NewBonusInst = BonusInst.clone();
-if (!isa(BonusInst) &&
-PTI->getDebugLoc() != NewBonusInst->getDebugLoc()) {
- // Unless the instruction has the sa
https://github.com/jmorse edited
https://github.com/llvm/llvm-project/pull/133482
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shiltian wrote:
I've updated the PR to use `getAssumedAddrSpace`, which is same as what
`InferAddressSpacePass` does. @arsenm @nikic
https://github.com/llvm/llvm-project/pull/136865
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https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/136865
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@@ -339,6 +369,183 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
}
+ std::optional>
+ getAuthCheckedReg(BinaryBasicBlock &BB) const override {
+// Match several possible hard-coded sequences of instructions which can be
+// emitted by LLVM backend to
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s -o -
| FileCheck %s
+
+declare void @bar(ptr)
+
+define i32 @static_alloca() {
+; CHECK-LAB
@@ -95,14 +95,24 @@ static MachineInstr *FindDominatedInstruction(MachineInstr
&New,
return Old;
}
+static bool isCodeMotionBarrier(MachineInstr &MI) {
+ return MI.hasUnmodeledSideEffects() && !MI.isPseudoProbe();
+}
arsenm wrote:
Document this? What is t
@@ -1867,6 +1867,30 @@ static StringRef getMIMnemonic(const MachineInstr &MI,
MCStreamer &Streamer) {
return Name;
}
+void AsmPrinter::emitIndirectCalleeLabels(
+FunctionInfo &FuncInfo,
+const MachineFunction::CallSiteInfoMap &CallSitesInfoMap,
+MachineInstr &MI
https://github.com/Xazax-hun approved this pull request.
https://github.com/llvm/llvm-project/pull/136589
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@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -339,6 +369,183 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
}
+ std::optional>
+ getAuthCheckedReg(BinaryBasicBlock &BB) const override {
+// Match several possible hard-coded sequences of instructions which can be
+// emitted by LLVM backend to
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/136798
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shiltian wrote:
The LLVM Lang Ref says:
> The function of the data layout string may not be what you expect. Notably,
> this is not a specification from the frontend of what alignment the code
> generator should use.
>
> Instead, if specified, **the target data layout is required to match what
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s -o -
| FileCheck %s
+
+declare void @bar(ptr)
+
+define i32 @static_alloca() {
+; CHECK-LAB
redstar wrote:
@uweigand I made all the suggested changes.
https://github.com/llvm/llvm-project/pull/133799
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arsenm wrote:
> My reading is, it has to match the ultimate code generator. Middle end
> optimization relies on it to improve the code.
The definition of "match" leaves room for interpretation, and it would be a
better system if we allowed more dynamic configuration for some fields. However
t
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s -o -
| FileCheck %s
+
+declare void @bar(ptr)
+
+define i32 @static_alloca() {
+; CHECK-LAB
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s -o -
| FileCheck %s
+
+declare void @bar(ptr)
+
+define i32 @static_alloca() {
+; CHECK-LAB
https://github.com/jmorse edited
https://github.com/llvm/llvm-project/pull/133493
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@@ -0,0 +1,52 @@
+; RUN: opt -passes='require,function(codegenprepare)' -S
-mtriple=x86_64 < %s \
+; RUN: | FileCheck %s
+
+;; Check debug locations are propagated onto new PHIs.
jmorse wrote:
"...and that source locations have their atom groups remapped"
https
https://github.com/jmorse approved this pull request.
LGTM with nit
https://github.com/llvm/llvm-project/pull/133493
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@@ -951,6 +951,9 @@ bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned
SrcAS,
}
unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
+ if (isa(V))
shiltian wrote:
I don't think we need to differentiate them. It is either flat or pri
https://github.com/arsenm requested changes to this pull request.
The address space should just come directly from the alloca. You don't know if
it's correct to just replace the addrspace with whatever the datalayout says is
the alloca addrspace. The datalayout value is for new allocas where th
https://github.com/jmorse approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/133494
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@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/banach-space edited
https://github.com/llvm/llvm-project/pull/135636
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@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
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