================ @@ -4723,20 +4723,25 @@ def HLSLResourceBinding: InheritableAttr { private: RegisterType RegType; - unsigned SlotNumber; + int SlotNumber; // -1 if the register slot was not specified ---------------- hekota wrote:
Good catch! DXC actually ignores the register `u4294967295` and uses `u0` instead, but that is a bug. :) We should support the whole `uint32_t` range. https://github.com/llvm/llvm-project/pull/135287 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits