llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Diana Picus (rovka) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/136847.diff 2 Files Affected: - (modified) llvm/lib/CodeGen/PrologEpilogInserter.cpp (+4-4) - (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (+1-1) ``````````diff diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 9b852c0fd49cf..ac4090252cea0 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -608,9 +608,9 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock, MCRegister Reg = CS.getReg(); if (CS.isSpilledToReg()) { - BuildMI(SaveBlock, I, DebugLoc(), - TII.get(TargetOpcode::COPY), CS.getDstReg()) - .addReg(Reg, getKillRegState(true)); + BuildMI(SaveBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), + CS.getDstReg()) + .addReg(Reg, getKillRegState(true)); } else { const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.storeRegToStackSlot(SaveBlock, I, Reg, true, CS.getFrameIdx(), RC, @@ -637,7 +637,7 @@ static void insertCSRRestores(MachineBasicBlock &RestoreBlock, MCRegister Reg = CI.getReg(); if (CI.isSpilledToReg()) { BuildMI(RestoreBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), Reg) - .addReg(CI.getDstReg(), getKillRegState(true)); + .addReg(CI.getDstReg(), getKillRegState(true)); } else { const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC, diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index c1ac9491b2363..7838fd91a94da 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -2510,7 +2510,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, bool IsWWMRegSpill = TII->isWWMRegSpillOpcode(MI->getOpcode()); if (IsWWMRegSpill) { TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(), - RS->isRegUsed(AMDGPU::SCC)); + RS->isRegUsed(AMDGPU::SCC)); } buildSpillLoadStore( `````````` </details> https://github.com/llvm/llvm-project/pull/136847 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
