https://github.com/RKSimon approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/158274
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@@ -2926,6 +2929,20 @@ def HasLdsBarrierArriveAtomic :
Predicate<"Subtarget->hasLdsBarrierArriveAtomic(
def HasSetPrioIncWgInst : Predicate<"Subtarget->hasSetPrioIncWgInst()">,
AssemblerPredicate<(all_of FeatureSetPrioIncWgInst)>;
+def NeedsAlignedVGPRs : Predicate<"Subtarge
@@ -2926,6 +2929,20 @@ def HasLdsBarrierArriveAtomic :
Predicate<"Subtarget->hasLdsBarrierArriveAtomic(
def HasSetPrioIncWgInst : Predicate<"Subtarget->hasSetPrioIncWgInst()">,
AssemblerPredicate<(all_of FeatureSetPrioIncWgInst)>;
+def NeedsAlignedVGPRs : Predicate<"Subtarge
https://github.com/kasuga-fj updated
https://github.com/llvm/llvm-project/pull/158281
>From bdde305c338bffd9958f17e3a11a08f2bb30b5bf Mon Sep 17 00:00:00 2001
From: Ryotaro Kasuga
Date: Fri, 12 Sep 2025 11:06:39 +
Subject: [PATCH] [DA] Add test where WeakCrossingSIV misses dependency due to
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158278
>From 96a4d9030b00b30f6aa7d9a70b191c1aaab1f2e8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass
Th
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146074
>From 72a940883e91a0fc0c67454b1e01b8f96cae34ab Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 26 Jun 2025 06:10:35 -0400
Subject: [PATCH 1/2] [SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From fcaebb21fdbc19ada18e20902a4626ba9ace9f99 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by
defau
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 157f6a257a5771cff71fd5ea4be46251bd26d97f Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/5] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From b67b9c58a1612903f409cfdcec80e8565e4d5dc2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by
defau
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 395fdf948ee1864d6fc427e62db5433a5ef3eba0 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/5] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/s-barannikov edited
https://github.com/llvm/llvm-project/pull/158273
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158273
>From 5b8f38bb56b46b9e63fe2031f9b43e4bbba333fb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 6 Sep 2025 21:14:45 +0900
Subject: [PATCH 1/3] Mips: Switch to RegClassByHwMode
---
.../Target/Mips/AsmPar
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158278
>From 96a4d9030b00b30f6aa7d9a70b191c1aaab1f2e8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass
Th
https://github.com/s-barannikov approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/158273
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@@ -46,20 +46,8 @@ unsigned MipsRegisterInfo::getPICCallReg() { return
Mips::T9; }
const TargetRegisterClass *
MipsRegisterInfo::getPointerRegClass(unsigned Kind) const {
- MipsPtrClass PtrClassKind = static_cast(Kind);
-
- switch (PtrClassKind) {
- case MipsPtrClass::Defa
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158271
>From e7ef891fb2c4e21bec4d23af954ad9204f3eb48f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 8 Sep 2025 14:04:59 +0900
Subject: [PATCH] SPARC: Use RegClassByHwMode instead of PointerLikeRegClass
---
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158777
>From 0e5dfd5493a599e6eb9e5a0a0b21cd542c964e8f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 5 Sep 2025 18:03:59 +0900
Subject: [PATCH 1/3] PPC: Replace PointerLikeRegClass with RegClassByHwMode
---
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158273
>From 5b8f38bb56b46b9e63fe2031f9b43e4bbba333fb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 6 Sep 2025 21:14:45 +0900
Subject: [PATCH 1/3] Mips: Switch to RegClassByHwMode
---
.../Target/Mips/AsmPar
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158274
>From 7d3e2fa03f76098b2f4f90a2c4407e18d59423c5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 9 Sep 2025 11:15:47 +0900
Subject: [PATCH] X86: Switch to RegClassByHwMode
Replace the target uses of Point
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158274
>From 7d3e2fa03f76098b2f4f90a2c4407e18d59423c5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 9 Sep 2025 11:15:47 +0900
Subject: [PATCH] X86: Switch to RegClassByHwMode
Replace the target uses of Point
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158271
>From e7ef891fb2c4e21bec4d23af954ad9204f3eb48f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 8 Sep 2025 14:04:59 +0900
Subject: [PATCH] SPARC: Use RegClassByHwMode instead of PointerLikeRegClass
---
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
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https://github.com/ergawy updated
https://github.com/llvm/llvm-project/pull/156589
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@@ -916,6 +916,30 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned
RegNo, uint64_t Address,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
s-barannikov wrote:
Can you add a comment why
@@ -211,6 +211,21 @@ def FeatureUseIndirectJumpsHazard :
SubtargetFeature<"use-indirect-jump-hazard",
def FeatureStrictAlign
: SubtargetFeature<"strict-align", "StrictAlign", "true",
"Disable unaligned load store for r6">;
+//===-
https://github.com/mtrofin approved this pull request.
https://github.com/llvm/llvm-project/pull/158376
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https://github.com/s-barannikov approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/158271
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s-barannikov wrote:
They seem all lowercase to me :man_shrugging:
```
$ grep -E ": (Register)?Operand" llvm/lib/Target/PowerPC/*.td | cut -d ':' -f
2,3
def s16imm64 : Operand {
def u16imm64 : Operand {
def s17imm64 : Operand {
def tocentry : Operand {
def tlsreg : Operand {
def tlsgd : Operand
arsenm wrote:
Most of the operands seem capitalized
https://github.com/llvm/llvm-project/pull/158777
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https://github.com/s-barannikov edited
https://github.com/llvm/llvm-project/pull/158777
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https://github.com/s-barannikov approved this pull request.
LGTM
Is there a reason to not implement the renaming suggestion? (Like it would
require renaming methods in C++ files or so or make the naming inconsistent.)
https://github.com/llvm/llvm-project/pull/158777
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156841
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llvmbot wrote:
@llvm/pr-subscribers-backend-hexagon
Author: Matt Arsenault (arsenm)
Changes
Both conceptually belong to the same subtarget, so it should not
be necessary to pass in the context TargetRegisterInfo to any
TargetInstrInfo member. Add this reference so those superfluous
argumen
@@ -261,55 +262,106 @@ void FlowAwareEmbedder::computeEmbeddings(const
BasicBlock &BB) const {
BBVecMap[&BB] = BBVector;
}
+//
==--===//
+// VocabStorage
+//===-
https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/159655
>From 108bf356e743d36b4eb5d0217720cf47ab85f33f Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Thu, 18 Sep 2025 14:31:38 -0700
Subject: [PATCH 1/2] [HLSL] NonUniformResourceIndex implementation
Adds HLSL funct
@@ -301,12 +380,16 @@ class Vocabulary {
constexpr static unsigned NumCanonicalEntries =
MaxOpcodes + MaxCanonicalTypeIDs + MaxOperandKinds + MaxPredicateKinds;
- // Base offsets for slot layout to simplify index computation
+ // Base offsets for flat index computati
@@ -1272,6 +1272,57 @@ void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E,
llvm::Value *Bound,
EmitCheck(std::make_pair(Check, CheckKind), CheckHandler, StaticData, Index);
}
+static bool
+typeContainsPointer(QualType T,
+llvm::SmallPtrSet &VisitedR
mtrofin wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/159645?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/ergawy updated
https://github.com/llvm/llvm-project/pull/156610
>From 3b73016ad3984069441409516598caf1161c7448 Mon Sep 17 00:00:00 2001
From: ergawy
Date: Tue, 2 Sep 2025 08:36:34 -0500
Subject: [PATCH] [flang][OpenMP] `do concurrent`: support `reduce` on device
Extends `do
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/157232
>From d749f30964e57caa797b3df87ae88ffc3d4a2f54 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Sun, 7 Sep 2025 17:39:19 +
Subject: [PATCH 1/3] feedback
Created using spr 1.3.6
---
llvm/test/MC/C
https://github.com/svkeerthy edited
https://github.com/llvm/llvm-project/pull/158376
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https://github.com/ilovepi approved this pull request.
LGTM. IMO this is a much nicer way to test a property on `stdin`'s positioning.
Lets get a bit more consensus from other maintainers before landing though.
https://github.com/llvm/llvm-project/pull/157232
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https://github.com/llvm/llvm-project/pull/159641
None
>From 344bfe15f023e965348da4d92738b48683768887 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 18 Sep 2025 12:58:41 -0700
Subject: [PATCH] [AMDGPU] gfx1251 VOP2 dpp support
---
llvm/lib/
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158274
>From 1a85c9cf7cdf944be302c00efd231eba5d46bdc6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 9 Sep 2025 11:15:47 +0900
Subject: [PATCH] X86: Switch to RegClassByHwMode
Replace the target uses of Point
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Helena Kotas (hekota)
Changes
Adds HLSL function NonUniformResourceIndex to hlsl_intrinsics.h. The function
calls a builtin `__builtin_hlsl_resource_nonuniformindex` which gets translated
to LLVM intrinsic `llvm.{dx|spv}.resource_nonunifo
llvmbot wrote:
@llvm/pr-subscribers-hlsl
@llvm/pr-subscribers-clang-codegen
Author: Helena Kotas (hekota)
Changes
Adds HLSL function NonUniformResourceIndex to hlsl_intrinsics.h. The function
calls a builtin `__builtin_hlsl_resource_nonuniformindex` which gets translated
to LLVM intrinsi
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: Helena Kotas (hekota)
Changes
Adds HLSL function NonUniformResourceIndex to hlsl_intrinsics.h. The function
calls a builtin `__builtin_hlsl_resource_nonuniformindex` which gets translated
to LLVM intrinsic `llvm.{dx|spv}.resource_no
https://github.com/hekota created
https://github.com/llvm/llvm-project/pull/159655
Adds HLSL function NonUniformResourceIndex to hlsl_intrinsics.h. The function
calls a builtin `__builtin_hlsl_resource_nonuniformindex` which gets translated
to LLVM intrinsic `llvm.{dx|spv}.resource_nonuniformi
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/159654?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/159654
None
>From b83405b879b471da983f885bfdffb3d1f58130de Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 18 Sep 2025 14:30:20 -0700
Subject: [PATCH] [AMDGPU] gfx1251 VOP3 dpp support
---
llvm/lib/
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Mircea Trofin (mtrofin)
Changes
---
Patch is 21.02 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/159645.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Utils/SimplifyCFG.
Author: MaheshRavishankar
Date: 2025-09-18T13:49:24-07:00
New Revision: 301f09f236c1439c9313ebc2dda1193d210ab698
URL:
https://github.com/llvm/llvm-project/commit/301f09f236c1439c9313ebc2dda1193d210ab698
DIFF:
https://github.com/llvm/llvm-project/commit/301f09f236c1439c9313ebc2dda1193d210ab698.d
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/159641
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@@ -1,5 +1,5 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=simplifycfg
-simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --ch
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/159645
>From 6d3342f397d39e366a06eb6bcabddec0b3d5a963 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Mon, 15 Sep 2025 17:49:18 +
Subject: [PATCH] [profcheck][SimplifyCFG] Propagate !prof from `switch` to
`sele
https://github.com/mtrofin edited
https://github.com/llvm/llvm-project/pull/159645
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github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff origin/main HEAD --extensions cpp --
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``
https://github.com/mtrofin ready_for_review
https://github.com/llvm/llvm-project/pull/159645
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https://github.com/llvm/llvm-project/pull/159645
None
>From 92728fa5d41bd5f6ef63837bcb3ea8e85b7a8764 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Mon, 15 Sep 2025 17:49:18 +
Subject: [PATCH] [profcheck][SimplifyCFG] Propagate !prof from `switch` to
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Stanislav Mekhanoshin (rampitec)
Changes
---
Patch is 22.81 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/159641.diff
5 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/VOP2Ins
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/159641?utm_source=stack-comment-downstack-mergeability-warning"
@@ -1070,8 +1070,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
<< " explicit " << ClassName
- << "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode = ~0u, "
-
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/159632
>From 7bb9fb5b3b9a2dfcd1d00f01c86fe26c5d14c30f Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 18 Sep 2025 08:49:38 -0500
Subject: [PATCH] [flang][OpenMP] Use OmpDirectiveSpecification in
THREADP
llvmbot wrote:
@llvm/pr-subscribers-flang-semantics
Author: Krzysztof Parzyszek (kparzysz)
Changes
Since ODS doesn't store a list of OmpObjects (i.e. not as OmpObjectList), some
semantics-checking functions needed to be updated to operate on a single object
at a time.
---
Full diff: htt
https://github.com/kparzysz created
https://github.com/llvm/llvm-project/pull/159632
Since ODS doesn't store a list of OmpObjects (i.e. not as OmpObjectList), some
semantics-checking functions needed to be updated to operate on a single object
at a time.
>From 7bb9fb5b3b9a2dfcd1d00f01c86fe26c
pcc wrote:
> What is the reasoning behind this? Could we document something when to apply
> the attribute?
I added this to types which are commonly used, as mentioned in the commit
message. I will document that in the coding guidelines.
https://github.com/llvm/llvm-project/pull/151652
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https://github.com/llvm/llvm-project/pull/157754
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https://github.com/tobias-stadler updated
https://github.com/llvm/llvm-project/pull/156715
>From d33b31f01aeeb9005581b0a2a1f21c898463aa02 Mon Sep 17 00:00:00 2001
From: Tobias Stadler
Date: Thu, 18 Sep 2025 12:34:55 +0100
Subject: [PATCH 1/3] Replace bitstream blobs by yaml
Created using spr 1
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156840
>From 14c75441e84aa32e4f5876598b9a2c59d4ecbe65 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 21:32:21 +0200
Subject: [PATCH 1/2] fixup! fix for incomplete types
Created using spr 1.3.8-beta.1
@@ -47,74 +47,61 @@ static func::FuncOp getOrDeclare(fir::FirOpBuilder
&builder, Location loc,
return func;
}
-static bool isZero(Value v) {
- if (auto cst = v.getDefiningOp())
-if (auto attr = dyn_cast(cst.getValue()))
- return attr.getValue().isZero();
- return
@@ -175,12 +176,20 @@ PowIStrengthReduction::matchAndRewrite(
Value one;
Type opType = getElementTypeOrSelf(op.getType());
- if constexpr (std::is_same_v)
+ if constexpr (std::is_same_v) {
one = arith::ConstantOp::create(rewriter, loc,
@@ -1272,7 +1272,18 @@ mlir::Value genMathOp(fir::FirOpBuilder &builder,
mlir::Location loc,
LLVM_DEBUG(llvm::dbgs() << "Generating '" << mathLibFuncName
<< "' operation with type ";
mathLibFuncType.dump(); llvm::dbgs() << "\n");
https://github.com/TIFitis updated
https://github.com/llvm/llvm-project/pull/158722
>From 6976910364aa2fe18603aefcb27b10bd0120513d Mon Sep 17 00:00:00 2001
From: Akash Banerjee
Date: Mon, 15 Sep 2025 20:35:29 +0100
Subject: [PATCH 1/7] Add complex.powi op.
---
flang/lib/Optimizer/Builder/Intr
https://github.com/mgorny milestoned
https://github.com/llvm/llvm-project/pull/157848
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in the release notes (completely optional). Please reply to this comment with a
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release:note label to this PR.
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/158224
Both conceptually belong to the same subtarget, so it should not
be necessary to pass in the context TargetRegisterInfo to any
TargetInstrInfo member. Add this reference so those superfluous
arguments can be remov
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/158246
This is special for the same reason av_mov_b64_imm_pseudo is special.
>From e5032294b4979c4b7f2367cee30c24d42901714b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 5 Sep 2025 17:27:37 +0900
Subject: [P
https://github.com/efriedma-quic commented:
Can you split "implement basic codegen support for prefalign" (the bits which
don't depend on the .prefalign directive) into a separate patch? It's not
clear what's causing the test changes here.
https://github.com/llvm/llvm-project/pull/155529
https://github.com/joaosaffran updated
https://github.com/llvm/llvm-project/pull/153287
>From b1e34ff07fffe96fec438b87027bd2c450b6b36f Mon Sep 17 00:00:00 2001
From: Joao Saffran <{ID}+{username}@users.noreply.github.com>
Date: Tue, 12 Aug 2025 13:07:42 -0700
Subject: [PATCH 01/24] adding valida
https://github.com/vpykhtin updated
https://github.com/llvm/llvm-project/pull/150937
>From ae3589e2c93351349cd1bbb5586c2dfcb075ea68 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Thu, 10 Apr 2025 11:58:13 +
Subject: [PATCH] amdgpu_use_ssaupdaterbulk_in_structurizecfg
---
llvm/lib/Tra
https://github.com/RossBrunton converted_to_draft
https://github.com/llvm/llvm-project/pull/157651
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Author: MaheshRavishankar
Date: 2025-09-18T09:29:29-07:00
New Revision: 7af3f6e0317e84900e6683ac0ea3dc60b805904e
URL:
https://github.com/llvm/llvm-project/commit/7af3f6e0317e84900e6683ac0ea3dc60b805904e
DIFF:
https://github.com/llvm/llvm-project/commit/7af3f6e0317e84900e6683ac0ea3dc60b805904e.d
https://github.com/MacDue updated
https://github.com/llvm/llvm-project/pull/142391
>From 0dfb0725e2a4f82af47821946bfbbfcd7ed08e10 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell
Date: Thu, 8 May 2025 17:38:27 +
Subject: [PATCH] [AArch64] Prepare for split ZPR and PPR area allocation
(NFCI)
https://github.com/vzakhari commented:
LGTM with some final comments.
https://github.com/llvm/llvm-project/pull/158722
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https://github.com/vzakhari edited
https://github.com/llvm/llvm-project/pull/158722
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@@ -175,12 +176,20 @@ PowIStrengthReduction::matchAndRewrite(
Value one;
Type opType = getElementTypeOrSelf(op.getType());
- if constexpr (std::is_same_v)
+ if constexpr (std::is_same_v) {
one = arith::ConstantOp::create(rewriter, loc,
@@ -1272,7 +1272,18 @@ mlir::Value genMathOp(fir::FirOpBuilder &builder,
mlir::Location loc,
LLVM_DEBUG(llvm::dbgs() << "Generating '" << mathLibFuncName
<< "' operation with type ";
mathLibFuncType.dump(); llvm::dbgs() << "\n");
https://github.com/tobias-stadler updated
https://github.com/llvm/llvm-project/pull/156715
>From d33b31f01aeeb9005581b0a2a1f21c898463aa02 Mon Sep 17 00:00:00 2001
From: Tobias Stadler
Date: Thu, 18 Sep 2025 12:34:55 +0100
Subject: [PATCH 1/2] Replace bitstream blobs by yaml
Created using spr 1
https://github.com/vpykhtin updated
https://github.com/llvm/llvm-project/pull/150937
>From ae3589e2c93351349cd1bbb5586c2dfcb075ea68 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Thu, 10 Apr 2025 11:58:13 +
Subject: [PATCH] amdgpu_use_ssaupdaterbulk_in_structurizecfg
---
llvm/lib/Tra
TIFitis wrote:
> The `powi` part looks good to me. Are you planning to merge it, and then
> rebase the other PR for the Flang changes for the final review?
I plan on landing both PRs at once. This PR depends on #158642, which should
land first.
All the work should have been in a single PR but
https://github.com/TIFitis edited
https://github.com/llvm/llvm-project/pull/158722
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@@ -47,74 +47,61 @@ static func::FuncOp getOrDeclare(fir::FirOpBuilder
&builder, Location loc,
return func;
}
-static bool isZero(Value v) {
- if (auto cst = v.getDefiningOp())
-if (auto attr = dyn_cast(cst.getValue()))
- return attr.getValue().isZero();
- return
https://github.com/jdenny-ornl edited
https://github.com/llvm/llvm-project/pull/159163
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https://github.com/TIFitis updated
https://github.com/llvm/llvm-project/pull/158722
>From 6976910364aa2fe18603aefcb27b10bd0120513d Mon Sep 17 00:00:00 2001
From: Akash Banerjee
Date: Mon, 15 Sep 2025 20:35:29 +0100
Subject: [PATCH 1/6] Add complex.powi op.
---
flang/lib/Optimizer/Builder/Intr
@@ -1349,6 +1350,98 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
CB->setMetadata(llvm::LLVMContext::MD_alloc_token_hint, MDN);
}
+/// Infer type from a simple sizeof expression.
+static QualType inferTypeFromSizeofExpr(const Expr *E) {
+ const Expr *Arg
https://github.com/vzakhari approved this pull request.
The `powi` part looks good to me. Are you planning to merge it, and then
rebase the other PR for the Flang changes for the final review?
https://github.com/llvm/llvm-project/pull/158722
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https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 7c417c4c1413a3807d476b7fc490256084a0ac62 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/5] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 7c417c4c1413a3807d476b7fc490256084a0ac62 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/5] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145330
>From da5b337fef36cdee209845b51bba323e84272334 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 04:03:53 -0400
Subject: [PATCH 1/2] [AMDGPU][SDAG] Handle ISD::PTRADD in various special
cas
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