[Lldb-commits] [PATCH] D154705: [lldb][AArch64] Fix flakiness in TestSVEThreadedDynamic

DavidSpickett created this revision. Herald added a subscriber: kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. This test runs to a breakpoint on thread 0. Thread 0 then starts threa

[Lldb-commits] [PATCH] D154705: [lldb][AArch64] Fix flakiness in TestSVEThreadedDynamic

DavidSpickett added a comment. My brain says this is not a good way to ensure a state, but I couldn't think of anything that wouldn't have its own race conditions. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154705/new/ https://reviews.llvm.org/

[Lldb-commits] [PATCH] D154757: [lldb][NFCI] TestEmulation should take a Stream ref

DavidSpickett added a reviewer: DavidSpickett. DavidSpickett accepted this revision. DavidSpickett added a comment. This revision is now accepted and ready to land. LGTM. Always happy to see never-null pointers get updated. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https

[Lldb-commits] [PATCH] D154823: [lldb][AArch64] Add test predicate for systems with SME enabled

DavidSpickett created this revision. Herald added a subscriber: kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. "sme" is just one of many cpuinfo features for SME but it's the only o

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett created this revision. Herald added subscribers: ctetreau, kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added subscribers: lldb-commits, alextsao1999. Herald added a project: LLDB. The Scalable Matrix Extension (SME) adds a new S

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett created this revision. Herald added subscribers: ctetreau, kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added subscribers: lldb-commits, alextsao1999. Herald added a project: LLDB. Software can tell if it is in streaming SVE mode

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett created this revision. Herald added a subscriber: kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. This changes the TLS regset to not only be dynamic in that it could ex

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett added a reviewer: omjavaid. DavidSpickett added a comment. Feel free to bombard me with questions about SME, if it's quicker than reading the entire spec yourself. It has some quirks to it for sure. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett added a comment. > SIMD registers must be read and written via the SVE regset when in SSVE mode. > Writing to them exits streaming mode. In my testing it did actually work if you always used the current mode. I think that's an artifact of QEMU or the kernel's implementation choice

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett added a comment. > You mention a couple of times that when in SSVE mode, we can only write to > the SVE registers and doing so forces the processor out of SSVE Mode. We can > read the SSVE registers while in SSVE mode though right? We are always able to read the header for either

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett added a comment. > Then we have SIMD (v0-31) which is a bit of a wrench in this. We must read > SIMD via the SVE regset even while SSVE is active, but writing to that same > set brings us out of SSVE mode (into SIMD mode, I think, but it could just be > SVE mode). In my testing i

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett created this revision. Herald added subscribers: ctetreau, kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. Reading the SVE registers of streaming mode from non-streamin

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett added inline comments. Comment at: lldb/test/API/linux/aarch64/tls_registers/TestAArch64LinuxTLSRegisters.py:73 + +@skipUnlessArch("aarch64") +@skipUnlessPlatform(["linux"]) omjavaid wrote: > These three tests have a lot of commonalities ma

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett planned changes to this revision. DavidSpickett added a comment. > As you say above, we can show svg when in non-streaming mode but we can't > show vg when in streaming mode. Should we only show a single vg for the > currently-available registers? I will admit I don't have practic

[Lldb-commits] [PATCH] D154705: [lldb][AArch64] Fix flakiness in TestSVEThreadedDynamic

This revision was automatically updated to reflect the committed changes. Closed by commit rGfdf36c3d4b46: [lldb][AArch64] Fix flakiness in TestSVEThreadedDynamic (authored by DavidSpickett). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154705/new/

[Lldb-commits] [PATCH] D154823: [lldb][AArch64] Add test predicate for systems with SME enabled

This revision was automatically updated to reflect the committed changes. Closed by commit rG3ebd6f65cb87: [lldb][AArch64] Add test predicate for systems with SME enabled (authored by DavidSpickett). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D1548

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > Could you offer higher abstractions? Show me the current SVME vector length? > Show me the current SVME mode? Adding it to `process status` is along those lines, we have stuff like the number of addressable bits there right now. Overall I prefer the registers r

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > I would never question giving low-level access to the registers. Well in your defense, both `svg` and `svcr` will actually be pseudo registers. So the user isn't getting access to the "real" ones either way, we're emulating the behaviour with ptrace commands. >

[Lldb-commits] [PATCH] D155256: Add fs_base/gs_base support for Linux

DavidSpickett added a comment. Caveat: I have 0 prior knowledge about these registers. What's the testing story here? I see one for fs_base on a live process but none for gs_base and neither for core files. If one test can hit all the code paths those would hit, then fine, but otherwise this ne

[Lldb-commits] [PATCH] D155107: Add support for llvm::MCInstPrinter::setPrintBranchImmAsAddress

DavidSpickett added a comment. Also you can test it as long as you put the right skipif annotations on it as it'll be architecture specific. Or use a corefile and just check that the backend for that architecture is enabled. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION ht

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. I think in https://reviews.llvm.org/D154926, `lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py` addresses this. If what you mean is you are stopped in streaming mode, you evaluate an expression that may cal

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > As a simplification of all of this, and to avoid using g/G, we added > QSaveRegisterState which tells the stub (debugserver etc) to save the current > register context, and then after the inferior function call has completed, > QRestoreRegisterState to restore t

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > I suspect that it may be the case that for example, writing to the bottom 128 > bits of streaming mode z0 may not be reflected in the SIMD unit's v0. Or at > least, one could build a core that acted that way. But the user would be very confused by this given tha

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett added a comment. > I am talking to our kernel folks to understand the background to that. The result is that yes cores an implement it as separate state but as mentioned here, taking that into account in lldb would be rather confusing in 99% of situations. If we simply want to rea

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett updated this revision to Diff 541520. DavidSpickett added a comment. Turns out I was misinterpreting this setence from the kernel docs: Note that when SME is present and streaming SVE mode is in use the FPSIMD subset of registers will be read via NT_ARM_SVE and NT_ARM_SVE writes

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett updated this revision to Diff 541526. DavidSpickett added a comment. Address some comments from the previous version. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154926/new/ https://reviews.llvm.org/D154926 Files: lldb/source/Plu

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett marked 3 inline comments as done. DavidSpickett added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:422 +m_sve_state = SVEState::Unknown; +m_sve_state_data.Invalidate(); +m_ssve_state_dat

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett marked 4 inline comments as done. DavidSpickett added inline comments. Comment at: lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py:1 +""" +Test that LLDB correctly reads and writes AArch64 SIMD registers in SVE, -

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett added a comment. On the off chance anyone was going to try and run this, you'll need a kernel that includes https://lore.kernel.org/lkml/20230713-arm64-fix-sve-sme-vl-change-v1-3-129dd8611...@kernel.org/T/. This fixes a bug found while writing these tests. Repository: rG LLVM

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett updated this revision to Diff 541540. DavidSpickett added a comment. Rebase, fix typo. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154927/new/ https://reviews.llvm.org/D154927 Files: lldb/source/Plugins/Process/Linux/NativeRegist

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett marked an inline comment as done. DavidSpickett added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:1003 + // Bit 2 indicates whether the array storage is active (not yet implemented). + m_sme_ctrl_reg = m_sve

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett updated this revision to Diff 541542. DavidSpickett marked an inline comment as done. DavidSpickett added a comment. Add missing newline. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154927/new/ https://reviews.llvm.org/D154927 File

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett added inline comments. Comment at: lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py:30 +"0x000" + expected_value]) + p_reg_size = int(z_reg_size / 8) Thi

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett updated this revision to Diff 541548. DavidSpickett added a comment. Add "Buffer" to method names. enabled -> present in skipped messages. I realised that "enabled" is ambiguous does it mean enabled in the CPU or in the process, present is more clearly meaning is it on the CPU at al

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett updated this revision to Diff 541570. DavidSpickett added a comment. Note the behaviour of tpidr2 on a system without SME. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154930/new/ https://reviews.llvm.org/D154930 Files: lldb/sourc

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett added inline comments. Comment at: lldb/test/API/linux/aarch64/tls_registers/TestAArch64LinuxTLSRegisters.py:73 + +@skipUnlessArch("aarch64") +@skipUnlessPlatform(["linux"]) DavidSpickett wrote: > omjavaid wrote: > > These three tests have

[Lldb-commits] [PATCH] D155256: [lldb][x86_64] Add fs_base/gs_base support for Linux

DavidSpickett added inline comments. Comment at: lldb/test/API/commands/register/register/register_command/TestRegisters.py:613 +def test_fs_gs_base(self): +"""Tests fs_base register can be read and equals to pthread_self() return value.""" +self.build() ---

[Lldb-commits] [PATCH] D155256: [lldb][x86_64] Add fs_base/gs_base support for Linux

DavidSpickett added inline comments. Comment at: lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py:647 +self.assertTrue(reg_gs_base.IsValid(), "gs_base is not available") +# The fs_base/gs_base registers in linux-x86_64.core are both zero. +

[Lldb-commits] [PATCH] D155256: [lldb][x86_64] Add fs_base/gs_base support for Linux

DavidSpickett added a comment. Tests LGTM, thanks. @clayborg please approve if they look good to you. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155256/new/ https://reviews.llvm.org/D155256 ___ lldb-

[Lldb-commits] [PATCH] D155768: [lldb] [NFC] Remove some dead code from Watchpoint class, and a method that makes no sense

DavidSpickett accepted this revision. DavidSpickett added a comment. This revision is now accepted and ready to land. I don't understand the logic for if the hit counter is < the number of false alarms. I'm not even sure that's possible given that a false alarm would have to come from a reported

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett marked 2 inline comments as done. DavidSpickett added a comment. Thanks for the review, I'll try making the test a bit more flexible so we can read both registers at once for a bit more coverage. Comment at: lldb/test/API/linux/aarch64/tls_registers/TestAArch64L

[Lldb-commits] [PATCH] D155905: lldb RFC: Exposing set/get address masks, Fix*Address methods in SBProcess

DavidSpickett added a comment. The only part of this that's maybe tricky is the HighMem parts of it. Given the niche use case it should be ok if they turn out a bit awkward for general use. You are missing a way to fix a high mem address, is that intentional? Or would you get the high mem mask,

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

DavidSpickett planned changes to this revision. DavidSpickett added a comment. In some sense it already is, it'll go in after the streaming mode SVE registers. Should we wait until we can show the full content including the ZA bit? Yeah, why not, we're in no rush. I have a patch locally for ZA

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett updated this revision to Diff 542910. DavidSpickett added a comment. Refactor the test so there are tests for: - reading tpidr on non-SME systems - reading tpidr and tpidr2 on SME systems - tpidr2 not being present on non-SME systems You could try to fold the last one into the firs

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett updated this revision to Diff 542911. DavidSpickett added a comment. Correct missing "tls" in test name. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154930/new/ https://reviews.llvm.org/D154930 Files: lldb/source/Plugins/Process/

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett marked an inline comment as done. DavidSpickett added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:81 opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSVE); + // We may also have the Scalable M

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett updated this revision to Diff 542930. DavidSpickett marked an inline comment as done. DavidSpickett added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154926/new/ https://reviews.llvm.org/D154926 Files: lldb/sou

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

DavidSpickett updated this revision to Diff 542932. DavidSpickett added a comment. Rebase and put this after the SSVE registers patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154930/new/ https://reviews.llvm.org/D154930 Files: lldb/source/

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

DavidSpickett added a comment. I will land this and the next patch once the 17 branch has been taken. I don't want SME changes on 17 with A: not enough testing and B: missing features (ZA). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154926/new/

[Lldb-commits] [PATCH] D155256: [lldb][x86_64] Add fs_base/gs_base support for Linux

DavidSpickett added a comment. If you feel it's significant enough, it is worth adding a release note in `llvm/docs/ReleaseNotes.rst` before/on to the llvm 17 branch is taken. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155256/new/ https://revie

[Lldb-commits] [PATCH] D156086: [lldb][NFC] Use MCInstrAnalysis when available in the disassembler plugin

DavidSpickett added a comment. What I understand is that `MCInstrAnalysis` defaults to using `MCInstrDesc`, however not all targets have `MCInstrAnalysis` at all. So we have this awkwardness here with the two pointers, which is fine. Sounds good to me, I am just wondering about the changes over

[Lldb-commits] [PATCH] D156118: [lldb][AArch64] Add reading of TLS tpidr register from core files

DavidSpickett created this revision. Herald added a subscriber: kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added subscribers: lldb-commits, alextsao1999. Herald added a project: LLDB. 7e229217f4215b519b886e7881bae4da3742a7d2

[Lldb-commits] [PATCH] D156118: [lldb][AArch64] Add reading of TLS tpidr register from core files

DavidSpickett added a reviewer: omjavaid. DavidSpickett added a comment. Herald added a subscriber: JDevlieghere. I wanted to add tpidr to the release notes and realised I left it half finished. Will update the release notes afterwards on branch or main depending on when this lands. Repository

[Lldb-commits] [PATCH] D156118: [lldb][AArch64] Add reading of TLS tpidr register from core files

DavidSpickett updated this revision to Diff 543587. DavidSpickett added a comment. Lower stack limit when making corefile to shrink it some. 16k was about as low as I could go before it failed to even get to the program itself. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION h

[Lldb-commits] [PATCH] D156118: [lldb][AArch64] Add reading of TLS tpidr register from core files

DavidSpickett updated this revision to Diff 543999. DavidSpickett added a comment. Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Rebase, add release note before I forget. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156118/

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

This revision was automatically updated to reflect the committed changes. Closed by commit rG03d8cd1d722d: [lldb][AArch64] Add support for SME's SVE streaming mode registers (authored by DavidSpickett). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D1

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGefa43d785ee6: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME (authored by DavidSpickett). Changed prior to commit: https://review

[Lldb-commits] [PATCH] D155107: Add support for llvm::MCInstPrinter::setPrintBranchImmAsAddress

DavidSpickett accepted this revision. DavidSpickett added a comment. > Also you can test it as long as you put the right skipif annotations on it as > it'll be architecture specific. Or use a corefile and just check that the > backend for that architecture is enabled. Given that: - We are a th

[Lldb-commits] [PATCH] D155905: lldb RFC: Exposing set/get address masks, Fix*Address methods in SBProcess

DavidSpickett added a comment. > I like it the above approach with more enums for the high and low code/data. > Not sure if eTypeAny makes sense in the GetAddressMask(eTypeAny) scenario It could be like the `FixAny` method, a fallback when you don't know either way. `eTypeAny` returns `FixAnyAd

[Lldb-commits] [PATCH] D155905: lldb RFC: Exposing set/get address masks, Fix*Address methods in SBProcess

DavidSpickett added a comment. > but I could imagine some harvard architecture target that behaved differently > (surely this is why Linux has two address masks) I'm not privy to the exact reasoning, but at least part of it comes from the architecture itself. You could have a target that enable

[Lldb-commits] [PATCH] D155905: lldb RFC: Exposing set/get address masks, Fix*Address methods in SBProcess

DavidSpickett added a comment. And +1 to the enum. This mitigates the MacOS specific-ness of the high and low masks at this time, and makes expansion easier if we do manage to generalise them later. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D15

[Lldb-commits] [PATCH] D155269: [lldb][AArch64] Add SME streaming vector length pseudo register

DavidSpickett abandoned this revision. DavidSpickett added a comment. Turns out that for ZA support, we need to know the streaming vector length regardless of current mode. So SVG will be implemented as part of ZA support instead. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTIO

[Lldb-commits] [PATCH] D156512: [lldb][AArch64] Save/restore TLS registers around expressions

DavidSpickett created this revision. Herald added a subscriber: kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. Previously we were storing them but not restoring them. This fixes tha

[Lldb-commits] [PATCH] D156118: [lldb][AArch64] Add reading of TLS tpidr register from core files

DavidSpickett updated this revision to Diff 545044. DavidSpickett added a comment. rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156118/new/ https://reviews.llvm.org/D156118 Files: lldb/include/lldb/Host/linux/Ptrace.h lldb/source/Plugi

[Lldb-commits] [PATCH] D156512: [lldb][AArch64] Save/restore TLS registers around expressions

DavidSpickett updated this revision to Diff 545045. DavidSpickett added a comment. rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156512/new/ https://reviews.llvm.org/D156512 Files: lldb/source/Plugins/Process/Linux/NativeRegisterContextLi

[Lldb-commits] [PATCH] D156493: [lldb-vsocde] Adding support for the "disassemble" request.

DavidSpickett added a comment. I have no excuse to not try vcsode with lldb now, thanks for working on this! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156493/new/ https://reviews.llvm.org/D156493 ___

[Lldb-commits] [PATCH] D156687: [LLDB][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

DavidSpickett created this revision. Herald added subscribers: ctetreau, kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. While working in support for SME's ZA register, I found a cir

[Lldb-commits] [PATCH] D156687: [LLDB][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

DavidSpickett added a reviewer: omjavaid. DavidSpickett added a comment. Herald added a subscriber: JDevlieghere. Even if this turns out not to be needed for Za handling, I think `WriteAllRegisterValues` not having to care about the layout is an improvement in itself. Plus, this will give us a

[Lldb-commits] [PATCH] D156687: [LLDB][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

DavidSpickett added a comment. And an important note, you don't need the size for each block because the scalable blocks have headers from ptrace embedded in them anyway (SVE/SSVE/ZA). I did remove some checks that seemed redundant because all data read by WriteAll is going to have been written

[Lldb-commits] [PATCH] D156687: [LLDB][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

DavidSpickett added a comment. I have some failing tests on Graviton to debug: Failed Tests (2): lldb-api :: commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py lldb-api :: tools/lldb-server/TestGdbRemoteRegisterState.py But the idea still stan

[Lldb-commits] [PATCH] D156687: [LLDB][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

DavidSpickett updated this revision to Diff 545652. DavidSpickett added a comment. Correct m_sve_state size to fix tests on SVE machines. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156687/new/ https://reviews.llvm.org/D156687 Files: lldb/sour

[Lldb-commits] [PATCH] D156687: [LLDB][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

DavidSpickett updated this revision to Diff 545657. DavidSpickett added a comment. Remove misleading comment. We save the whole SVE context, FPSIMD or not. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156687/new/ https://reviews.llvm.org/D156687

[Lldb-commits] [PATCH] D156817: _wsopen_s does not accept bits other than `_S_IREAD | _S_IWRITE`

DavidSpickett added a comment. I just commented on the issue, thanks for the fix! What exactly are the other bits in the mode here, are we losing something important potentially? I guess it can't be that important if Windows rejects them. Repository: rG LLVM Github Monorepo CHANGES SINCE L

[Lldb-commits] [PATCH] D156817: _wsopen_s does not accept bits other than `_S_IREAD | _S_IWRITE`

DavidSpickett added a comment. Also please put `[lldb][Windows]` at the start of the commit title. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156817/new/ https://reviews.llvm.org/D156817 ___ lldb-comm

[Lldb-commits] [PATCH] D156817: _wsopen_s does not accept bits other than `_S_IREAD | _S_IWRITE`

DavidSpickett added inline comments. Comment at: lldb/source/Host/windows/FileSystem.cpp:104 return -1; + mode = mode & (_S_IREAD | _S_IWRITE); // All other bits are rejected by _wsopen_s int result; Nitpick: comments are usually on the line before. R

[Lldb-commits] [PATCH] D156493: [lldb-vsocde] Adding support for the "disassemble" request.

DavidSpickett added a comment. I've marked one of these tests skipped on Arm because it's failing on our bot: https://github.com/llvm/llvm-project/commit/54458c525aa47219a3ef2bee2be33d6096b1585c This is a 32 Arm machine, so unless you've got ready access to one, we'll figure out what the proble

[Lldb-commits] [PATCH] D156493: [lldb-vsocde] Adding support for the "disassemble" request.

DavidSpickett added a comment. Also it would be very useful if the logs could be printed in a pretty form like: >>> from pprint import pprint >>> pprint(j) {u'body': {u'instructions': [{u'address': u'0x400584', u'column': 9, u'

[Lldb-commits] [PATCH] D156493: [lldb-vsocde] Adding support for the "disassemble" request.

DavidSpickett added a comment. It's failing the test, but actually it looks like a cleanup step is failing. Whether that is also the timeout I don't know. I will restart the machine to rule out any lingering processes and get back to you. Repository: rG LLVM Github Monorepo CHANGES SINCE LA

[Lldb-commits] [PATCH] D156804: [lldb] Bump SWIG minimum version to 4

DavidSpickett added a comment. We are on 4.01 (AArch64), 4.02 (Arm) and 4.1.1 (Windows on Arm), so we have no issues with this. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156804/new/ https://reviews.llvm.org/D156804 ___ lldb-commits maili

[Lldb-commits] [PATCH] D156949: [lldb] Update LLDB Code Ownership

DavidSpickett added inline comments. Comment at: lldb/CodeOwners.rst:7-8 +particular part of LLDB are reviewed, either by themself or by someone else. +They are also the gatekeepers for their part of LLDB, with the final word on +what goes in or not. + This could

[Lldb-commits] [PATCH] D155905: lldb RFC: Exposing set/get address masks, Fix*Address methods in SBProcess

DavidSpickett added inline comments. Comment at: lldb/include/lldb/API/SBProcess.h:433 + + /// Clear the non-addressable bits of an \a addr value and return a + /// virtual address in memory. "Clear bits from an addr value that are not used for addressing" is c

[Lldb-commits] [PATCH] D156493: [lldb-vsocde] Adding support for the "disassemble" request.

DavidSpickett added a comment. > Also it would be very useful if the logs could be printed in a pretty form > like: And I'll have a patch for this shortly. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156493/new/ https://reviews.llvm.org/D156493

[Lldb-commits] [PATCH] D156977: [lldb][lldb-vscode] Fix nullptr dereference when JSON is not an object

DavidSpickett created this revision. Herald added a project: All. DavidSpickett requested review of this revision. Herald added subscribers: lldb-commits, wangpc. Herald added a project: LLDB. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D156977 Files: lldb/tools/lldb-vscode/

[Lldb-commits] [PATCH] D156979: [lldb][lldb-vscode] Pretty print JSON to log files

DavidSpickett created this revision. Herald added a project: All. DavidSpickett requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. This makes anlysing test failures much more easy. For SendJSON this is simple, just use llvm::format instead.

[Lldb-commits] [PATCH] D156979: [lldb][lldb-vscode] Pretty print JSON to log files

DavidSpickett added reviewers: ashgti, wallace. DavidSpickett added a comment. The one disadvantage here is that pretty printing adds more characters, so before you could copy paste the single JSON line and (I presume) it would have the same number of characters. If that's a required use case t

[Lldb-commits] [PATCH] D156118: [lldb][AArch64] Add reading of TLS tpidr register from core files

DavidSpickett added a comment. ping! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156118/new/ https://reviews.llvm.org/D156118 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llv

[Lldb-commits] [PATCH] D156512: [lldb][AArch64] Save/restore TLS registers around expressions

DavidSpickett added a comment. ping! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156512/new/ https://reviews.llvm.org/D156512 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llv

[Lldb-commits] [PATCH] D156118: [lldb][AArch64] Add reading of TLS tpidr register from core files

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG43ad521f2fa9: [lldb][AArch64] Add reading of TLS tpidr register from core files (authored by DavidSpickett). Repository: rG LLVM Github Monorepo

[Lldb-commits] [PATCH] D156512: [lldb][AArch64] Save/restore TLS registers around expressions

This revision was automatically updated to reflect the committed changes. Closed by commit rG6239227172cd: [lldb][AArch64] Save/restore TLS registers around expressions (authored by DavidSpickett). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156512

[Lldb-commits] [PATCH] D157000: [lldb][AArch64] Check SIMD save/restore in SVE SIMD test

DavidSpickett created this revision. Herald added subscribers: ctetreau, kristof.beyls. Herald added a project: All. DavidSpickett requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. While doing some refactoring I forgot to carry over the copyi

[Lldb-commits] [PATCH] D156687: [lldb][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

DavidSpickett updated this revision to Diff 546842. DavidSpickett added a comment. Use uint8_t for kind, fix some places doing sizeof uint32_t not of the kind type. Put back memcopy of fpr registers, which is now tested by the parent patch. Repository: rG LLVM Github Monorepo CHANGES SINCE

[Lldb-commits] [PATCH] D156687: [lldb][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

DavidSpickett added a comment. Oh, and fixed the FIXME now that the TLS fixes have landed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156687/new/ https://reviews.llvm.org/D156687 ___ lldb-commits mail

[Lldb-commits] [PATCH] D157000: [lldb][AArch64] Check SIMD save/restore in SVE SIMD test

DavidSpickett added a comment. MTE control needs a test too, I'm working on that as its own change. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157000/new/ https://reviews.llvm.org/D157000 ___ lldb-com

[Lldb-commits] [PATCH] D156949: [lldb] Update LLDB Code Ownership

DavidSpickett added inline comments. Comment at: lldb/CodeOwners.rst:7-8 +particular part of LLDB are reviewed, either by themself or by someone else. +They are also the gatekeepers for their part of LLDB, with the final word on +what goes in or not. + JDevlieghe

[Lldb-commits] [PATCH] D156977: [lldb][lldb-vscode] Fix nullptr dereference when JSON is not an object

This revision was automatically updated to reflect the committed changes. Closed by commit rGbdeb35bda438: [lldb][lldb-vscode] Fix nullptr dereference when JSON is not an object (authored by DavidSpickett). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.or

[Lldb-commits] [PATCH] D156979: [lldb][lldb-vscode] Pretty print JSON to log files

This revision was automatically updated to reflect the committed changes. Closed by commit rG165f45a87774: [lldb][lldb-vscode] Pretty print JSON to log files (authored by DavidSpickett). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156979/new/ http

[Lldb-commits] [PATCH] D156817: [lldb][windows] _wsopen_s does not accept bits other than `_S_IREAD | _S_IWRITE`

DavidSpickett accepted this revision. DavidSpickett added a comment. I think this could be tested with an lldb-server test, but it would likely go in `lldb/test/API/tools/lldb-server/TestGdbRemotePlatformFile.py` which has every test marked as skipped on Windows. For reasons lost to time. If yo

[Lldb-commits] [PATCH] D156493: [lldb-vsocde] Adding support for the "disassemble" request.

DavidSpickett added a comment. > Do you have any additional information about the failure? The link looks like > a timeout, so I'm not sure where things are timing out. Sorry for the false alarm, https://github.com/llvm/llvm-project/commit/9a3f0cd717f68ccf9e348bce2d76a2372482f4f2 fixed a few v

[Lldb-commits] [PATCH] D156949: [lldb] Update LLDB Code Ownership

DavidSpickett added inline comments. Comment at: lldb/CodeOwners.rst:150 + +ELF +~~~ labath wrote: > @DavidSpickett Ok with me. Comment at: lldb/CodeOwners.rst:220 + +lldb-server +~~~ labath wrote: > @DavidSpickett Ok

[Lldb-commits] [PATCH] D157214: [lldb] Fix typo in comments and in test

DavidSpickett accepted this revision. DavidSpickett added a comment. This revision is now accepted and ready to land. LGTM, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157214/new/ https://reviews.llvm.org/D157214

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