uot; }; /* { dg-error {excess elements in 'char[1]'
initializer} } */
See <https://www.tcl.tk/man/tcl8.6.13/TclCmd/Tcl.html> for a very short
page that has *all* Tcl syntax!
Segher
size of this patch already makes clear this is a bad idea, imo.
This code is already hard enough to read.
Segher
On Thu, Dec 01, 2022 at 12:17:30AM +0100, Andreas Schwab wrote:
> On Nov 30 2022, Segher Boessenkool wrote:
>
> > char u[1] = { "x", "x" }; /* { dg-error {excess elements in 'char[1]'
> > initializer} } */
>
> That won't work, as &#x
*/
> +A ret_arg_pt (A *a){return *a;}
> +
> +/* blr */
> +A ret_arg (A a) {return a;}
> +
> +/* 3 stfd */
> +void st_arg (A a, A *p) {*p = a;}
> +
> +/* { dg-final { scan-assembler-times {\mlfd\M} 3 } } */
> +/* { dg-final { scan-assembler-times {\mstfd\M} 3 } } */
> +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 9 } } */
Comment that last one? Just something as simple as "count insns" is
enough :-)
Segher
just things that came into my mind here, I'm not too
> familiar with how we handle such situations but at least I'm not
> aware of dozens of target hooks to handle instruction availability.
In similar cases I never could up with anything that worked better than
recognising all possible patterns, unfortunately. We can do a predicate
for that though, there is no need to write it out all over the place :-)
Segher
a part of the C/C++ 2x standards.
Only if you select a new enough -std=, it still is an extended type if
not?
Segher
\)\s} 1 } } *
> +/* { dg-final { scan-assembler-times {\mstd 6,16\(3\)\s} 1 } } */
This is only correct on certain ABIs, probably only ELFv2 even.
We certainly can improve the homogeneous aggregates stuff, but please
make sure you don't degrade all other stuff? Older, as well as when
things are not an homogeneous aggregate, for example too big. Can you
please add tests for such cases?
Segher
On Thu, Dec 08, 2022 at 09:17:38PM +0800, Jiufu Guo wrote:
> Segher Boessenkool writes:
> > On Wed, Dec 07, 2022 at 08:00:08PM +0800, Jiufu Guo wrote:
> >> typedef struct SA {double a[3];} A;
> >> A ret_arg_pt (A *a) {return *a;} // on ppc64le, expect only 3 lfd(s)
>
u cross. Bootstrapped and
> > tested on
> > powerpc64le-linux-gnu with no regressions. Is this okay for trunk?
>
> Okay.
No, as I said before this is not correct, not without a lot more
explanation at least. We should not copy errors in the old code into
the new code. Th
gt; @@ -0,0 +1,11 @@
> > +/* { dg-do compile { target { powerpc*-*-* && lp64 } } */
>
> Please don't include the "powerpc" target selector in the
> gcc.target/powerpc directory. Just use lp64.
Or actually, don't use anything, and do a dg-require int128 instead.
Segher
On Mon, Dec 13, 2021 at 02:37:43PM -0600, Bill Schmidt wrote:
> On 12/13/21 10:54 AM, Segher Boessenkool wrote:
> > On Mon, Dec 13, 2021 at 11:30:28AM -0500, David Edelsohn wrote:
> >> On Mon, Dec 13, 2021 at 10:48 AM Bill Schmidt
> >> wrote:
> >>> PR103624
iltin_unpack_longdouble (long double, const int<1>);
> -UNPACK_TF unpacktf {}
> +UNPACK_TF unpacktf {ibmld}
And that comment :-) (Or just copy the short comment from there).
Okay for trunk with that tweaked (and Martin's quoting thing taken care
of). Thanks!
Segher
unsigned long z = sum + x;
> + if (sum + x < x)
> + z++;
> + return z;
> +}
> +
> +/* { dg-final { scan-assembler "addze " } } */
Same question here.
Thanks!
Segher
On Tue, Dec 14, 2021 at 07:32:30AM -0600, Bill Schmidt wrote:
> On 12/13/21 6:22 PM, Segher Boessenkool wrote:
> > On Mon, Dec 13, 2021 at 02:37:43PM -0600, Bill Schmidt wrote:
> >> On 12/13/21 10:54 AM, Segher Boessenkool wrote:
> >>> On Mon, Dec 13, 2021 at 11:30:28
. If
there are many exceptions to that it will not be useful, but a bit of
it would make sense.
If you do that (and maybe similar things as well) this array question
will swivel.
> - if (TREE_CODE (arg0_type) != VECTOR_TYPE)
> - goto bad;
> - if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
> - goto bad;
Yay, all gotos should go :-)
Thanks again,
Segher
e larger
> set of problems. Is that a reasonable plan?
It is much more work than doing it correct in the first place.
I'll do the RTL side, if you want?
Segher
On Wed, Dec 15, 2021 at 01:29:57PM -0700, Jeff Law wrote:
> I think the generic parts are fine once Segher is happy with the rest of
> the bits.
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/585478.html
(last lines)
:-)
Segher
ion for the original
> report, so the attached patch is a suggestion to add a
> -mdejagnu-cpu=power9 to dg-options, which gets the test
> to pass for us.
Thanks for the patch!
Please use p7 instead of p9.
Also, you attached some binary, so I cannot reply to it easily.
Thanks,
Segher
On Fri, Dec 17, 2021 at 03:04:19PM +0100, Olivier Hainque wrote:
> > On 17 Dec 2021, at 13:58, Segher Boessenkool
> > wrote:
> > Please use p7 instead of p9.
>
> Sure.
>
> > Also, you attached some binary, so I cannot reply to it easily.
>
> Ah, sorry.
The builtins now all return "long". The patterns have :GPR as the
output mode, so they can be 32-bit as well (the instruction makes sense
in 32 bit just fine). The builtins expand to the DImode version
normally, but to the SImode if {32bit} is true.
2021-12-17 Segher Boessenkool
Make the darn testcases work (and be tested) in 32-bit mode as well.
They used to ICE, but they no longer do.
2021-12-17 Segher Boessenkool
gcc/testsuite/
PR target/103624
* gcc.target/powerpc/darn-0.c: Remove target clause.
* gcc.target/powerpc/darn-1.c: Remove target
ll only allow const_int, and matching a const_int
ignores the mode, so most (or all?) things will work whatever mode you
give here. But only MODE_INT modes make sense (and possibly VOIDmode,
but VOIDmode in machine descriptions means anything is allowed, also not
what you want here).
Segher
across all current releases.
>
> OK for mainline?
This fixes PR103739 by not building D at all anymore. That is also a
regression of course, but at least it doesn't break bootstrap anymore :-)
Thanks,
Segher
+1,9 @@
> +/* { dg-do compile { target { has_arch_pwr9 } } } */
Don't do that? Instead, use -mdejagnu-cpu=power9. This will give more
coverage, and also will make us need less future test maintenance (if on
Power28 we will generate different code for this, for example).
> +void __attribute__ ((noinline)) wrap_set_fpscr_rn (int val)
> +{
> + __builtin_set_fpscr_rn (val);
> +}
Should be noipa, not just noinline?
Segher
we have with fpscr (most FP insns use some of its
fields, most set some, but there is no way to cleanly express that).
Explicit clobbers like this help one side of the issue. For vscr, other
than the sat bit there is only the nj bit, and we just ignore that :-)
> This patch is okay. Thanks for updating the machine description and
> for cleaning up the formatting.
x2. Thanks!
Segher
e from operand. */
> - emit_insn (gen_anddi3 (tmp_rn, operands[0], GEN_INT (0x3)));
> + rtx op0 = convert_to_mode (DImode, operands[0], false);
> + emit_insn (gen_anddi3 (tmp_rn, op0, GEN_INT (3)));
>
>/* Insert new RN mode into FSCPR. */
> emit_insn (gen_rs6000_mffs (tmp_df));
It doesn't seem correct to use DImode with -m32, hrm. Not new of
course, but I wonder how this worked.
Okay for trunk with such changelog fixes. Thanks!
Segher
pro done because of
> !can_get_prologue didn't push anything into vec again).
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
That looks good, and very simple, thanks!
git blame says I wrote 69.9% of shrink-wrap.c, but I am not maintainer
of it, so I ca
probably need to be checking target
> costs.
It even then is still not worse on any modern superscalar machine!
Segher
in RTL at all. Probably the
simplest / best way to get there is to not have it in Gimple either, and
instead just use some "select" operation there, which can be optimised
much better anyway?
And yeah that will be GCC 13 stuff :-(
Segher
Hi!
On Mon, Jan 03, 2022 at 12:00:10PM +0100, Jakub Jelinek wrote:
> On Thu, Dec 30, 2021 at 04:08:25AM -0600, Segher Boessenkool wrote:
> > > The following simple patch makes sure we call can_get_prologue even after
> > > the last former iteration when vec is already empt
to, but to do that is much more complicated. Instead,
> this patch just ensures we don't dereference a NULL pointer when the situation
> arises.
Okay for trunk. Thanks!
Segher
> PR target/103622
> * config/rs6000/rs6000-c.c (altivec_resolve_new_overloaded_builtin):
> Skip over instances with undefined function types.
On Mon, Jan 10, 2022 at 06:09:01PM -0500, David Edelsohn wrote:
> On Sun, Jan 9, 2022 at 10:16 PM HAO CHEN GUI wrote:
> > > +/* { dg-final { scan-assembler-not "\mmr\M" } } */
>
> Segher probably would prefer {\mmr\M} .
Because that one works, and the one with double
y correct, it is not!)
> - return scalar_extract_exp (source);/* { dg-error "requires ISA 3.0
> IEEE
> 128-bit floating point" } */
> + return scalar_extract_exp (source);/* { dg-error "requires ISA 3.0
> IEEE
> 128-bit floating-point" } */
Your patch is malformed. Please fix your mailer.
Segher
Hi!
On Mon, Jan 17, 2022 at 09:06:25PM +0100, Sebastian Huber wrote:
> On 11/01/2022 09:10, Sebastian Huber wrote:
> >On 20/04/2021 17:00, Segher Boessenkool wrote:
> >>There are various non-IBM CPUs with isel as well, so it is easiest if we
> >>just don't co
On Fri, Mar 17, 2023 at 10:33:22AM -0600, Tom Tromey wrote:
> >>>>> "Segher" == Segher Boessenkool writes:
>
> Segher> Yes. On most architectures you can get multiple machine instructions
> of
> Segher> course (for long calls for example), bu
y much always.
Similar for the other three testcases of course.
This patch is okay for trunk, if you have tested it on all
configurations (powerpc-linux, powerpc64-linux, powerpc64le-linux with
and without default IEEE128 long double at least). Thank you!
Does this need backports?
Segher
On Mon, Mar 20, 2023 at 01:43:41PM -0400, Michael Meissner wrote:
> On Fri, Mar 17, 2023 at 02:35:16PM -0500, Segher Boessenkool wrote:
> > On Thu, Mar 09, 2023 at 08:40:36PM -0500, Michael Meissner wrote:
> > /* { dg-final { scan-assembler {\m__divtc3\M} } } */
> >
> &g
ot {\mmodsd\M} } } */
> +/* { dg-final { scan-assembler-not {\mmodud\M} } } */
You can do
/* { dg-final { scan-assembler-not {\mmod[su]d\M} } } */
if you want?
With or without that, okay for trunk. Thanks!
Segher
Hi!
On Thu, Mar 23, 2023 at 12:06:39AM -0300, Alexandre Oliva wrote:
> On Mar 13, 2023, Segher Boessenkool wrote:
> > Yes. On most architectures you can get multiple machine instructions of
> > course (for long calls for example), but on rs6000 (with some ABIs, in
> > s
+ if (insn_is_zext_p(cand->insn)
> + && CONST_INT_P (orig_src) && INTVAL (orig_src) != 0)
> +return false;
if (insn_is_zext_p (cand->insn) && orig_src != const0_rtx)
return false;
So what is this patch doing? At least two things, right? It aims to
improve what REE does, and also enables it by default for rs6000? So
make it two patches, please.
Can you talk a bit about what improvements to generated code you see?
Segher
missing. If DEST is non-NULL, additionally push the INSN
> > @@ -593,7 +646,7 @@ get_defs (rtx_insn *insn, rtx reg, vec
> > *dest)
> >
> >return ref_chain;
> > }
> > -
> > +#endif
>
> Why did you move get_defs?
And we should not normally have #if 0, too.
Segher
prerequisites so that everything is removed.
This solves the PR (PR101834). Thanks!
Segher
vec_concat gives
ABCDEFGH, and the vec_select than gives AEBF.
What happens for LE?
Segher
avioural change intended.
That doesn't sound as if you are very sure about things. I'll just
pretend it says "no functional changes" :-)
(*Is* this a pure refactoring?)
Segher
;
> +
> +*p_dst++ = constellation_64qam[index1];
> +
> +nbits--;
> + }
> +}
> +
> +/* { dg-final { scan-assembler {ldr\tw[0-9]+, \[x[0-9]+, w[0-9]+, [su]xtw
> #?2\]} } } */
This looks pretty good (thanks!), but as always it needs testing on more
architectures, showing it doesn't hurt things. It should be beneficial,
but it is not unlikely to hurt other existing backends, and we are not
in stage 1 (we are in stage 4 even!)
Do you have any such proof / indication / anything? I can start
some run but it takes a day (or two), and I cannot start it until next
week.
Do you have plans to make combine not do this insane "and" thing at all?
Or to attack the compound operation stuff head on?
Segher
On Fri, Mar 31, 2023 at 03:06:41PM +0100, Richard Sandiford wrote:
> Segher Boessenkool writes:
> > On Thu, Mar 09, 2023 at 12:10:51PM +, Richard Sandiford wrote:
> >> (and:DI (subreg:DI (reg:SI r115) 0)
> >> (const_int 63))
> >
> > Th
- Use rs6000_vprtyb2 rather than parityb2, and
> adjust several places with it accordingly.
>
> Bootstrapped and regtested on powerpc64-linux-gnu P{8,9}
> and powerpc64le-linux-gnu P10.
>
> Is it ok for trunk?
Looks good. Thanks!
Segher
v16qi,v8hi,v4si}_*
> then make them adopt the same naming style?
Yes please :-)
Segher
the same time? :-)
What does "pcvr" mean? You could put that in a short comment?
> + /* Generate one permutation control vector used for rotating the element
Ah. Yeah just "/* Permutation control vector */" for the above one
prevents all mysteries :-)
Patch looks good. Thanks!
Segher
>
> I believe the options should be sorted by the OPT_LEVEL* they are given.
If that is true, that rule is violated all over the place already. It
doesn't make much sense anyway, the OPT_LEVEL* have no complete ordering
at all. But, yeah, -O2 stuff after the -O1 stuff makes sense, and we do
have such a partial ordering now.
Segher
On Tue, Apr 04, 2023 at 05:26:26PM +0200, Jakub Jelinek wrote:
> On Tue, Apr 04, 2023 at 10:19:23AM -0500, Segher Boessenkool wrote:
> > > > +/* Enable -free for zero extension and sign extension
> > > > elimination.*/
> > > > +{ OPT_LEVELS_2_PL
entially changing the underlying RTL structure of an insn.
When returning the original, might be clearer?
Thanks,
Segher
On Wed, Apr 05, 2023 at 09:07:30AM -0600, Jeff Law wrote:
> On 4/5/23 08:21, Segher Boessenkool wrote:
> >On Wed, Mar 29, 2023 at 07:48:00AM -0600, Jeff Law wrote:
> >>So as mentioned in the PR the underlying issue here is combine changes
> >>the form of an existing
Hi again,
On Wed, Apr 05, 2023 at 11:43:30AM -0600, Jeff Law wrote:
> On 4/5/23 11:38, Segher Boessenkool wrote:
> >Right. But it seems to me it has been there all those years? Does the
> >new testcase fail on older branches? Even if not, it seems clear it is
> >wrong on
4SF 1 "vsx_register_operand" "%wa,wa,v")
> - (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
> +(match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
> +(match_operand:V4SF 2 "vsx_register_operand" "wa,0")
> (neg:V4SF
> - (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")]
> + (match_operand:V4SF 3 "vsx_register_operand" "0,wa")]
>"VECTOR_UNIT_VSX_P (V4SFmode)"
>"@
> xvnmsubasp %x0,%x1,%x2
> - xvnmsubmsp %x0,%x1,%x3
> - vnmsubfp %0,%1,%2,%3"
> + xvnmsubmsp %x0,%x1,%x3"
>[(set_attr "type" "vecfloat")])
Well, together with this of course :-)
Could you please do that?
Segher
Hi!
On Fri, Apr 07, 2023 at 02:32:04AM -0400, Michael Meissner wrote:
> On Thu, Apr 06, 2023 at 03:37:59PM -0500, Segher Boessenkool wrote:
> > > This patch eliminates the generation of the Altivec fmaddfp and fnmsubfp
> > > instructions as alternatives in the VSX instruction
00 for VMX), but also the NJ setting, and the default for NJ is
unusable for normal code (that is, code that is not low-precision
graphics code or the like; most code).
Please change *only* the two patterns I mentioned? Just never generate
vmaddfp or vnmsubfp when not explicitly asked for it.
Segher
VSX instructions.
Please mention the VSCR[NJ] thing here as well? Just something very
short, just mentioning "NJ" or "Non-Java" is enough.
With that: okay for trunk, thank you! Also okay for all backports.
Segher
ew builtin framework changed
so many things, there was bound to be some breakage to go with all the
good things it brought.
So what is the actual thing going wrong? QP insns work fine and are
valid on all systems and environments, BE or LE, 32-bit or 64-bit. Of
course you cannot use the "long double" type for those everywhere, but
that is a very different thing.
Segher
de rather than mode if WORD_REGISTER_OPERATIONS and mode is
> smaller than word_mode.
> * simplify-rtx.cc (simplify_context::simplify_binary_operation_1)
> : Likewise.
>
> * gcc.c-torture/execute/pr109040.c: New test.
Okay for trunk. Thanks!
Segher
the v3 patch has completed. Regression testing is still
> spinning. It should be done and waiting for me when I wake up in the
> morning.
It's still okay for trunk (of course) if the bootstrap doesn't fail (of
course). Thanks guys!
Segher
o maybe remove it
from the testcase here, but certainly not cargo-cult it to other
testcases!
Thanks,
Segher
bcdsub_lt,
> __builtin_bcdsub_eq, __builtin_bcdsub_gt, and __builtin_bcdsub_ov functions.
> This patch corrects these documentation errors.
What did you check this against? The ABI doc, or what is currently
implemented? Neither is very clear to me :-/
Segher
On Tue, Jul 31, 2018 at 10:33:59AM -0500, Aaron Sawdey wrote:
> Just teasing things apart a bit more in this function so I can add
> vec/vsx code generation without making it enormous and
> incomprehensible.
>
> Bootstrap/regtest passes on powerpc64le, ok for trunk?
Yes please. T
want to (or does that not work?)
The approach looks like it should work, but it does not seem all that
convenient to me. Well I'm sure you try it out on a reasonably sized
project, and you'll find out if it is handy or not :-)
Segher
hose that punt
> until we bump the requirement, well, they will now have to bump. :-)
"g++ requires it"? In what way? I haven't seen any issues with older
dejagnu versions.
> Ok to update to 1.5.3.
1.5.3 is only three years old, and not all distros carry it. This is
rather aggressive...
Segher
hich has
shorthand \s .
> +/* { dg-final { scan-assembler-not "\[ \t\]stp\tq\[01234567\]" } } */
That's [0-7] but maybe you find [01234567] more readable here.
> +/* { dg-final { scan-assembler-not "\[ \t\]str\t" } } */
You can also use \m and \M for start resp. end of word:
/* { dg-final { scan-assembler-not {\mstr\M} } } */
(or if you like double quotes better that is:
/* { dg-final { scan-assembler-not "\\mstr\\M" } } */
but why would you want that ;-) )
Segher
* { dg-options "-mvsx -O2" } */
What is that p8vector_ok for? You don't force p8 vector support on.
I think you can remove this.
Okay for trunk with that last one resolved. Thanks!
Segher
else
gcc_unreachable ();
}
Okay for trunk with that changed. Thanks!
Segher
Hi Kelvin,
On Tue, Aug 07, 2018 at 05:42:48PM -0500, Kelvin Nilsen wrote:
>
> My "consistency" check was against the implementation.
>
> On 8/2/18 11:38 AM, Segher Boessenkool wrote:
> > On Wed, Aug 01, 2018 at 02:55:22PM -0500, Kelvin Nilsen wrote:
> >>
On Wed, Aug 08, 2018 at 12:38:54AM -0300, Alexandre Oliva wrote:
> On Aug 7, 2018, Segher Boessenkool wrote:
> > On Tue, Aug 07, 2018 at 02:18:59AM -0300, Alexandre Oliva wrote:
>
> >> I saw comments, docs and init code that suggested the possibility of
> >> using
On Wed, Aug 08, 2018 at 01:17:49PM +0200, Bernhard Reutner-Fischer wrote:
> On 7 August 2018 18:34:30 CEST, Segher Boessenkool
> wrote:
> >On Mon, Aug 06, 2018 at 08:25:49AM -0700, Mike Stump wrote:
> >> Since g++ already requires 1.5.3, it make no sense to bump to
> &g
Hi Alexandre,
On Thu, Aug 09, 2018 at 03:23:12AM -0300, Alexandre Oliva wrote:
> On Aug 8, 2018, Segher Boessenkool wrote:
>
> > Then you get sdata2 used (via srodata in generic code), and it is accessed
> > via GPR2 (via the sda21 reloc and linker magic). It is
anging the constraints.
> (labelref): New insn to optimize loading a label address into
> registers on a medium code system.
(*labelref) btw.
Segher
On Mon, Jun 25, 2018 at 06:32:27AM -0500, Segher Boessenkool wrote:
> On Tue, Jun 19, 2018 at 10:45:59AM +0000, Segher Boessenkool wrote:
> > The existing code allows only 4 vectors worth of ieee128 homogeneous
> > aggregates, but it should be 8. This happens because at one
On Mon, Jun 25, 2018 at 03:34:26PM -0600, Jeff Law wrote:
> On 06/25/2018 05:53 AM, Segher Boessenkool wrote:
> > Hi Eric,
> >
> > On Wed, May 09, 2018 at 09:22:47AM +0200, Eric Botcazou wrote:
> >>> 2018-05-08 Segher Boessenkool
> >>>
> >&
ORDER): Defined.
> (TARGET_SHED_VARIABLE_ISSUE): Likewise.
> * config/aarch64/falor.md (falkor_variable_issue): New.
SCHED, not SHED :-) And s/falor/falkor/ .
Segher
On Mon, Aug 13, 2018 at 06:13:58PM +0200, Kai Tietz wrote:
> 2018-08-13 17:51 GMT+02:00 Segher Boessenkool :
> > On Mon, Aug 13, 2018 at 10:16:20AM +0200, Kai Tietz wrote:
> >> * config/aarch64.c (aarch64_sched_reorder): Implementing
> >>
After the combine 2-2 changes, this testcase does not have a ZERO_EXTEND
in the intermediate code, but an AND instead.
This adjusts the testcase. Committing.
2018-08-13 Segher Boessenkool
gcc/testcuite/
* gcc.target/powerpc/pr56605.c: The generated code can have an AND
.
Bootstrapped and tested on powerpc64-linux; will also test on
powerpc64le-linux before committing.
Segher
gcc/config/rs6000/altivec.md | 81 ++--
gcc/config/rs6000/darwin.md | 45 +++--
gcc/config/rs6000/dfp.md | 6 +-
gcc/config/rs6000/htm.md | 36 +++
gcc
This moves what is currently the default of the length attribute to
the only branch instruction patterns where it applies, namely, the
B-form instructions. It was used for the "jump" instruction as well
before, but that is an I-form instruction and always has length 4.
2018-08-
Now that it is the default for branch insns like for all other insns,
we don't need to set it explicitly so often anymore.
2018-08-16 Segher Boessenkool
* config/rs6000/altivec.md: Don't set length attribute to the default
value, for branch instructions.
There are some patterns that recognise the parallel of an add and a
compare, and split it back to the same two insns. This apparently
helped RIOS machines before RTL scheduling existed? Either way, it
isn't helpful anymore, and even hurts a tiny bit. So, delete it.
2018-08-16 S
There were many insns that set "length 4" explicitly while that does
not make anything clearer to the reader. So, simplify the code.
2018-08-16 Segher Boessenkool
* config/rs6000/altivec.md: Don't set length attribute to the default
value.
* config/r
tree t, tree bitsize, tree bitpos)
It could use a comment, too (what the args are, etc.)
Other than those nits, looks fine to me. Maybe Richard or Bill have
more comments?
Segher
This gives a name to the conditional branch and conditional return
patterns, so that it looks neater in dumps and verbose asm. Also, the
comment for conditional branch was out of date; this fixes it.
Committing.
Segher
2018-08-17 Segher Boessenkool
* config/rs6000/rs6000.md
makeinfo warns about this. Obvious, tested, committing.
Segher
2018-08-17 Segher Boessenkool
* doc/md.texi (Patterns): Use @ref instead of @xref in the middle of
a sentence.
---
gcc/doc/md.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc
_L0W1"
> + [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
> + (match_operand:DF 1 "gpc_reg_operand" "d")]
> + UNSPECV_MTFSF_L0W1)]
> + "TARGET_HARD_FLOAT"
> + "mtfsf %0,%1,0,1")
Maybe name it rs6000_mtsfs_high? L0W1 reads like "low" :-)
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -15745,6 +15745,10 @@ uint64_t __builtin_ppc_get_timebase ();
> unsigned long __builtin_ppc_mftb ();
> __ibm128 __builtin_unpack_ibm128 (__ibm128, int);
> __ibm128 __builtin_pack_ibm128 (double, double);
> +double __builtin_mffs(void);
> +void __builtin_mtfsb0(const int);
> +void __builtin_mtfsb1(const int);
> +void __builtin_set_fpscr_rn(int);
> @end smallexample
(space before opening paren)
> +++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_builtins.c
> @@ -0,0 +1,282 @@
> +/* { dg-do run { target { powerpc64*-*-* && lp64 } } } */
> +/* { dg-require-effective-target lp64 } */
You have "lp64" in the selector already, repeating it here doesn't do
anything.
> +/* { dg-options "-pedantic" } */
Why is this?
Segher
(%qs is
> deprecated)
This is not described in the changelog.
I don't understand what it means either; did you change the semantics of
the "Ignore" flag? It worked just fine before, and I don't know if it
still does :-/
[ Please cc: the rs6000 maintainers when you change rs6000 code. Thanks! ].
Segher
re
> we also catch any qualified types matching the V2DF_ or V4SF_ types.
That looks fine; if no one hollers, please commit. Thanks!
I note we use lang_hooks.types_compatible_p a lot, which is a totally
different thing? How confusing :-/
Segher
> 2018-08-20 Will Schmidt
>
>
tch adds the "Z" constraint as well,
> which allows indexed addresses.
This is okay for trunk, and for backports too. Thanks!
> +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
Maybe add a comment on why lp64 is needed here, it took me a minute :-)
Segher
reported failing fortran
testcase on an arm-linux-gnueabi crosscompiler (by inspection).
Committing.
2018-08-22 Segher Boessenkool
* combine.c (try_combine): Do not allow splitting a resulting PARALLEL
of two SETs into those two SETs, one to be placed at i2, if that SETs
returns if we cannot create pseudos.
Tested on powerpc64-linux {-m32,-m64}. Is this okay for trunk?
Segher
2018-08-23 Segher Boessenkool
PR rtl-optimization/87026
* expmed.c (canonicalize_comparison): If we can no longer create
pseudoregisters, don't.
---
gcc/exp
There currently is nothing that prevents replacing the TOC_REGISTER in
a TOCREL unspec with something else, like a pseudo, or a memory ref.
This of course does not work. Fix that.
Tested on powerpc64-linux {-m32,-m64}; committing.
Segher
2018-08-24 Segher Boessenkool
PR target
ybe you want
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 7 } } */
instead?
Rest looks fine to me (whatever that means :-) )
Segher
attempting to extract
> > the splat value.
> > Removed the (now unnecessary) code that did bounds-checking before calling
> > the tree_vec_extract helper.
> > Used arg0_type rather than lhs_type for calculating the tree size.
> >
> > V3 updates, inspired by add
Hi Jakub,
On Mon, Aug 27, 2018 at 09:24:16AM +0200, Jakub Jelinek wrote:
> This patch is just a partial fix, combine.c has lots of other code that was
> written before vector modes were introduced and won't work well with them.
Yeah. But somehow it works fine almost all of the time. Maybe most
g compares to
> + do the final comparison of less than 16 bytes. Also I do not want
> + to deal with making this work for 32 bits. */
Two spaces after full stop.
> + if (use_vec)
> +{
> + s1addr = gen_reg_rtx (Pmode);
> + s2addr = gen_reg_rtx (Pmode);
> + off_reg = gen_reg_rtx (Pmode);
> + vec_result = gen_reg_rtx (load_mode);
> + emit_move_insn (result_reg, GEN_INT (0));
> + expand_strncmp_vec_sequence(compare_length,
Space before (.
Please fix these nits, and then it is okay for trunk. Thanks!
Segher
queued up for backports.
Segher
2018-08-31 Segher Boessenkool
PR target/86684
PR target/87149
* config/rs6000/rs6000.md (lrounddi2): Gate on TARGET_FPRND.
---
gcc/config/rs6000/rs6000.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config
6: Don't use frame pointer without stack access
>
> When there is no stack access, there is no need to use frame pointer
> even if -fno-omit-frame-pointer is used and caller's frame pointer is
> unchanged.
>
> changed it in the last minute. It is too late to go back. When it is done,
> hard frame pointer must be replaced by stack pointer - UNITS_PER_WORD
> if it is ever used.
So after that patch something uses the hard frame pointer, while it also
claims nothing uses the hard frame pointer? Sounds to me you should fix
the uses, and all will be fine.
Segher
2801 - 2900 of 6091 matches
Mail list logo
