From: Pan Li
There are sorts of forms for the unsigned SAT_ADD. Some of them are
complicated while others are cheap. This patch would like to simplify
the complicated form into the cheap ones. For example as below:
>From the form 6 (branch):
SUM = ADD_OVERFLOW (X, Y)
SAT_U_ADD = IMAGPART_
From: Pan Li
The phiopt2 pass will also try the gimple_simplify for the form 15
of unsigned integer SAT_ADD. Thus add the testcase to make sure
it will be performed in phiopt2 pass.
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap test
From: Pan Li
The phiopt2 pass will also try the gimple_simplify for the form 11
of unsigned integer SAT_ADD. Thus add the testcase to make sure
it will be performed in phiopt2 pass.
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap test
From: Pan Li
The phiopt2 pass will also try the gimple_simplify for the form 12
of unsigned integer SAT_ADD. Thus add the testcase to make sure
it will be performed in phiopt2 pass.
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap test
From: Pan Li
The phiopt2 pass will also try the gimple_simplify for the form 9
of unsigned integer SAT_ADD. Thus add the testcase to make sure
it will be performed in phiopt2 pass.
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests
From: Pan Li
The phiopt2 pass will also try the gimple_simplify for the form 10
of unsigned integer SAT_ADD. Thus add the testcase to make sure
it will be performed in phiopt2 pass.
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap test
From: Pan Li
There are sorts of forms for the unsigned SAT_ADD. Some of them are
complicated while others are cheap. This patch would like to simplify
the complicated form into the cheap ones. For example as below:
>From the form 4 (branch):
SUM = ADD_OVERFLOW (X, Y)
SAT_U_ADD = IMAGPART_
From: Pan Li
The phiopt2 pass will also try the gimple_simplify for the form 6
of unsigned integer SAT_ADD. Thus add the testcase to make sure
it will be performed in phiopt2 pass.
gcc/testsuite/ChangeLog:
* gcc.dg/sat_arith_simplify.h: Add test helper macros.
* gcc.dg/sat_u_ad
From: Pan Li
This patch would like to add doc for the below 2 standard names.
1. strided load: v = mask_len_strided_load (ptr, stried, mask, len, bias)
2. strided store: mask_len_stried_store (ptr, stride, v, mask, len, bias)
gcc/ChangeLog:
* doc/md.texi: Add doc for mask_len_stried_lo
From: Pan Li
This reverts commit df4af89bc3eabbeaccb16539aa1082cb9863e187.
---
gcc/match.pd | 11 ---
.../gcc.dg/tree-ssa/sat_u_add-simplify-1-u16.c| 15 ---
.../gcc.dg/tree-ssa/sat_u_add-simplify-1-u32.c| 15 ---
.../g
From: Pan Li
This patch would like to refactor the unsigned SAT_ADD pattern by:
* Extract type check outside.
* Extract common sub pattern.
* Re-arrange the related match pattern forms together.
* Remove unnecessary helper pattern matches.
The below test suites are passed for this patch.
* The r
From: Pan Li
Just notice the indent is not that right for ustrunc pattern from
the md files. Thus, make it correct. It is somehow very obvious
and will commit it after next 48H if no more comments.
gcc/ChangeLog:
* config/riscv/autovec.md: Fix indent format issue.
Signed-off-by: Pan
From: Pan Li
The phiopt2 pass will also try the gimple_simplify for the form 5
of unsigned integer SAT_ADD. Thus add the testcase to make sure
it will be performed in phiopt2 pass.
gcc/testsuite/ChangeLog:
* gcc.dg/sat_arith_simplify.h: Add test helper macros.
* gcc.dg/sat_u_ad
From: Pan Li
There are sorts of forms for the unsigned SAT_ADD. Some of them are
complicated while others are cheap. This patch would like to simplify
the complicated form into the cheap ones. For example as below:
>From the form 7 (branch):
SAT_U_ADD = x <= (T)(x + y) ? (x + y) : -1.
To (
From: Pan Li
There are sorts of forms for the unsigned SAT_ADD. Some of them are
complicated while others are cheap. This patch would like to simplify
the complicated form into the cheap ones. For example as below:
>From the form 4 (branch):
SAT_U_ADD = (X + Y) < x ? -1 : (X + Y).
To (bran
From: Pan Li
Sorts of comments of unsigned integer SAT_ADD matching is not updated
to date. This patch would like to refine it.
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
gcc/ChangeLog:
From: Pan Li
In previous, we extract matching usadd_left_part_1 to avoid duplication.
After we simplify some usadd patterns into cheap form, there will be
only one reference to this matching. Thus, remove this matching pattern
and unfold it to the reference place.
The below test suites are pass
From: Pan Li
The phiopt2 pass will also try the gimple_simplify for the form 8
of unsigned integer SAT_ADD. Thus add the testcase to make sure
it will be performed in phiopt2 pass.
gcc/testsuite/ChangeLog:
* gcc.dg/sat_arith_simplify.h: Add test helper macros.
* gcc.dg/sat_u_ad
From: Pan Li
The phiopt2 pass will also try the gimple_simplify for the form 7
of unsigned integer SAT_ADD. Thus add the testcase to make sure
it will be performed in phiopt2 pass.
gcc/testsuite/ChangeLog:
* gcc.dg/sat_arith_simplify.h: Add test helper macros.
* gcc.dg/sat_u_ad
From: Pan Li
There are sorts of forms for the unsigned SAT_ADD. Some of them are
complicated while others are cheap. This patch would like to simplify
the complicated form into the cheap ones. For example as below:
>From the form 8 (branch):
SAT_U_ADD = x > (T)(x + y) ? -1 : (x + y).
To (b
From: Pan Li
As suggested by Richard, move the SAT_ADD simplify testcases from
the tree-ssa to gcc.dg.
gcc/testsuite/ChangeLog:
* gcc.dg/sat_arith_simplify.h: Add test macros.
* gcc.dg/tree-ssa/sat_u_add-simplify-1-u16.c: Move to...
* gcc.dg/sat_u_add-simplify-1-u16.c: .
From: Pan Li
This patch would like to leverage the match_cond_with_binary_phi to
match the phi on cond, and get the true/false arg if matched. This
helps a lot to simplify the implementation of gen_phi_on_cond.
Before this patch:
basic_block _b1 = gimple_bb (_a1);
if (gimple_phi_num_args (_a1)
From: Pan Li
This patch would like fix the dump check times of vector SAT_ADD. The
middle-end change makes the match times from 2 to 4 times.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/b
From: Pan Li
When matching the cond with 2 args phi node, we need to figure out
which arg of phi node comes from the true edge of cond block, as
well as the false edge. This patch would like to add interface
to perform the action and return the true and false arg in TREE type.
The below test su
From: Pan Li
This patch would like to support the form 3 of the scalar signed
integer .SAT_ADD. Aka below example:
Form 3:
#define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \
T __attribute__((noinline))\
sat_s_add_##T##_fmt_3 (T x, T y)
From: Pan Li
Form 3:
#define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
{
From: Pan Li
This patch would like to support the form 3 of the vector signed
integer .SAT_ADD. Aka below example:
Form 3:
#define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_
From: Pan Li
Form 4:
#define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{
From: Pan Li
This patch would like to fix one ICE when try to match the binary
phi for below cfg. We check the first edge of the Phi block comes
from b0, instead of check the only one edge of b1 comes from the
b0 too. Thus, it will result in some code to be recog as .SAT_SUB
but it is not, and
From: Pan Li
This patch would like to fix the following ICE for -O2 -m32 of x86_64.
during RTL pass: expand
JackMidiAsyncWaitQueue.cpp.cpp: In function 'void DequeueEvent(unsigned
int)':
JackMidiAsyncWaitQueue.cpp.cpp:3:6: internal compiler error: in
expand_fn_using_insn, at internal-fn.cc:263
From: Pan Li
This patch would like to support the form 1 of the scalar signed
integer SAT_SUB. Aka below example:
Form 1:
#define DEF_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_sub_##T##_fmt_1 (T x, T y) \
{
From: Pan Li
This patch would like to implement the sssub form 1. Aka:
Form 1:
#define DEF_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_sub_##T##_fmt_1 (T x, T y) \
{\
T minus = (UT)x
From: Pan Li
Form 1:
#define DEF_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_sub_##T##_fmt_1 (T x, T y) \
{\
T minus = (UT)x - (UT)y; \
return (x ^ y) >= 0
From: Pan Li
This patch would like to fix the following ICE for -O2 -m32 of x86_64.
during RTL pass: expand
JackMidiAsyncWaitQueue.cpp.cpp: In function 'void DequeueEvent(unsigned
int)':
JackMidiAsyncWaitQueue.cpp.cpp:3:6: internal compiler error: in
expand_fn_using_insn, at internal-fn.cc:263
From: Pan Li
This patch would like to fix the following ICE for -O2 -m32 of x86_64.
during RTL pass: expand
JackMidiAsyncWaitQueue.cpp.cpp: In function 'void DequeueEvent(unsigned
int)':
JackMidiAsyncWaitQueue.cpp.cpp:3:6: internal compiler error: in
expand_fn_using_insn, at internal-fn.cc:263
From: Pan Li
This patch would like to fix one incorrect test macro usage for
form 2 of signed scalar SAT_ADD run test. It should leverage the
_FMT_2 instead of _FMT_1 for form 2.
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up
From: Pan Li
Take scan-assembler-times for vsadd insn check instead of function body,
as we only care about if we can generate the fixed point insn vsadd.
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit
From: Pan Li
Take scan-assembler-times for vsadd insn check instead of function body,
as we only care about if we can generate the fixed point insn vssub.
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit
From: Pan Li
Take scan-assembler-times for vsadd insn check instead of function body,
as we only care about if we can generate the fixed point insn vnclip.
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit
From: Pan Li
This patch would like to support the form 2 of the scalar signed
integer SAT_SUB. Aka below example:
Form 2:
#define DEF_SAT_S_SUB_FMT_2(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_sub_##T##_fmt_1 (T x, T y) \
{
From: Pan Li
Form 2:
#define DEF_SAT_S_SUB_FMT_2(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_sub_##T##_fmt_1 (T x, T y) \
{\
T minus = (UT)x - (UT)y; \
if ((x ^ y) >= 0 || (minus
From: Pan Li
We iterate all phi node of bb to try to match the SAT_* pattern
for scalar integer. We also remove the phi mode when the relevant
pattern matched.
Unfortunately the iterator may have no idea the phi node is removed
and continue leverage the free data and then ICE similar as below.
From: Pan Li
Form 4:
#define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX) \
T __attribute__((noinline))\
sat_s_add_##T##_fmt_4 (T x, T y) \
{ \
T sum;
From: Pan Li
This patch would like to add testcases of the signed scalar SAT_ADD
for form 3. Aka:
Form 3:
#define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \
T __attribute__((noinline))\
sat_s_add_##T##_fmt_3 (T x, T y) \
{
From: Pan Li
Form 2:
#define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
{
From: Pan Li
This patch would like to support the form 2 of the vector signed
integer .SAT_ADD. Aka below example:
Form 2:
#define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_
From: Pan Li
Some print code for debugging is committed by mistake, remove them
from the test header file.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/scalar_sat_binary_run_xxx.h: Remov
From: Pan Li
Like the strided load/store, the testcases of vector gather/scatter are
designed to pick up different sorts of optimization options but actually
these option are ignored according to the Execution log of gcc.log. This patch
would like to make it correct almost the same as what we fi
From: Pan Li
This patch would like to refactor the testcases of gather/scatter
after sorts of optimization option passing to testcase. Includes:
* Remove unnecessary optimization options.
* Adjust dg-final by any-opts and/or no-opts if the rtl dump changes
on different optimization options (l
From: Pan Li
There are some forms like below failed to recog the SAT_ADD
pattern for target i386. It is related to some match pattern
extraction but get fixed after the refactor of the SAT_ADD
pattern. Thus, add testcases to ensure we may have similar
issue in futrue.
#define DEF_SAT_ADD(T)
From: Pan Li
Update in v2:
* Skip lto build as no such dump files.
* scan dump check for optimized.
Original log:
There are some forms like below failed to recog the SAT_ADD
pattern for target i386. It is related to some match pattern
extraction but get fixed after the refactor of the SAT_ADD
From: Pan Li
This patch would like to refactor the unsigned SAT_ADD pattern when
leverage the IFN ADD_OVERFLOW, aka:
* Extract type check outside.
* Re-arrange the related match pattern forms together.
* Remove unnecessary helper pattern matches.
The below test suites are passed for this patch.
From: Pan Li
This patch would like to refactor the all unsigned SAT_SUB patterns, aka:
* Extract type check outside.
* Re-arrange the related match pattern forms together.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fu
From: Pan Li
Like the strided load/store, the testcases of vector widen are
designed to pick up different sorts of optimization options but actually
these option are ignored according to the Execution log of gcc.log.
This patch would like to make it correct almost the same as what we fixed for
st
From: Pan Li
Like the strided load/store, the testcases of vector widen are
designed to pick up different sorts of optimization options but actually
these option are ignored according to the Execution log of gcc.log.
This patch would like to make it correct almost the same as what we fixed for
st
From: Pan Li
This patch would like to fix the testcases failures of strided
load/store after sorts of optimization option passing to testcase.
* Add no strict align for vector option.
* Adjust dg-final by any-opts and/or no-opts if the rtl dump changes
on different optimization options (like O
From: Pan Li
This patch would like to remove the unnecessary option for the
strided load/store testcases. After fix the option from the rvv.exp,
both the O2 and O3 will be passed to the test files for rtl expand
dump check but the O2 has 2 time for IFN while the O3 has 4 times with
-fvectorize s
From: Pan Li
After we create a isolated folder to hold all SAT scalar test,
we have fully control of what optimization options passing to
the testcase. Thus, it is better to remove the unnecessary
work around for flto option, as well as the -O3 option for
each cases. The riscv.exp will pass sor
From: Pan Li
The testcases of vector strided load/store are designed to pick up
different sorts of optimization options but actually these option
are ignored according to the Execution log of gcc.log. This patch
would like to make it correct, and then you will see the build option
similar as bel
From: Pan Li
After we move vector SAT_ADD testcases into a isolated folder, aka
riscv/rvv/autovec/sat. We would like to add the folder as one of
the test items of the rvv.exp testsuite.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch
From: Pan Li
This patch would like to remove the unnecessary option for the
vector SAT_ADD testcases at first. And the different optimization
option like O2 and O3 will be passed to the test files for rtl
expand dump check. If there are different dump check times for
different optimization opti
From: Pan Li
Move the scalar SAT_ADD includes both the signed and unsigned
integer to the folder gcc.target/riscv/sat. According to the
implementation the below options will be appended for each
test cases.
* -O2
* -O3
* -Ofast
* -Os
* -Oz
Then we can see the test log similar as below:
Execut
From: Pan Li
After we create a isolated folder to hold all SAT scalar test,
we have fully control of what optimization options passing to
the testcase. Thus, it is better to remove the unnecessary
work around for flto option, as well as the -O3 option for
each cases. The riscv.exp will pass sor
From: Pan Li
The test files of scalar SAT_SUB only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}. For example,
test form 3 for uint32_t SAT_SUB will have -3-u32.c for asm check and
-run-3-u32.c for the run test.
Meanwhile, all related test files moved to ris
From: Pan Li
Move all the other files of scalar SAT to dir riscv/sat/.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
*
From: Pan Li
The test files of vector SAT_SUB only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}. For example,
test form 3 for uint32_t SAT_SUB will have -3-u32.c for asm check and
-run-3-u32.c for the run test.
Meanwhile, moved all related test files to ris
From: Pan Li
Move all other test files of SAT ALU to riscv/rvv/autovec/sat/.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-1-i16.c: Move to...
* gc
From: Pan Li
This patch would like to refactor the testcases of vector SAT_SUB
after move to rvv/autovec/sat folder. Includes:
* Refine the include header files.
* Remove unnecessary optimization options.
* Adjust dg-final by any-opts and/or no-opts if the rtl dump changes
on different optimi
From: Pan Li
This patch would like to refactor the testcases of vector SAT_TRUNC
after move to rvv/autovec/sat folder. Includes:
* Refine the include header files.
* Remove unnecessary optimization options.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
From: Pan Li
The test files of vector SAT_TRUNC only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}. For example,
test form 3 for uint32_t SAT_TRUNC will have -3-u32.c for asm check
and -run-3-u32.c for the run test.
Meanwhile, moved all related test files to
From: Pan Li
The rtl expand dump for IFN check of stride load/store testcase is
different between O2 and O3. It it reasonable to leverage target
no-opts/any-opts to filte out, instead of the xfail.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test
From: Pan Li
Add asm dump check and run test for vec_duplicate + vadd.vv combine
to vadd.vx. Introduce new folder to hold all related testcases.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.ex
From: Pan Li
After we support the vec_duplicate + vadd.vv combine to vadd.vx, the
existing testcases need some adjust for asm dump check times.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/
From: Pan Li
This patch would like to combine the vec_duplicate + vadd.vv to the
vadd.vx. From example as below:
#define DEF_VX_BINARY(T, OP)\
void\
test_vx_binary (T * restrict out, T
From: Pan Li
Some forms like below failed to recog the SAT_ADD pattern
for target i386. It is related to some match pattern
extraction but get fixed after the refactor of the SAT_ADD
pattern. Thus, add testcases to ensure we may have similar
issue in futrue.
#define DEF_SAT_ADD(T) \
T sa
From: Pan Li
Like the strided load/store, the testcases of vector cond and builtin are
designed to pick up different sorts of optimization options but actually
these option are ignored according to the Execution log of gcc.log.
This patch would like to make it correct almost the same as what we
f
From: Pan Li
The test files of scalar SAT_ADD only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}. For example,
test form 3 for uint32_t SAT_ADD will have -3-u32.c for asm check and
-run-3-u32.c for the run test.
The below test suites are passed for this patc
From: Pan Li
The test files of scalar SAT_TRUNC only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}. For example,
test form 3 for uint32_t SAT_TRUNC will have -3-u32.c for asm check and
-run-3-u32.c for the run test.
Meanwhile, all related test files moved to
From: Pan Li
After we create a isolated folder to hold all SAT scalar test,
we have fully control of what optimization options passing to
the testcase. Thus, it is better to remove the unnecessary
work around for flto option, as well as the -O3 option for
each cases. The riscv.exp will pass sor
From: Pan Li
There are some forms like below failed to recog the SAT_ADD
pattern for target i386. It is related to some match pattern
extraction but get fixed after the refactor of the SAT_ADD
pattern. Thus, add testcases to ensure we may have similar
issue in futrue.
#define DEF_SAT_ADD(T)
From: Pan Li
Like the strided load/store, the testcases of vector reduce and ternop
are designed to pick up different sorts of optimization options but
actually these option are ignored according to the Execution log of
the gcc.log.
This patch would like to make it correct almost the same as wha
From: Pan Li
This patch would like to refactor the all unsigned SAT_TRUNC patterns,
aka:
* Extract type check outside.
* Re-arrange the related match pattern forms together.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86
From: Pan Li
According to the the initial analysis of PR117878, the ice comes from
the out-of-range operand access for recog_data.operand[]. Thus, add
one assert here to expose this explicitly.
PR target/117878
gcc/ChangeLog:
* config/riscv/riscv-v.cc (vlmax_avl_type_p): Add a
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_SUB exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SA
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_TRUNC exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SA
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SA
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_TRUNC exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_SUB exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SA
From: Pan Li
Like the strided load/store, the testcases of vector binop and cmp
are designed to pick up different sorts of optimization options but
actually these option are ignored according to the Execution log of
the gcc.log.
This patch would like to make it correct almost the same as how we
From: Pan Li
This patch would like to refactor the testcases for rvv binop
and cmp after sorts of optimization option passing to testcase.
To fits different optimization option asm dump checks.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only
From: Pan Li
Like the strided load/store, the testcases of vector partial
are designed to pick up different sorts of optimization options but
actually these option are ignored according to the Execution log of
the gcc.log.
This patch would like to make it correct almost the same as how we
fixed
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_TRUNC exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_SUB exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SA
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_TRUNC exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SA
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SA
From: Pan Li
The sat alu related testcase check the rtl dump for the standard name
like .SAT_SUB exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SA
From: Pan Li
Inspired by PR118103, the VXRM register should be treated almost the
same as the FRM register, aka cooperatively-managed global register.
Thus, add the VXRM to global_regs to avoid the elimination by the
late-combine pass.
For example as below code:
21 │
22 │ void compute (
From: Pan Li
This patch would like to refactor the all signed SAT_ADD patterns,
aka:
* Extract type check outside.
* Re-arrange the related match pattern forms together.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 full
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