From: Pan Li <pan2...@intel.com>
This patch would like to refactor the testcases of vector SAT_TRUNC
after move to rvv/autovec/sat folder. Includes:
* Refine the include header files.
* Remove unnecessary optimization options.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c:
Refine the include file and remove unnecessary optimization options.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c: Ditto
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c | 2 +-
.../riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c | 2 +-
48 files changed, 72 insertions(+), 72 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c
index 5354717cc46..bf83a5cbe66 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c
index 15654b4bf8b..01022496ca4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c
index 1e272aeb726..4f3efb9ec1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c
index 3d29d26abff..118a7267dde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c
index fc43a8a58f8..8c1f3caf0e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c
index b5a3fc3222d..400f892001d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c
index 9ed21e21e33..184a5fe6bd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c
index eb7d96197bb..70a096ec383 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c
index c9634d383ae..b4365bd9022 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c
index d2239d3e42c..614a189d86b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c
index 9c671cb897b..7e000689fab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c
index d93453f6890..1e9a584eed4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c
index 072d189224f..59acd8b7542 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c
index 837551ca6b6..70563d679dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c
index 3174f45fd60..bfc504e20f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c
index 04d12048bc2..56857340ad1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c
index 32a30f3692a..a615cfa2ee9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c
index dd14fad454c..457cc374a56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c
index b77fcd4a5bc..c4a09b29c10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c
index f177f7bedd7..e19ea9b6adc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c
index 8b27b69cf08..772924fa36d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c
index df1752c05db..a4b18954e37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c
index 200c559f855..d8c33c5188f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c
index db788e19092..25f6665c79f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c
index a51ad60ebbb..227a0524bab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c
index 90a12c9275e..0fb81031e4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c
index 3e7a7eda2db..7d69afcbe24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c
index 4e387d89019..dddc65256f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c
index 82396f53877..7ab739974bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c
index 33eea81cdf1..cf0a79a7596 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c
index d804b855845..f0de8599270 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c
index ffb9e6fe322..a5e822c44e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c
index e7852dd120b..a0557beee0c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c
index 283fb643029..6a535deff79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c
index 8b00555dbb9..9fac1448afa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c
index c580fda870b..e084ff778f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c
index 499eb17ff64..b2e812d8a54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c
index b42ad620259..9190c713728 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c
index 662b33a97a5..3d26721453e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c
index 1247ea335d4..3ea1669ef10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c
index 2a47a8ef05f..0517aad1bdb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c
index 4e387d89019..dddc65256f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c
index a51ad60ebbb..227a0524bab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c
index 201973d2134..650afdaebce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c
index 3e7a7eda2db..7d69afcbe24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c
index ffb9e6fe322..a5e822c44e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint16_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c
index 82396f53877..7ab739974bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint32_t
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c
index 90a12c9275e..0fb81031e4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
#include "vec_sat_data.h"
#define T1 uint8_t
--
2.43.0
