ed in leaf function.
Haven't noticed significant impact on benchmarks, but by grepping some
keywords like "Spilling", "Push.*spill" etc in ira rtl dump, the number
is smaller.
OK for trunk?
2015-05-19 Jiong. Wang
gcc/
PR 63521
* config/aarch64/
sequences.
Currently, -mtls-size accept all integer, then will translate it into
12(4K), 24(16M), 32(4G), 48(256TB) based on the value.
no functional change.
ok for trunk?
2015-05-20 Jiong Wang
gcc/
* config/aarch64/aarch64.opt (mtls-size): New entry.
* config/aarch64/aarch64.c
R_AARCH64_TLSLE_MOVW_TPREL_G2x4
movk t0, #:tprel_g1_nc:x4 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC x4
movk t0, #:tprel_g0_nc:x4 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC x4
add t0, t0, tp
OK for trunk?
2015-05-14 Jiong Wang
gcc/
* config/aarch64/aarch64.c
Jiong Wang writes:
> This patch add -mtls-size option for AArch64. This option let user to do
> finer control on code generation for various TLS model on AArch64.
>
> For example, for TLS LE, user can specify smaller tls-size, for example
> 4K which is quite usual, to let
Jeff Law writes:
> On 05/14/2015 03:13 PM, Jiong Wang wrote:
>>
>> Jeff Law writes:
>>
>>> For all kinds of reassociation we have to concern ourselves with adding
>>> overflow where it didn't already occur. Assuming a 32 bit architecture
>>>
This is a rework of
https://gcc.gnu.org/ml/gcc-patches/2014-07/msg01998.html
After second thinking, I feel it's better to fix this in earlier stage
during RTL expand which is more generic, and we also avoid making the
already complex combine pass complexer.
Currently gcc expand wide mode left
2015-02-11 18:18 GMT+00:00 Jiong Wang :
>
> 2015-02-11 Jiong Wang
>
> gcc/
> * loop-invariant.c (find_defs): Enable DF_DU_CHAIN build.
> (vfp_const_iv): New hash table.
> (expensive_addr_check_p): New boolean.
> (init_inv_motion_data): Initialize new variables.
&
Jiong Wang writes:
> 2015-04-14 18:24 GMT+01:00 Jeff Law :
>> On 04/14/2015 10:48 AM, Steven Bosscher wrote:
>>>>
>>>> So I think this stage2/3 binary difference is acceptable?
>>>
>>>
>>> No, they should be identical. If there'
> -Original Message-
> From: Ramana Radhakrishnan [mailto:ramana@googlemail.com]
> Sent: Wednesday, April 22, 2015 3:50 PM
> To: Joseph Myers
> Cc: Hale Wang; GCC Patches
> Subject: Re: [PATCH] [1/2] [ARM] [libgcc] Support RTABI half-precision
> conversion functi
Jeff Law writes:
> On 04/21/2015 08:24 AM, Jiong Wang wrote:
>>
>> Jiong Wang writes:
>>
>>> 2015-04-14 18:24 GMT+01:00 Jeff Law :
>>>> On 04/14/2015 10:48 AM, Steven Bosscher wrote:
>>>>>>
>>>>>> So I think this
> -Original Message-
> From: Ramana Radhakrishnan [mailto:ramana@googlemail.com]
> Sent: Wednesday, April 22, 2015 5:00 PM
> To: Hale Wang
> Cc: Ramana Radhakrishnan; Joseph Myers; GCC Patches
> Subject: Re: [PATCH] [1/2] [ARM] [libgcc] Support RTABI half-prec
Jeff Law writes:
> On 04/16/2015 05:04 AM, Jiong Wang wrote:
>>
>> This is a rework of
>>
>>https://gcc.gnu.org/ml/gcc-patches/2014-07/msg01998.html
>>
>> After second thinking, I feel it's better to fix this in earlier stage
>> during R
Hi Matthew,
2015-04-21 15:24 GMT+01:00 Jiong Wang :
>
> 2015-04-21 Jiong Wang
>
> gcc/
> * loop-invariant.c (find_defs): Enable DF_DU_CHAIN build.
> (vfp_const_iv): New hash table.
> (expensive_addr_check_p): New boolean.
> (init_inv_motion_data):
2015-04-28 14:56 GMT+01:00 Matthew Fortune :
>> Hi Matthew,
>>
>> 2015-04-21 15:24 GMT+01:00 Jiong Wang :
>>
>> >
>> > 2015-04-21 Jiong Wang
>> >
>> > gcc/
>> > * loop-invariant.c (find_defs): Enable DF_DU_CHAIN build.
Jeff Law writes:
> On 04/27/2015 02:21 PM, Jiong Wang wrote:
>
>> Jeff,
>>
>>Sorry, I can't understand the meaning of "overlap between t_low and low",
>>assume "right" in "right value" means the opposite of "left"
> -Original Message-
> From: Hale Wang [mailto:hale.w...@arm.com]
> Sent: Monday, February 09, 2015 9:54 AM
> To: Richard Earnshaw
> Cc: Hale Wang; gcc-patches; Matthew Gretton-Dann
> Subject: RE: [Ping^2] [PATCH, ARM, libgcc] New aeabi_idiv function for
> ar
> -Original Message-
> From: Hale Wang [mailto:hale.w...@arm.com]
> Sent: Thursday, November 13, 2014 2:16 PM
> To: 'Christophe Lyon'
> Cc: gcc-patches@gcc.gnu.org
> Subject: RE: Small multiplier support in Cortex-M0/1/+
>
> > -Original M
This patch add vector pattern for __builtin_ctz.
like __builtin_clz, only 32bit version of ctz supported.
for scalar version ctz, we expand it into:
rbit
clz
reverse bits first, then turn cout tailing zero into count leading zero.
while for vector version, rbit only support byte granulari
2014-11-15 0:15 GMT+00:00 Andrew Pinski :
> On Tue, Sep 30, 2014 at 8:00 AM, Jiong Wang wrote:
>> On 27/09/14 22:20, Kugan wrote:
>>>
>>>
>>> On 23/09/14 01:58, Jiong Wang wrote:
>
> + /* If we decided that we didn't need a leaf frame pointer b
2014-11-15 15:49 GMT+00:00 Andrew Pinski :
>> My local modifications can be found in the gcc git at
>> apinski/thunderx-cost. Note I reverted this patch so I can continue
>> working. The testcase is compiling newlib. Let me try to get it
>> again.
>> I was configuring a combined build with:
>> -
s patch is used to fix this issue.
These cases will be skipped if we don't define
"-mcpu=cortex-m0/m1/m0plus.small-multiply". So no influence to other
targets.
Build gcc passed. Is it OK for trunk?
Thanks and Best Regards,
Hale Wang
gcc/testsuite/ChangeLog:
2014-11-13 Hale Wan
as Pinski reported at
https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01967.html
the previosu LR free patch on AArch64 cause one gcc_assert in lra-elimination.c
one of the problem is that gcc_assert is too strict and overkilled some valid
cases.
the purpose of that assert is described here
2014-11-17 20:36 GMT+00:00 Jeff Law :
> On 11/17/14 02:26, Jiong Wang wrote:
>>
>> as Pinski reported at
>>
>>https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01967.html
>>
>> the previosu LR free patch on AArch64 cause one gcc_assert in
>> lra-e
passed for armv6-m.
OK for trunk?
Thanks,
Hale Wang
libgcc/ChangeLog:
2014-11-26 Hale Wang
* config/arm/lib1funcs.S: Add new wrapper.
===
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index b617137..de66c81
On 01/12/14 15:33, Christophe Lyon wrote:
On 27 November 2014 at 11:35, Ramana Radhakrishnan
wrote:
On Wed, Oct 29, 2014 at 10:20 AM, Jiong Wang wrote:
On 26/08/14 13:36, Richard Earnshaw wrote:
On 29/07/14 15:49, Jiong Wang wrote:
test done
===
no regression on the full toolchain test
On 05/03/15 09:53, Thomas Preud'homme wrote:
*** gcc/testsuite/ChangeLog ***
2015-02-16 Thomas Preud'homme
* gcc.dg/loop-7.c: Run on all targets and check for loop2_invariant
being able to move instructions without introducing new temporary
Thomas,
Can you please confi
Wilco Dijkstra writes:
>> Jeff Law wrote:
>> Can you move pr45685.c into gcc.target/i386?
>>
>> I know Richi said next stage1, but given this fixes a performance
>> regression for ARM and it's reverting rather than adding new code, I
>> think this is OK for the trunk with the testcase moved.
>>
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Joseph Myers
> Sent: Saturday, April 11, 2015 4:30 AM
> To: Hale Wang
> Cc: 'GCC Patches'
> Subject: Re: [PATCH] [1/2] [ARM] [libgcc] Support RT
2015-02-11 18:18 GMT+00:00 Jiong Wang :
> On 11/02/15 14:21, Kenneth Zadeck wrote:
>>
>> On 02/11/2015 06:20 AM, Jiong Wang wrote:
>>>
>>> 2014-12-19 15:21 GMT+00:00 Kenneth Zadeck :
>>>>
>>>> however, since i am a nice person
>&
2015-04-14 18:24 GMT+01:00 Jeff Law :
> On 04/14/2015 10:48 AM, Steven Bosscher wrote:
>>>
>>> So I think this stage2/3 binary difference is acceptable?
>>
>>
>> No, they should be identical. If there's a difference, then there's a
>> bug - which, it seems, you've already found, too.
>
> RIght. An
Ping for trunk?
Hale
> -Original Message-
> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
> Sent: Friday, February 27, 2015 4:04 AM
> To: Terry Guo
> Cc: Segher Boessenkool; Richard Sandiford; GCC Patches; Hale Wang
> Subject: Re: Ping : [PATCH] [gcc
sequence is:
A: mrs tp, tpidr_el0
B0: ldr t0, :gottprel:x1 R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 x1
B1: add t0, t0, tp
B0 and B1 should not be scheduled, as the pattern will be recognized
later for linker IE model to LE model optimization.
2015-06-19 Marcus Shawcroft
Jiong Wang
gcc
Rename test source from tlsle.c into tls.c for reuse purpose.
tls.c will be used as test source file for all TLS test, we just need to
specify different tls options in different testcases.
2015-06-19 Jiong Wang
gcc/testsuite/
* gcc.target/aarch64/tlsle.c: Rename to tls.c
* gcc.target
a0, #:tlsgd_g0_nc:x
add a0, gp, a0
This patch generalize TLS GD code for all memory model and remove the
duplicated define_expand. Another seperate patch will add GD support for
Tiny model.
OK for trunk?
2015-06-19 Jiong Wang
gcc/
* config/aarch64/aarch64-protos.h (aarch64_symbol_context
As we have generalized TLS GD code for all memory model in patch 1,
support for tiny model is quite straightforward. We just need to output
different assembly according to memory model.
2015-06-19 Jiong Wang
gcc/
* config/aarch64/aarch64.md (tlsgd): Support tiny model constraint.
gcc
On 04/05/15 17:37, Alexander Monakov wrote:
This patch introduces option -fno-plt that allows to expand calls that would
go via PLT to load the address of the function immediately at call site (which
introduces a GOT load). Cover letter explains the motivation for this patch.
New option docume
As we have generalized GD Descriptor support for all memory model in
the first patch. Support for tiny model is quite straightforward. We
just need to output different instruction sequences according on memory
model.
OK for trunk?
2015-06-22 Jiong Wang
gcc/
* config/aarch64/aarch64.md
Obivious coding style fix.
2015-06-22 Jiong Wang
gcc/
* config/aarch64/aarch64.c (aarch64_expand_move_immediate): Sort case
label alphabetically.
--
Regards,
Jiong
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 16c8dba..dddf401 100644
--- a/gcc/config
.tlsdesccall var
blr xr
This patch generalize TLS Global Dynamic Descriptor code for all memory
model. Another seperate patch will add descriptor support for Tiny model.
OK for trunk?
2015-06-22 Jiong Wang
gcc/
* config/aarch64/aarch64-protos.h (aarch64_symbol_context): Rename
Marcus Shawcroft writes:
> On 20 May 2015 at 11:21, Jiong Wang wrote:
>
>> gcc/
>> * config/aarch64/aarch64.md: (ldr_got_small_): Support new GOT
>> relocation
>> modifiers.
>> (ldr_got_small_sidi): Ditto.
>> * config/aarch64/iter
Marcus Shawcroft writes:
> On 23 June 2015 at 14:02, Jiong Wang wrote:
>>
>> Marcus Shawcroft writes:
>>
>>> On 20 May 2015 at 11:21, Jiong Wang wrote:
>>>
>>>> gcc/
>>>> * config/aarch64/aarch64.md: (ldr
x27;s attribute better, and by introducing this new
symbol type, we could avoid checking aarch64_cmodel at some extent
though still needs the check somewhere.
All other code logic not changed.
OK for trunk?
Thanks.
2015-06-26 Jiong. Wang
gcc/
* config/aarch64/aarch64-protos.h (
Marcus Shawcroft writes:
> On 26 June 2015 at 10:32, Jiong Wang wrote:
>>
>> This patch respin https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01804.html.
>>
>> A new symbol classification "SYMBOL_SMALL_GOT_28K" added to represent symbol
>> which need
ils patch has been upstreamed already. Please checkout the
latest binutils code.
commit 99ad26cb0d4f9152dbe5ed03b74020cc52d84d94
Author: Jiong Wang
Date: Mon Jun 1 10:26:00 2015 +0100
[AArch64] BFD Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
Thanks.
--
Regards,
Jiong
Andreas Schwab writes:
> Jiong Wang writes:
>
>> Andreas Schwab writes:
>>
>>> spawn -ignore SIGHUP /opt/gcc/gcc-20150627/Build/gcc/xgcc
>>> -B/opt/gcc/gcc-20150627/Build/gcc/ -fno-diagnostics-show-caret
>>> -fdiagnostics-color=never -O0 -w -fpie -
Christophe Lyon writes:
> On 27 June 2015 at 14:49, Jiong Wang wrote:
>>
>> Andreas Schwab writes:
>>
>>> Jiong Wang writes:
>>>
>>>> Andreas Schwab writes:
>>>>
>>>>> spawn -ignore SIGHUP /opt/gcc/gcc-20150627/
This patch fix the breakage caused by
https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01913.html
We fall back to -fPIC if there is no assembler support on those new
relocation modifiers for -fpic.
OK for trunk?
gcc/
* configure.ac: Add check for aarch64 assembler -fpic relocation
modifier
Andreas Schwab writes:
> Jiong Wang writes:
>
>> gcc/
>> * configure.ac: Add check for aarch64 assembler -fpic relocation
>> modifier support.
>> * configure: Regenerate.
>> * config.in: Regenerate.
>> * config/aarch64/aarch64.c (initialize_aa
at 16:39, Marcus Shawcroft wrote:
>> On 20 May 2015 at 12:21, Jiong Wang wrote:
>>>
>>> Add new unspec name UNSPEC_TLSLE, use it for all tlsle pattern.
>>>
>>> ok for trunk?
>>>
>>> 2015-05-19 Jiong Wang
>>>
>>> g
Christophe Lyon writes:
> On 30 June 2015 at 11:12, Jiong Wang wrote:
>>
>> Christophe Lyon writes:
>>
>>> Hi Jiong,
>>>
>>> It seems to me that you committed patches 1/N, 2/N and 3/N as only 1
>>> commit (rev 225121).
>>>
>&
handle.
OK for trunk?
Thanks.
2015-06-30 Jiong Wang
gcc/
* doc/sourcebuild.texi (AArch64-specific attributes): New subsection.
Document "aarch64_small_fpic".
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_aarch64_small_fpic): New
function.
* gcc.target/aarc
James Greenhalgh writes:
> On Mon, Jun 29, 2015 at 01:42:13PM +0100, Jiong Wang wrote:
>>
>> This patch fix the breakage caused by
>>
>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01913.html
>>
>> We fall back to -fPIC if there is no assembler suppo
James Greenhalgh writes:
> On Tue, Jun 30, 2015 at 03:17:00PM +0100, Jiong Wang wrote:
>>
>> As discussed here
>>
>> https://gcc.gnu.org/ml/gcc-patches/2015-06/msg02151.html,
>>
>> Since have enabled binutils feature detection when configuring gcc,
&
committed as 225233.
2015-07-01 Jiong Wang
gcc/
* doc/sourcebuild.texi (AArch64-specific attributes): Document
"aarch64_tiny", "aarch64_small", "aarch64_large",
"aarch64_little_endian", &qu
.
2015-07-06 Jiong Wang
gcc/
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Mark mem as
READONLY and NOTRAP for PIC symbol.
gcc/testsuite/
* gcc.target/aarch64/got_mem_hoist.c: New test.
--
Regards,
Jiong
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config
, may_trap_or_fault_p will be
invoked which will call this target hook.
OK for trunk?
2015-07-07 Jiong Wang
gcc/
* config/aarch64/aarch64.c (aarch64_unspec_may_trap_p): New function.
(TARGET_UNSPEC_MAY_TRAP_P): Define as aarch64_unspec_may_trap_p.
--
Regards,
Jiong
diff --git a/gcc
On 13/01/15 21:45, Jeff Law wrote:
On 01/09/15 06:39, Jiong Wang wrote:
the bug testcase is
===
typedef short U __attribute__((may_alias, aligned (1)));
struct S
{
_Complex float d __attribute__((aligned (8)));
};
void bar(struct S);
void f5 (int x)
{
struct S s
On 15/12/14 08:41, Zhenqiang Chen wrote:
-Original Message-
From: Richard Henderson [mailto:r...@redhat.com]
Sent: Saturday, December 13, 2014 3:26 AM
To: Zhenqiang Chen
Cc: Marcus Shawcroft; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH, AARCH64] Fix ICE in CCMP (PR64015)
- tr
On 15/01/15 03:51, Jeff Law wrote:
On 01/14/15 15:31, Jiong Wang wrote:
agree, and I think the truncation is needed otherwise there may have ICE
on some target.
and I found current gcc LOCATION info is very good !
have done an experimental hack on at "expand_assignment": 4931 wher
On 15/01/15 21:56, Joseph Myers wrote:
On Thu, 15 Jan 2015, Jiong Wang wrote:
+ if (bitsize + bitnum > unit && bitnum < unit)
+{
+ warning (OPT_Wextra, "write of "HOST_WIDE_INT_PRINT_UNSIGNED"bit data "
+ "outside the bound of
On 16/01/15 10:50, Marcus Shawcroft wrote:
On 14 January 2015 at 15:31, Jiong Wang wrote:
2015-01-15 Jiong. Wang (jiong.w...@arm.com)
gcc/
PR64304
* config/aarch64/aarch64.md (define_insn "*ashl3_insn"): Deleted.
(ashl3): Don't expand if operands[2] is not constant.
On 14/01/15 22:59, Richard Henderson wrote:
On 12/15/2014 07:36 AM, Jiong Wang wrote:
+ char buf[64];
+ uint64_t val = ((uint64_t) 1) << UINTVAL (operands[1]);
+ sprintf (buf, "tst\t%%0, %"PRId64, val);
+ output_asm_insn (buf, operands);
+ return
On 19/01/15 10:34, Jakub Jelinek wrote:
On Mon, Jan 19, 2015 at 10:28:47AM +, Jiong Wang wrote:
On 14/01/15 22:59, Richard Henderson wrote:
On 12/15/2014 07:36 AM, Jiong Wang wrote:
+ char buf[64];
+ uint64_t val = ((uint64_t) 1) << UINTVAL (operands[1]);
+ sprint
The volatile register "r1" is totally disappeared in the asm_operands, and
the generated asm code is unexpected.
This patch is used to disable the combine operation if the insns contain
volatile registers. A new test case is also added in this patch.
Is it OK for trun
> -Original Message-
> From: Andrew Pinski [mailto:pins...@gmail.com]
> Sent: Monday, January 26, 2015 6:03 PM
> To: Hale Wang
> Cc: GCC Patches
> Subject: Re: [PATCH] [gcc, combine] PR46164: Don't combine the insns if a
> volatile register is contained.
>
> -Original Message-
> From: Segher Boessenkool [mailto:seg...@kernel.crashing.org]
> Sent: Tuesday, January 27, 2015 3:07 AM
> To: Hale Wang
> Cc: GCC Patches
> Subject: Re: [PATCH] [gcc, combine] PR46164: Don't combine the insns if a
> volatile register is cont
> -Original Message-
> From: Segher Boessenkool [mailto:seg...@kernel.crashing.org]
> Sent: Tuesday, January 27, 2015 12:52 PM
> To: Hale Wang
> Cc: GCC Patches
> Subject: Re: [PATCH] [gcc, combine] PR46164: Don't combine the insns if a
> volatile register is c
rget.
Jakub
testcase changed to execution version, and moved to gcc.dg. the compile time
only
take several seconds. (previously I am using cc1 built by O0 which at most take
24s)
ok to install?
Thanks.
2015-01-19 Ramana Radhakrishnan
Jiong Wang
gcc/
* config/aar
just used to fix this bug. Is it OK for you?
Thanks,
Hale
gcc/ChangeLog:
2015-01-27 Segher Boessenkool
Hale Wang
PR rtl-optimization/64818
* combine.c (can_combine_p): Don't combine the insn if
the dest of insn is a user specified register.
gcc/tes
2015-01-29 14:27 GMT+00:00 Kyrill Tkachov :
>
> On 29/01/15 12:44, Richard Biener wrote:
>>
>>
>> Can you test?
>
two issues during bootstrapping the patch on arm board on top of r220249
* one warning treated as error.
declaration of "new_stmt" need to be removed in
vect_handle_widen_op_by_
On 30/01/15 09:20, Richard Biener wrote:
On Thu, 29 Jan 2015, Jiong Wang wrote:
2015-01-29 14:27 GMT+00:00 Kyrill Tkachov :
On 29/01/15 12:44, Richard Biener wrote:
Can you test?
two issues during bootstrapping the patch on arm board on top of r220249
* one warning treated as error
Ping?
> -Original Message-
> From: Hale Wang [mailto:hale.w...@arm.com]
> Sent: Thursday, January 29, 2015 9:58 AM
> To: Hale Wang; 'Segher Boessenkool'
> Cc: GCC Patches
> Subject: RE: [PATCH] [gcc, combine] PR46164: Don't combine the insns if a
> vol
Ping https://gcc.gnu.org/ml/gcc-patches/2014-12/msg01059.html.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Hale Wang
> Sent: Friday, December 12, 2014 9:36 AM
> To: gcc-patches
> Subject: RE: [Ping] [
2014-12-19 15:21 GMT+00:00 Kenneth Zadeck :
>
> however, since i am a nice person
>
> loop-invariant solves the DF_UD_CHAIN which builds a data structure that
> connects each use with all of the defs that reach it. I believe that this
> is the opposite of what you want here.
>
> if you reall
On 20/01/15 13:26, Maxim Kuvyrkov wrote:
On Jan 20, 2015, at 1:24 PM, Richard Earnshaw wrote:
...
In general, how should someone tuning the compiler for this parameter
select a value that isn't one of (-1, m_i_q_d+1)?
From my experiments it seems there are 4 reasonable values for the paramet
On 11/02/15 14:21, Kenneth Zadeck wrote:
On 02/11/2015 06:20 AM, Jiong Wang wrote:
2014-12-19 15:21 GMT+00:00 Kenneth Zadeck :
however, since i am a nice person
loop-invariant solves the DF_UD_CHAIN which builds a data structure that
connects each use with all of the defs that reach it
> -Original Message-
> From: Segher Boessenkool [mailto:seg...@kernel.crashing.org]
> Sent: Friday, February 13, 2015 6:16 AM
> To: Hale Wang; 'GCC Patches'; Richard Sandiford
> Subject: Re: Ping : [PATCH] [gcc, combine] PR46164: Don't combine the
ins
Ping?
https://gcc.gnu.org/ml/gcc-patches/2014-10/msg02025.html
Thanks
Hale Wang
> -Original Message-
> From: Hale Wang [mailto:hale.w...@arm.com]
> Sent: Tuesday, October 21, 2014 5:57 PM
> To: Hale Wang; gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] Add arm_cortex_m7_tu
Ping?
https://gcc.gnu.org/ml/gcc-patches/2014-10/msg02027.html
Thanks,
Hale Wang
> -Original Message-
> From: Hale Wang [mailto:hale.w...@arm.com]
> Sent: Tuesday, October 21, 2014 6:02 PM
> To: 'gcc-patches@gcc.gnu.org'
> Subject: Small multiplier support
On 26/08/14 13:36, Richard Earnshaw wrote:
On 29/07/14 15:49, Jiong Wang wrote:
test done
===
no regression on the full toolchain test on arm-none-eabi.
ok to install?
Hmm, I think this is wrong for DF mode. The principle the patch works
on is by tying the output to the value containing
This is a ping for
https://gcc.gnu.org/ml/gcc-patches/2014-10/msg01049.html
-- Original message --
From: Wang Deqiang
Date: 11 October 2014 11:27
Subject: [testsuite patch] avoid test when compile options is conflict
with default mthumb
To: gcc-patches@gcc.gnu.org
When
On 01/10/14 09:00, Kugan wrote:
On 01/10/14 01:00, Jiong Wang wrote:
On 27/09/14 22:20, Kugan wrote:
On 23/09/14 01:58, Jiong Wang wrote:
On 22/09/14 16:43, Kugan wrote:
AArch64 has the same issue ARM had where the LR register was not
used in
leaf functions. This was reported in
https
On 04/11/14 15:51, Paolo Carlini wrote:
Hi,
On 11/04/2014 04:37 PM, Martin Jambor wrote:
Hi,
since revision 216728, testsuite/g++.dg/ipa/devirt-40.C is failing
because although the tested-for devirtualization does happen, it is
probably being done earlier and the string we are trying to match
the same ICE will happen on x86-64, if compile with -O2 -fPIC.
the reason is for the following two functions, they are identical, so
IPA-ICF
pass try to transform the second function to call the first one directly.
int
atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b)
{
return __
the problem is caused by constant fold of node with TREE_CLOBBER_P be true.
according to rtl expander, the purpose of clobber is to mark the going out of
scope.
if (TREE_CLOBBER_P (rhs))
/* This is a clobber to mark the going out of scope for
this LHS.
On 07/11/14 10:57, Tejas Belagod wrote:
On 07/11/14 10:35, Richard Biener wrote:
On Fri, Nov 7, 2014 at 11:22 AM, Jiong Wang wrote:
ok to trunk?
Please instead guard the GIMPLE_SINGLE_RHS case in fold_gimple_assign
instead, like
Index: gcc/gimple-fold.c
On 07/11/14 12:53, Martin Liška wrote:
On 11/07/2014 10:52 AM, Jan Hubicka wrote:
On 11/05/14 07:09, Jiong Wang wrote:
the same ICE will happen on x86-64, if compile with -O2 -fPIC.
the reason is for the following two functions, they are identical, so
IPA-ICF
pass try to transform the second
add aarch64 to the target list in gcc.dg/tree-ssa/20040204-1.c
after this fix the XPASS (unexpected pass) gone away on aarch64.
committed as obvious, 217228.
gcc/testsuite/
* gcc.dg/tree-ssa/20040204-1.c: Add aarch64*-*-* to the target list.
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/20040204
one more gnu11 fix for gcc.target/arm/lp1243022.c
(this test only run on arm-none-eabi/-mthumb, just noticed when I go through
bare metal test)
committed as obvious, 217230.
gcc/testsuite/
* gcc.target/arm/lp1243022.c (xhci_test_trb_in_td): Add return type.
(xhci_check_trb_in_td_math): Like
currently, if a testcase use dg-output, then absolute file path will occur
in the test summary reported by dejagnu which is bad. because the summary
should only contain the test name and it's better to exclude all local test
machine info from the report.
dg-output eventually calls dejagnu generic
On 12/11/14 10:01, Yangfei (Felix) wrote:
+ if (GET_MODE (operands[0]) != DImode)
+ FAIL;
shouldn't SImode be considered for -mabi=ilp32 ?
On 12/11/14 14:09, Marek Polacek wrote:
... prune_gcc_output prunes more than just absolute file paths, it
prunes even the "note: " messages. And several ubsan tests have
/* { dg-output "\[^\n\r]*note: pointer points here\[^\n\r]*(\n|\r\n|\r)" } */
but since the note's are already gone, the te
> -Original Message-
> From: Christophe Lyon [mailto:christophe.l...@linaro.org]
> Sent: Wednesday, November 12, 2014 9:49 PM
> To: Hale Wang
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: Small multiplier support in Cortex-M0/1/+
>
> On 21 October 2014 12:01,
... vectorizes with SHRNT/SHRNB
* 32-bit and 8-bit input/output types
* Signed output types
SMULLT/SMULLB are generated instead
SQRDMULH was considered as a potential single-instruction optimization but
saturates the intermediate value instead of truncating.
Best Regards,
Yuliang Wang
Hi Richard,
Thanks for your comments and advice; I have applied the relevant changes.
Regards,
Yuliang
UPDATE:
Added new tests. Built and regression tested on aarch64-none-elf and
aarch64-linux-gnu.
gcc/ChangeLog:
2019-09-1 Yuliang Wang
PR tree-optimization/89386
,
Yuliang Wang
gcc/ChangeLog:
2019-09-19 Yuliang Wang
* match.pd (for cnd (cond vec_cond)): New match statements for the
above patterns.
* doc/sourcebuild.texi (vect_condred_si): Document new target selector.
gcc/testsuite/ChangeLog:
2019-09-19 Yuliang Wang
CTS (arg) ...)
return NULL_TREE;
...
For instance, this causes infinite recursion in
gcc.dg/vect/fast-math-vect-call-2 because ARG is a float literal.
Regards,
Yuliang
-Original Message-
From: Richard Biener
Sent: 20 September 2019 13:02
To: Yuliang Wang
Cc: gcc-patches@gcc.gnu.org;
Andrew Pinski writes:
> On Mon, Jul 27, 2015 at 3:36 AM, James Greenhalgh
> wrote:
>> On Mon, Jul 27, 2015 at 10:52:58AM +0100, pins...@gmail.com wrote:
>>> > On Jul 27, 2015, at 2:26 AM, Jiong Wang wrote:
>>> >
>>> > Andrew Pinski writes:
>
Adhemerval Zanella writes:
>> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
>> index e56398a..2cf239f 100644
>> --- a/gcc/config/aarch64/aarch64.c
>> +++ b/gcc/config/aarch64/aarch64.c
>> @@ -3227,6 +3227,34 @@ aarch64_expand_prologue (void)
>>RTX_FRAME_RELATED_
Jiong Wang writes:
> Andrew Pinski writes:
>
>> On Mon, Jul 27, 2015 at 3:36 AM, James Greenhalgh
>> wrote:
>>> On Mon, Jul 27, 2015 at 10:52:58AM +0100, pins...@gmail.com wrote:
>>>> > On Jul 27, 2015, at 2:26 AM, Jiong Wang wrote:
>>>>
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