Current IRA still use both target macros in a few places.
Tell IRA to use the order we defined rather than with it's own cost
calculation. Allocate caller saved first, then callee saved.
This is especially useful for LR/x30, as it's free to allocate and is
pure caller saved when used in leaf function.
Haven't noticed significant impact on benchmarks, but by grepping some
keywords like "Spilling", "Push.*spill" etc in ira rtl dump, the number
is smaller.
OK for trunk?
2015-05-19 Jiong. Wang <jiong.w...@arm.com>
gcc/
PR 63521
* config/aarch64/aarch64.h (REG_ALLOC_ORDER): Define.
(HONOR_REG_ALLOC_ORDER): Define.
Regards,
Jiong
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index bf59e40..0acdf10 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -337,6 +337,31 @@ extern unsigned long aarch64_tune_flags;
V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \
}
+#define REG_ALLOC_ORDER \
+{ \
+ /* Reverse order for argument registers. */ \
+ 7, 6, 5, 4, 3, 2, 1, 0, \
+ /* Other caller-saved registers. */ \
+ 8, 9, 10, 11, 12, 13, 14, 15, \
+ 16, 17, 18, 30, \
+ /* Callee-saved registers. */ \
+ 19, 20, 21, 22, 23, 24, 25, 26, \
+ 27, 28, \
+ /* All other registers. */ \
+ 29, 31, \
+ /* Reverse order for argument vregisters. */ \
+ 39, 38, 37, 36, 35, 34, 33, 32, \
+ /* Other caller-saved vregisters. */ \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63, \
+ /* Callee-saved vregisters. */ \
+ 40, 41, 42, 43, 44, 45, 46, 47, \
+ /* Other pseudo registers. */ \
+ 64, 65, 66 \
+}
+
+#define HONOR_REG_ALLOC_ORDER 1
+
/* Say that the epilogue uses the return address register. Note that
in the case of sibcalls, the values "used by the epilogue" are
considered live at the start of the called function. */
