[PATCH] Reduction of conditional operations for vectorization

[Yuliang Wang]

Hi,

ifcvt transforms the following conditional operation reduction pattern:

  if ( condition )
    a = a OP b;
  else
    a = a OP c;

Into:

  a_1 = a OP b;
  a_2 = a OP c;
  a = condition ? a_1 : a_2;

Where OP is one of { plus minus mult min max and ior eor }.

This patch further optimizes the above to:

  a_0 = condition ? b : c;
  a = a OP a_0;

Which enables vectorization on AArch64.
Also supported are permutations of the above operand ordering subject to 
commutativity of OP.

Added new tests. Built and regression tested on aarch64-none-elf and 
aarch64-linux-gnu.

Best Regards,
Yuliang Wang


gcc/ChangeLog:

2019-09-19  Yuliang Wang  <yuliang.w...@arm.com>

        * match.pd (for cnd (cond vec_cond)): New match statements for the
        above patterns.
        * doc/sourcebuild.texi (vect_condred_si): Document new target selector.

gcc/testsuite/ChangeLog:

2019-09-19  Yuliang Wang  <yuliang.w...@arm.com>

        * gcc.target/aarch64/sve2/condred_1.c: New test.
        * gcc.dg/vect/vect-condred-1.c: As above.
        * gcc.dg/vect/vect-condred-2.c: As above.
        * gcc.dg/vect/vect-condred-3.c: As above.
        * gcc.dg/vect/vect-condred-4.c: As above.
        * gcc.dg/vect/vect-condred-5.c: As above.
        * gcc.dg/vect/vect-condred-6.c: As above.
        * gcc.dg/vect/vect-condred-7.c: As above.
        * gcc.dg/vect/vect-condred-8.c: As above.
        * lib/target-supports.exp (check_effective_target_vect_condred_si):
        Return true for AArch64 without SVE.

rb11852.patch
Description: rb11852.patch