On 2019-02-09 8:28 a.m., Segher Boessenkool wrote:
Hi Vlad,
On Fri, Feb 08, 2019 at 02:18:40PM -0500, Vladimir Makarov wrote:
Recently I committed a patch solving
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88560
The patch resulted in test vsx-simode2.c failure. Here is the
difference in
On 2019-02-13 5:54 a.m., Andre Vieira (lists) wrote:
PING.
Since Jeff is away can another maintainer have a look at this please?
I see the following patch
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index
c061093ed699620afe2dfda60d58066d6967523a..736b084acc552b75ff4d369b658
. 238991.
2016-08-02 Vladimir Makarov
PR rtl-optimization/69847
* lra-int.h (struct lra-reg): Use restore_rtx instead of
restore_regno.
(lra_rtx_hash): New.
* lra.c (initialize_lra_reg_info_element): Use restore_rtx instead
of restore_regno.
(lra_rtx_hash): Rename and move lra-remat.c
)
@@ -1,5 +1,11 @@
2016-08-02 Vladimir Makarov
+ PR middle-end/72778
+ * lra-spills.c (regno_in_use_p): New.
+ (lra_final_code_change): Use it.
+
+2016-08-02 Vladimir Makarov
+
PR rtl-optimization/69847
* lra-int.h (struct lra-reg): Use restore_rtx instead of
restore_regno.
Index: lra
On 05/26/2016 07:02 AM, Alan Modra wrote:
This fixes lack of bb_loop_depth info in some of the early parts of
ira, which has been the case for quite some time. All active branches
return 0 from bb_loop_depth() in update_equiv_regs, but whether that
actually causes mis-optimization anywhere but t
On 05/26/2016 10:14 PM, Alan Modra wrote:
On Thu, May 26, 2016 at 10:12:14AM -0400, Vladimir Makarov wrote:
On 05/26/2016 07:02 AM, Alan Modra wrote:
This fixes lack of bb_loop_depth info in some of the early parts of
ira, which has been the case for quite some time. All active branches
On 06/06/2016 09:32 AM, Bernd Edlinger wrote:
Ping...
see https://gcc.gnu.org/ml/gcc-patches/2016-05/msg02010.html
Thank you for working on the PR and sorry for the delay with LRA part of
review.
Change in lra-constraints.c is ok for me with the following change.
Instead of just
-
(revision 253795)
+++ ChangeLog (working copy)
@@ -1,3 +1,12 @@
+2017-10-16 Vladimir Makarov
+
+ PR sanitizer/82353
+ * lra.c (collect_non_operand_hard_regs): Don't ignore operator
+ locations.
+ * lra-lives.c (bb_killed_pseudos, bb_gen_pseudos): Move up.
+ (make_hard_regno
===
--- ChangeLog (revision 253862)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-10-18 Vladimir Makarov
+
+ PR middle-end/82556
+ * lra-constraints.c (curr_insn_transform): Use non-input operand
+ instead of output one for matched reload.
+
2017-10-17 Jakub Jelinek
PR tree-optimization
On 10/18/2017 06:48 AM, Segher Boessenkool wrote:
A volatile asm statement can not be moved (relative to other volatile
asm, etc.), but IRA could do it nevertheless. This patch fixes it.
Testing on powerpc64-linux {-m32,-m64}; okay if it succeeds? Also
for backports?
Although I am not an au
On 10/19/2017 06:37 AM, Alexander Monakov wrote:
Ping.
On Thu, 5 Oct 2017, Alexander Monakov wrote:
Bootstrapped and regtested on x86-64, OK for trunk?
OK. Alexander, sorry for the delay with the answer and thank you for
finding and fixing the problem.
PR rtl-optimization/82395
On 08/22/2017 06:48 AM, Wilco Dijkstra wrote:
Hi,
The register allocator inserts move preferences when an instruction has
one or more dead sources in add_insn_allocno_copies. If an instruction
doesn't have a matching constraint (eg. "0"), then any dead source is treated
as a copy with all dest
On 08/28/2017 09:06 AM, Alexander Monakov wrote:
Hello,
The code in record_address_regs shown in the following patch assumes that
if a given target cannot have two registers in a memory address, then the
sole register, if present, must be the leftmost operand in the PLUS chain.
I think this i
On 05/17/2017 07:32 AM, Wilco Dijkstra wrote:
When lra-remat rematerializes an instruction with a clobber, it checks
that the clobber does not kill live registers. However it fails to check
that the clobber also doesn't overlap with the destination register of the
final rematerialized instruct
On 01/16/2017 02:26 PM, Jeff Law wrote:
On 01/13/2017 11:19 AM, Thomas Preudhomme wrote:
Ping? I'm not sure if an ok from Valdimir is enough or if I also need RM
approval.
Vlad's approval is all you need.
Thomas, the patch is ok for backporting. It is pretty safe.
)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-01-17 Vladimir Makarov
+
+ PR target/79058
+ * ira-conflicts.c (ira_build_conflicts): Update total conflict
+ hard regs for inner regno.
+
2017-01-17 Martin Liska
PR ipa/71207
Index: ira-conflicts.c
On 01/17/2017 04:57 PM, Christophe Lyon wrote:
Hi Vladimir,
On 17 January 2017 at 17:14, Vladimir Makarov wrote:
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79058
The patch was successfully bootstrapped and tested on x86-64.
Committed as rev. 244535.
The new
.
Committed as rev. 244942.
Index: ChangeLog
===
--- ChangeLog (revision 244937)
+++ ChangeLog (working copy)
@@ -1,3 +1,16 @@
+2017-01-26 Vladimir Makarov
+
+ PR target/79131
+ * lra-assigns.c (setup_live_pseudos_and_spill_after_risky
===
--- ChangeLog (revision 246466)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-03-24 Vladimir Makarov
+
+ PR target/80148
+ * lra-assigns.c (assign_by_spills): Add spilled non-reload pseudos
+ to consider in curr_insn_transform.
+
2017-03-24 Jakub Jelinek
(working copy)
@@ -1,3 +1,8 @@
+2017-03-28 Vladimir Makarov
+
+ PR rtl-optimization/80193
+ * ira.c (ira): Do not check allocation for LRA.
+
2017-03-28 Alexander Monakov
* config/nvptx/nvptx-protos.h (nvptx_output_simt_enter): Declare.
Index: ira.c
)
+++ ChangeLog (working copy)
@@ -1,3 +1,10 @@
+2017-04-05 Vladimir Makarov
+
+ PR rtl-optimization/70703
+ * ira-color.c (update_costs_from_allocno): Use the smallest mode.
+ (update_conflict_hard_regno_costs): Use long instead of unsigned
+ arithmetic for cost calculation.
+
2017-04-05 Jakub Jelinek
On 04/05/2017 11:25 AM, Jakub Jelinek wrote:
On Wed, Apr 05, 2017 at 11:11:54AM -0400, Vladimir Makarov wrote:
--- ira-color.c (revision 246536)
+++ ira-color.c (working copy)
@@ -1367,6 +1367,16 @@ update_costs_from_allocno (ira_allocno_t
|| ALLOCNO_ASSIGNED_P (another_allocno
On 04/05/2017 12:07 PM, Vladimir Makarov wrote:
I'll correct the patch.
Here is the patch I've committed.
2017-04-05 Vladimir Makarov
PR rtl-optimization/70703
* ira-color.c (update_conflict_hard_regno_costs): Use
HOST_WIDE_INT instead of long.
246763)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-04-07 Vladimir Makarov
+
+ PR rtl-optimization/70478
+ * lra-constraints.c (process_alt_operands): Disfavor alternative
+ insn memory operands.
+
2017-04-07 Jeff Law
* config/iq2000/iq2000.c (final_prescan_insn): Do not separate a
On 04/06/2017 06:24 AM, Richard Biener wrote:
On Wed, Apr 5, 2017 at 6:18 PM, Vladimir Makarov wrote:
On 04/05/2017 12:07 PM, Vladimir Makarov wrote:
I'll correct the patch.
Here is the patch I've committed.
Note that in such contexts it's better to just use [u]int6
On 04/07/2017 05:45 PM, Jakub Jelinek wrote:
On Fri, Apr 07, 2017 at 12:04:16PM -0400, Vladimir Makarov wrote:
Index: ChangeLog
===
--- ChangeLog (revision 246763)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-04-07
. 246808.
Index: ChangeLog
===
--- ChangeLog (revision 246807)
+++ ChangeLog (working copy)
@@ -1,3 +1,12 @@
+2017-04-10 Vladimir Makarov
+
+ PR rtl-optimization/70478
+ * lra-constraints.c (curr_small_class_check): New
On 04/11/2017 03:30 AM, Christophe Lyon wrote:
Hi Vladimir,
On 10 April 2017 at 17:05, Vladimir Makarov wrote:
This is the second try to fix
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70478
The first try patch triggered a latent bug and broke one Fortran testcase
on x86-64
On 04/11/2017 11:42 AM, Vladimir Makarov wrote:
Yes, Christophe. It would be helpful. I've tried to reproduce it but
I don't see the difference in the generated code.
Never mind. I've reproduced it. Thanks.
(revision 246853)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-04-11 Vladimir Makarov
+
+ PR rtl-optimization/70478
+ * lra-constraints.c (process_alt_operands): Check memory for
+ disfavoring memory insn operand.
+
2017-04-11 Jakub Jelinek
PR middle-end/80100
Index: lra-constraints.c
On 04/11/2017 03:30 AM, Christophe Lyon wrote:
Hi Vladimir,
On 10 April 2017 at 17:05, Vladimir Makarov wrote:
This is the second try to fix
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70478
The first try patch triggered a latent bug and broke one Fortran testcase
on x86-64
)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-04-13 Vladimir Makarov
+
+ PR rtl-optimization/80343
+ * lra-remat.c (update_scratch_ops): Assign original hard reg to
+ new scratch pseudo.
+
2017-04-13 Jeff Law
* reload1.c (eliminate_regs_1): Call gen_rtx_raw_SUBREG for SUBREGs
Index: lra
On 09/15/2017 01:38 PM, Alexander Monakov wrote:
Hello,
I'd like to apply the following LRA patch to make qsort comparator
reload_pseudo_compare_func proper (right now it lacks transitivity
due to incorrect use of non_reload_pseudos bitmap, PR 68988).
This function was originally a proper compa
(working copy)
@@ -1,3 +1,8 @@
+2017-09-29 Vladimir Makarov
+
+ PR rtl-optimization/82338
+ * lra-constraints.c (inherit_in_ebb): Check usage_insns check.
+
2017-09-29 Alexander Monakov
* genmodes.c (calc_wider_mode): Suppress qsort macro.
Index: lra-constraints.c
===
--- ChangeLog (revision 253299)
+++ ChangeLog (working copy)
@@ -1,5 +1,11 @@
2017-09-29 Vladimir Makarov
+ PR target/81481
+ * ira-costs.c (scan_one_insn): Don't take into account PIC equiv
+ with a symbol for LRA.
+
+2017-09-29 Vladimir Makarov
+
On 09/30/2017 04:15 AM, Richard Sandiford wrote:
Vladimir Makarov writes:
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81481
The patch was bootstrapped and tested on x86-64.
Committed as rev. 253300.
Index: ira-costs.c
===
--- ChangeLog (revision 253655)
+++ ChangeLog (working copy)
@@ -1,3 +1,12 @@
+2017-10-11 Vladimir Makarov
+
+ PR sanitizer/82353
+ * lra.c (collect_non_operand_hard_regs): Don't ignore operator
+ locations.
+ * lra-lives.c (bb_killed_pseudos, bb_gen_pseudos): Move up.
+ (make_hard_regno
On 10/11/2017 05:11 PM, Jakub Jelinek wrote:
On Wed, Oct 11, 2017 at 03:39:21PM -0400, Vladimir Makarov wrote:
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82353
LRA did not update hard reg liveness on bb borders for hard regs which are
part of insn patterns like
On 10/12/2017 12:49 PM, Jakub Jelinek wrote:
Hi!
On Wed, Oct 11, 2017 at 06:41:05PM -0400, Vladimir Makarov wrote:
Tested on x86_64-linux -m32/-m64, and verified with cc1plus before your
change, ok for trunk?
BTW, I think it is quite fragile to scan for the reload messages, so I've
c
===
--- ChangeLog (revision 244987)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-01-27 Vladimir Makarov
+
+ PR target/79131
+ * lra-assigns.c (find_hard_regno_for_1): Take endianess for into
+ account to calculate conflict_set.
+
2017-01-27 Bin Cheng
PR rtl-optimization/78559
Index: testsuite
)
+++ ChangeLog (working copy)
@@ -1,5 +1,11 @@
2017-01-27 Vladimir Makarov
+ PR tree-optimization/71374
+ * lra-constraints.c (check_conflict_input_operands): New.
+ (match_reload): Use it.
+
+2017-01-27 Vladimir Makarov
+
PR target/79131
* lra-assigns.c (find_hard_regno_for_1): Take endianess
On 02/07/2017 04:17 PM, Jakub Jelinek wrote:
Hi!
As mentioned in the PR, on a huge function init_costs attempts to allocate
124 * 17380077 bytes, 124 is max_struct_costs_size and 17380077
is cost_elements_num. The problem is that the multiplication is done in
int type, so it overflows and we
On 02/07/2017 09:08 AM, Matthew Fortune wrote:
Hi,
This patch addresses a problem with LRA splitting hard registers
where the mode requires multiple registers. When splitting then
each constituent register is split individually using the widest
mode for each register but no check is made that
On 02/07/2017 09:08 AM, Matthew Fortune wrote:
Hi,
This patch partially reverts r243782 where a return false was added
expecting it to be a no-op. Detailed inspection shows this was not
true. Despite no bug being identified following the change, removing
the early return is likely to be safe
On 02/07/2017 09:08 AM, Matthew Fortune wrote:
Hi,
This patch is a minimal change to prevent (subreg(mem)) from being
simplified to use the outer mode for WORD_REGISTER_OPERATIONS. There
is high probability of refining and/or re-implementing this for GCC 8
but such a change would be too invas
On 02/07/2017 09:08 AM, Matthew Fortune wrote:
Hi,
This change deals with reloading a subreg(reg) using the inner mode
to prevent partial spilling of data like in the case described here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78660#c8
No test case for now but I am investigating a targe
On 02/07/2017 09:08 AM, Matthew Fortune wrote:
Hi,
This change deals with reloading a subreg(reg) using the inner mode
to prevent partial spilling of data like in the case described here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78660#c8
No test case for now but I am investigating a targe
On 02/14/2017 01:30 AM, Jeff Law wrote:
So imagine we have two allocnos related by a copy chain (two operand
architecture).
(gdb) p *cp->first
$11 = {num = 9, regno = 33, mode = DImode, wmode = DImode, aclass =
GENERAL_REGS, dont_reassign_p = 0,
bad_spill_p = 0, assigned_p = 1, conflict_ve
)
+++ ChangeLog (working copy)
@@ -1,3 +1,19 @@
+2017-02-14 Vladimir Makarov
+
+ PR target/79282
+ * lra-int.h (struct lra_operand_data, struct lra_insn_reg): Add
+ member early_clobber_alts.
+ * lra-lives.c (reg_early_clobber_p): New.
+ (process_bb_lives): Use it.
+ * lra.c (new_insn_reg): New arg
)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-02-16 Vladimir Makarov
+
+ PR rtl-optimization/78127
+ * lra.c (lra): Call lra_eliminate before finish the loop after
+ lra_constraint.
+
2017-02-16 Richard Biener
* graphite.h: Do not include isl/isl_val_gmp.h, instead include
Index: lra.c
)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-02-17 Vladimir Makarov
+
+ PR rtl-optimization/79541
+ * lra-constraints.c (curr_insn_transform): Remove wrong asm insn
+ instead of transforming it into USE.
+
2017-02-17 Segher Boessenkool
* config/rs6000/rs6000.md (extendsfdf2): Remove default
On 02/24/2017 12:07 AM, Alan Modra wrote:
I'm going to wait for Vlad's opinion. I've written a couple of
replies and erased them, since I figure whatever I have to say doesn't
carry much weight.
I would prefer not to touch simplify_subreg_operand, especially a
code related to subreg of mem
hm is based on choosing an
+ insn alternative first and then calculation of pseudo reg class
+ costs knowing the alternative. The branch is maintained by Vladimir
+ Makarov mailto:vmaka...@redhat.com";>vmaka...@redhat.com.
+
+
libstdcxx_so_7-2-branch
This branch carries all the C++ Ru
On 03/03/2017 08:36 AM, Bernd Schmidt wrote:
Reload is designed in a way to avoid cycles and to process all reloads
for an insn in order of ascending class so as to avoid this kind of
issue. With LRA I'm really not sure how to fix this properly, but the
following patch seems to cure the PR
)
+++ ChangeLog (working copy)
@@ -1,3 +1,10 @@
+2017-03-06 Vladimir Makarov
+
+ PR rtl-optimization/79571
+ * lra-constraints.c (process_alt_operands): Claculate static
+ reject and subtract it from overal when there will be only address
+ reloads.
+
2017-03-06 Julia Koval
PR target/79793
Index
Sorry the ChangeLog entry had typos. Here is the final variant
2017-03-06 Vladimir Makarov
PR rtl-optimization/79571
* lra-constraints.c (process_alt_operands): Calculate static
reject and subtract it from overall when only addresses will be
reloaded.
)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-03-09 Vladimir Makarov
+
+ PR rtl-optimization/79949
+ * lra-constraints.c (process_alt_operands): Check memory when
+ trying to predict a cycle. Print about the overall increase.
+
2017-03-09 Richard Biener
PR middle-end/79971
Index: lra
(revision 246180)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2017-03-15 Vladimir Makarov
+
+ PR target/80017
+ * lra-constraints.c (process_alt_operands): Increase reject for
+ reloading an input/output operand.
+
2017-03-15 Michael Meissner
PR target/79038
Index: lra-constraints.c
On 03/10/2016 03:26 AM, Bernd Schmidt wrote:
This crash happens because LRA tries to save an AVX hard reg in a
large mode, and it only appears in the function in smaller modes.
Stack alignment isn't set up to support the larger mode.
Currently, biggest_mode for hard registers is set up from
r
===
--- ChangeLog (revision 234142)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2016-03-12 Vladimir Makarov
+
+ PR target/69614
+ * lra-constraints.c (delete_move_and_clobber): New.
+ (remove_inheritance_pseudos): Use it.
+
2016-03-11 Kyrylo Tkachov
PR target/70002
Index: testsuite/ChangeLog
===
--- ChangeLog (revision 234526)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2016-03-29 Vladimir Makarov
+
+ PR rtl-optimization/68695
+ * ira-color.c (allocno_copy_cost_saving): New.
+ (improve_allocation): Use it.
+
2016-03-29 Richard
The patch for PR69614 has been backported to gcc-5 branch:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69614
Committed as rev. 234577.
rev. 234649.
Index: ChangeLog
===
--- ChangeLog (revision 234648)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2016-03-31 Vladimir Makarov
+
+ PR rtl-optimization/70461
+ * ira-color.c (allocno_copy_cost_saving): Use allocno
On 03/31/2016 05:35 AM, Christophe Lyon wrote:
On 30 March 2016 at 18:01, Vladimir Makarov wrote:
The patch for PR69614 has been backported to gcc-5 branch:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69614
Committed as rev. 234577.
Hi,
As I've already reported:
https://gcc.gn
On 03/30/2016 05:23 PM, Christophe Lyon wrote:
On 29 March 2016 at 18:28, Vladimir Makarov wrote:
The following patch improves the code in 2 out of 3 cases in
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68695
The patch uses more accurate costs for the RA cost improvement
optimization
On 03/30/2016 05:23 PM, Christophe Lyon wrote:
On 29 March 2016 at 18:28, Vladimir Makarov wrote:
The following patch improves the code in 2 out of 3 cases in
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68695
The patch uses more accurate costs for the RA cost improvement
optimization
On 04/01/2016 01:39 PM, Christophe Lyon wrote:
On 1 April 2016 at 19:34, Vladimir Makarov wrote:
O
Sorry, I tried to reproduce it on today trunk on a real hardware but I've
failed.
You have hardware running big-endian natively?
Oops, I missed that it is a big endian machine. Thanks.
234791)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2016-04-06 Vladimir Makarov
+
+ PR rtl-optimization/70398
+ * lra-constraints.c (process_address_1): Check zero scale and code
+ for reloading with zero scale.
+
2016-04-06 Uros Bizjak
* config/i386/sse.md (shuffletype): Add V32HI and
On 04/10/2016 11:24 PM, Zhouyi Zhou wrote:
save a function call to init_reload when using lra, also remove the a
type error in reload1.c
because init_reload is called only once when compile process, the
performance reduction may not be significant when compiling multi function
source files.
Th
On 04/12/2016 11:14 AM, Jakub Jelinek wrote:
Hi!
Removing DEBUG_INSNs (unless it is removed e.g. together with whole bb
as unreachable code) is always wrong, instead it should be reset,
which indicates we don't know where the var lives (removing it instead
means that the previous DEBUG_INSN for
gcc-patches has rejected the original message as it contained invalid
MIME type. Therefore I am re-sending it.
Forwarded Message
Subject: Re: [lra] Cleanup the use of offmemok and don't count spilling
cost for it
Date: Mon, 4 Jul 2016 15:44:25 -0400
From: Vla
)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2016-07-08 Vladimir Makarov
+
+ PR rtl-optimization/71621
+ * lra-constraints.c (process_alt_operands): Check combination of
+ reg class and mode.
+
2016-06-25 Jason Merrill
Richard Biener
Index: testsuite/ChangeLog
On 07/08/2016 11:07 AM, Thomas Preudhomme wrote:
Hi,
While investigating the root cause a testsuite regression for the
ARM/embedded-5-branch GCC in gcc.dg/vect/slp-perm-5.c, we found that the bug
seems to also affect trunk. The bug manifests itself as an ICE in cselib due to
a parallel insn with
)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2016-12-06 Vladimir Makarov
+
+ target/77761
+ * lra-lives.c (process_bb_lives): Update biggest mode for
+ implicitly used hard reg.
+
2016-12-06 Uros Bizjak
* config/i386/predicates.md (general_gr_operand): New predicate.
Index: testsuite/ChangeLog
On 05/11/2016 01:39 AM, Alexander Monakov wrote:
On Wed, 30 Mar 2016, Bernd Schmidt wrote:
On 03/25/2016 04:43 AM, Aldy Hernandez wrote:
If Bernd is fine with this, I'm happy to retract my patch and any
possible followups. I'm just interested in having no path causing a
possible out of bounds
On 05/17/2016 06:02 AM, Jiong Wang wrote:
This bug is introduced by my commit r236181 where the inner rtx of
SUBREG haven't been checked while it should as "in_class_p" only
works with REG, and SUBREG_REG is actually not always REG. If REG_P
check failed, then we should fall back to normal code
On 08/28/2015 06:07 AM, Anatoliy Sokolov wrote:
Hi.
This patch remove static reg_class_names array from
print_translated_classes and print_unform_and_important_classes
functions. Global reg_class_names array is used instead.
Bootstrapped and reg-tested on x86_64-unknown-linux-gnu and
powerpc
The following patch is for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61578
The patch was bootstrapped and tested on x86 and x86-64.
Committed as rev. 227382.
2015-09-01 Vladimir Makarov
PR target/61578
* lra-lives.c (process_bb_lives): Process move pseudos with
On 09/02/2015 11:32 AM, Christophe Lyon wrote:
Hi Vladimir,
On 1 September 2015 at 21:39, Vladimir Makarov wrote:
The following patch is for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61578
The patch was bootstrapped and tested on x86 and x86-64.
Committed as rev. 227382
On 09/03/2015 11:00 AM, Vladimir Makarov wrote:
On 09/02/2015 11:32 AM, Christophe Lyon wrote:
Hi Vladimir,
On 1 September 2015 at 21:39, Vladimir Makarov
wrote:
The following patch is for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61578
The patch was bootstrapped and tested on
On 12/17/2015 04:00 AM, Yury Gribov wrote:
This patch fixes intransitive comparison in
reload_pseudo_compare_func. Imagine the following
situation:
1) bitmap_bit_p is unset for A and B but set for C
2) A < B (due to early ira_reg_class_max_nregs comparison)
3) B < C (due to following regno_assig
On 12/14/2015 08:05 AM, Andreas Krebbel wrote:
Hi,
the constraint modifier % applies to all the alternatives of a pattern
and hence is mostly added to the first constraint of an operand. IRA
currently ignores it if the alternative with the % gets disabled by
using the `enabled' attribute or if
On 01/08/2016 03:13 PM, Jakub Jelinek wrote:
Hi!
The following testcase ICEs, because move_plus_up attempts to
optimize (subreg:HI (plus:SI (...) (const_int 0xff78)) 0)
into (plus:HI (subreg:HI (...) 0) (const_int 0xff78)) which is
incorrect, HImode CONST_INT with MSB set should be (const_int -1
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69030
The patch was bootstrapped and tested on x86 and x86-64.
Committed as rev. 232445.
2016-01-15 Vladimir Makarov
PR rtl-optimization/69030
* lra-spills.c (remove_pseudos): Check nrefs and make
used.
The patch was successfully bootstrapped and tested on x86-64.
Ok to commit to the trunk?
2014-12-05 Vladimir Makarov
PR rtl-optimization/64157
* toplev.c (target_reinit): Call ira_init.
Index: toplev.c
On 2014-12-08 10:41 AM, Richard Sandiford wrote:
Vladimir Makarov writes:
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64157
After calling target_reinit from save_target_globals for switchable
targets (as ppc), a lot of ira data (register sets, classes etc
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64110
The patch was successfully tested and bootstrapped on x86/x86-64.
Committed as rev. 218688.
2014-12-12 Vladimir Makarov
PR target/64110
* lra-constraints.c (process_alt_operands): Refuse
On 2014-12-15 9:14 AM, Christophe Lyon wrote:
Hi,
After this commit, GCC build fails for ARM targets:
--target=arm-none-eabi --with-mode=arm --with-cpu=cortex-a9 --with-fpu=neon
full bug report,
Can you have a look?
Sure. Sorry for inconvenience. LRA/reload bug fixing is a complicated
My last patch for PR64110 results in LRA crash on ARM on compilation
of some programs. There is no PR for it. Here is the patch fixing the
occurred problem.
The patch was tested and bootstrapped on x86/x86-64 and ARM.
Committed as rev. 218760.
2014-12-15 Vladimir Makarov
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62642
The patch was successfully bootstrapped on x86-64.
It is difficult for me to make a testcase to check the right code
generation. So the patch has no test.
Committed as rev. 218761.
2014-12-15 Vladimir
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63397
The patch was successfully bootstrapped on x86-64.
Committed as rev. 218766.
2014-12-15 Vladimir Makarov
PR rtl-optimization/63397
* ira-int.h (ira_overall_cost, ira_reg_cost, ira_mem_cost): Use
H.J. reported a failure for PR64110 test.
Here is the patch solves it.
The patch was bootstrapped on x86/x86-64/arm.
Committed as rev. 218835.
2014-12-17 Vladimir Makarov
* lra-constraints.c (process_alt_operands): Remove non
allocatable hard regs when considering
On 2014-12-17 7:56 PM, Kaz Kojima wrote:
This patch series is to make SH target use LRA and is discussed
in the PR target/55212:
[SH] Switch to LRA
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
I think there are issues which should be solved before defaulting
LRA on SH and the helps from t
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64291
It is a bug in a new rematerialization subpass of LRA.
The patch was bootstrapped on x86/x86-64.
Committed as rev. 218874.
2014-12-18 Vladimir Makarov
PR rtl-optimization/64291
* lra-remat.c
On 2014-12-17 8:00 PM, Kaz Kojima wrote:
This was discussed in PR55212
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c25
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c58
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c69
and is to fix another ICEs in assign_by_spills.
This patch
On 2014-12-17 7:59 PM, Kaz Kojima wrote:
This was discussed in PR55212
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c52
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c53
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c55
and is to fix ICE in assign_by_spills.
In that case, rtlana
On 2014-12-18 2:26 PM, Mike Stump wrote:
On Dec 18, 2014, at 10:42 AM, Vladimir Makarov wrote:
Thank you very much for your work on porting LRA to SH!
I’ve ported my target to LRA, and I have not found any LRA bits I needed to
change.
Thanks, Mike. When I did a few first ports, it never
On 2014-12-17 8:00 PM, Kaz Kojima wrote:
This patch adds a target macro discussed in PR55212
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c76
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c78
is to avoid bad codes on SH.
SH has very limited base+displacement addressing and it looks
t
On 2014-12-17 7:57 PM, Kaz Kojima wrote:
This patch is discussed in PR55212
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c47
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c48
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c49
and is to avoid segfault in remove_pseudos.
In the pro
The following patch fixes a typo in usage of register_move_cost. For
most targets, the change does not matter as the cost function is
symmetric relative to args.
The patch was bootstrapped on x86-64.
Committed as rev. 218875.
2014-12-18 Vladimir Makarov
* lra-constraints.c
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