On 02/07/2017 09:08 AM, Matthew Fortune wrote:
Hi,
This patch addresses a problem with LRA splitting hard registers
where the mode requires multiple registers. When splitting then
each constituent register is split individually using the widest
mode for each register but no check is made that such a mode is
actually supported in those registers.
MIPS has an ABI variant o32 FPXX that allows DFmode values to
exist in pairs of 32-bit floating point registers but only the
first 32-bit register is directly addressable. The second
register can only be accessed as part of a 64-bit load/store or
via a special move instruction used as part of a 64-bit move.
The split is simply rejected to ensure compliance with the ABI
although I expect the split logic could account for this case
and split using the wider mode. Such a change appears more
invasive than appropriate in stage 4.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78012
It is unknown if any other LRA enabled target could hit this
issue but it is certainly possible depending on mode/register
restrictions.
The patch is ok for the trunk and it is pretty safe. Thank you Robert
and Matt.
