On 10/30/24 18:11, Jeff Law wrote:
> On 10/20/24 1:40 PM, Vineet Gupta wrote:
>> Background
>> --
>> sched1 runs a preliminary "model schedular" ahead of the main list schedular.
>> Its sole purpose is to keep register pressure to mimimum [1] and
On 10/30/24 14:13, Jeff Law wrote:
> On 10/29/24 6:11 PM, Vineet Gupta wrote:
>> When bisecting for ICE in PR/117353, commit 771256bcb9dd ("RISC-V: Emit
>> costs for
>> bool and stepped const vectors") uncovered yet another latent issue (first
>> noted
Ping !
On 10/20/24 12:40, Vineet Gupta wrote:
> Hi,
>
> PFA patch series which improves sched1 spilling. This all started with
> SPEC2017 507.Cactu dynamic icounts on RISC-V being double than those of
> aarch64 (~2.6 trillion vs. ~1.4 trillion). Robin/Jeff hinted that the
> iss
On 10/22/24 12:02, rep.dot@gmail.com wrote:
>> +/* { dg-final { scan-assembler-times "%sfp" 0 } } */
> scan-assembler-not, please
Fixed and also in the other patch.
Thx,
-Vineet
gcc.target/riscv/rvv/autovec/slp-interleave-5.c: New test.
Tested-by: Edwin Lu # Pre-commit CU #2503
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-v.cc | 6 ++--
.../riscv/rvv/autovec/slp-interleave-5.c | 35 +++
2 files changed, 38 insert
On 11/6/24 12:11, Vineet Gupta wrote:
> changes since v1
> * Changed target hook to --param
> * squash addon patch for RISC-V opting-in, testcase here
> * updated changelog with latest perf numbers
ping !
> ---
>
> sched1 computes ECC (Excess Change Cost) for each i
On 11/6/24 14:20, Vineet Gupta wrote:
> This is broken out of predecessor promotion patch so that debugging can
> proceed during stage1 restrictions.
>
> Signed-off-by: Vineet Gupta
ping !
> ---
> gcc/haifa-sched.cc | 10 +-
> gcc/sched-rgn.cc | 14
bb.
* sched-rgn.cc (debug_dependencies): Dump SD_LIST_HARD_BACK deps.
Signed-off-by: Vineet Gupta
---
gcc/haifa-sched.cc | 10 +-
gcc/sched-rgn.cc | 14 --
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/gcc/haifa-sched.cc b/gcc/haifa-sched.cc
index cd4b6badd
PR target/114729
* gcc.target/riscv/riscv.exp: Enable new tests to build.
* gcc.target/riscv/sched1-spills/spill1.cpp: Add new test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 4 +++
gcc/doc/invoke.texi |
On 12/4/24 11:48, Jonathan Wakely wrote:
>> gcc/ChangeLog:
>> PR target/11472
> Note that you typo'd the PR number here, so that it added a comment
> to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=11472
Apologies my bad.
In my defense I ran following:
./contrib/gcc-changelog/git_check_comm
On 12/4/24 11:52, Jonathan Wakely wrote:
>> I see you've been using the PR/nnn form for all your commits, please
>> use the [PRnnn] form as described at
>> https://gcc.gnu.org/contribute.html#patches
> Also it looks like the actual component in bugzilla is
> "rtl-optimization" not "target", so sho
-authored-by: Pan Li
Signed-off-by: Vineet Gupta
PR target/117722
gcc/ChangeLog:
* config/riscv/autovec.md: Add uabd expander.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr117722.c: New test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/autovec.md
: Vineet Gupta
---
gcc/config/riscv/vector.md| 16 ++---
.../cond/cond_convert_int2int-rv32-1.c| 4 ++--
.../cond/cond_convert_int2int-rv32-2.c| 4 ++--
.../cond/cond_convert_int2int-rv64-1.c| 4 ++--
.../cond/cond_convert_int2int-rv64-2.c
-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.opt| 4
gcc/config/riscv/vector.md| 20 +---
.../cond/cond_convert_int2int-rv32-1.c| 4 ++--
.../cond/cond_convert_int2int-rv32-2.c| 4 ++--
.../cond/cond_convert_int2int-rv64
On 12/20/24 17:16, Andrew Pinski wrote:
> On Fri, Dec 20, 2024 at 2:14 PM Vineet Gupta wrote:
>> This improves codegen for x264 sum of absolute difference routines.
>> The insn count is same, but we avoid double widening ops and ensuing
>> whole register moves.
>&g
-developed-by: Pan Li
Signed-off-by: Vineet Gupta
PR target/117722
gcc/ChangeLog:
* config/riscv/autovec.md: Add uabd expander.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr117722.c: New test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/autovec.md
variant.
Suggested-by: Robin Dapp
Co-developed-by: Pan Li
Signed-off-by: Vineet Gupta
PR target/117722
gcc/ChangeLog:
* config/riscv/autovec.md: Add uabd expander.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr117722.c: New test.
Signed-off-by: Vineet Gupta
#2.370 M/sec
| 15,403,357 branch-misses:u #0.14% of all
branches
|
| 4556.445490123 seconds time elapsed
Fixes: 46888571d242 "RISC-V: Add cr and cf constraint"
Signed-off-by: Vineet Gupta
gcc/ChangeLog:
* config/riscv/riscv.cc
get/118103
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_emit_frm_mode_set): Use volatile
fsrmi restore.
gcc/testsuite/ChangeLog:
* gfortran.target/riscv/rvv/pr118646.f90 (New Test).
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 2 +-
.../
On 1/26/25 05:29, Jeff Law wrote:
>
> On 1/24/25 3:12 PM, Vineet Gupta wrote:
>> RV-Vector FP-INT insns use the rounding mode in FRM register which if
>> explicitly set for V insn needs, is saved/restored (although from the
>> psABI CC Spec, it is not clear if it ac
aborts in
glibc:round_away() due to non-canonical rounding mode showing up,
"leaking" earlier in the call chain because such rounding mode
save/restore was getting eliminated.
PR target/118646
gcc/testsuite/ChangeLog:
* gfortran.target/riscv/rvv/pr118646.f90 (New Test).
S
On 1/26/25 05:33, pan2...@intel.com wrote:
> From: Pan Li
>
> After we add the frm register to the global_regs, we may not need to
> define_insn that volatile to emit the frm restore insns. The
> cooperatively-managed global register will help to handle this, instead
> of emit the volatile define
On 1/20/25 19:07, Li, Pan2 wrote:
> Agree, the mode-switch will take care of the frm when meet a call (covered by
> testcase already).
>
>5 │
>6 │ extern size_t normalize_vl_1 (size_t vl);
>7 │ extern size_t normalize_vl_2 (size_t vl);
>8 │
>9 │ vfloat32m1_t
> 10
#2.370 M/sec
| 15,403,357 branch-misses:u #0.14% of all
branches
|
| 4556.445490123 seconds time elapsed
Fixes: 46888571d242 ("RISC-V: Add cr and cf constraint")
Signed-off-by: Vineet Gupta
gcc/ChangeLog:
* config/riscv/riscv.cc
On 1/13/25 18:08, Kito Cheng wrote:
> Thanks, that's apparently my stupid mistake...:P
No worries. We've all done that many times over !
Cheers,
-Vineet
On 1/16/25 15:07, Vineet Gupta wrote:
> +CC Juzhe, Robin, gcc patches mailing list
>
> On 1/16/25 14:49, Andrew Waterman wrote:
>> On Thu, Jan 16, 2025 at 11:43 AM Vineet Gupta wrote:
>>> On 1/16/25 11:14, Joseph Myers wrote:
>>>> The simple thing to do is to c
at this doesn't help chase the problem down.
I'm running reducer - will update in proper gcc channels.
Thx,
-Vineet
>
> Pan
>
> -Original Message-
> From: Vineet Gupta
> Sent: Friday, January 17, 2025 9:28 AM
> To: Andrew Waterman
> Cc: Joseph Mye
On 2/13/25 20:46, Jeff Law wrote:
>> BTW what exactly is speculative scheduling ? As in what is it actually
>> trying to
>> schedule ahead ?
> In simplest terms assume we have this kind of graph
>
> 0
> / \
>1-->2
>
>
> The scheduler knows how to build scheduling regions, essentially
On 2/13/25 14:17, Robin Dapp wrote:
Other thoughts?
>>> The docs seem to hint TARGET_SCHED_CAN_SPECULATE_INSN is meant for stuff
>>> we can't/don't model in the pipeline, but I have no idea how to model
>>> the VL=0 case there.
>> Maybe so, but what Edwin is doing looks sensible enough. It
On 2/8/25 23:02, Jeff Law wrote:
> On 2/7/25 9:34 PM, Vineet Gupta wrote:
>> A couple of Vector pseudoinstructions use x0 scalar which being regfile
>> crosser could be inefficient on certain wider uarches.
>>
>> Use the imm 0 form, which should be functionally equ
.
* gcc.target/riscv/rvv/autovec/vls/trunc-3.c: Ditto.
* gcc.target/riscv/rvv/base/simplify-vdiv.c: Ditto.
* gcc.target/riscv/rvv/base/unop_v_constraint-1.c: Ditto.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/vector.md| 16 ++---
.../cond
splitter.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr117722.c: Adjust output insn.
* gcc.target/riscv/rvv/autovec/pr119224.c: Add new test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/autovec.md | 2 +-
.../gcc.target/riscv/rvv/autovec/pr117722.c
Hi,
On 12/3/24 03:02, Jiawei wrote:
> This patch series introduces support for RISC-V Profiles RV20, RV22[1],
> and RV23[2][3].The updates enhance compatibility and streamline the process
> of leveraging RISC-V Profiles through the -march option. These additions
> are in line with the RISC-V stand
On 4/1/25 17:44, Jeff Law wrote:
> On 4/1/25 12:15 PM, Vineet Gupta wrote:
>> On 3/31/25 23:48, Heinrich Schuchardt wrote:
>>> On 3/30/25 01:49, Vineet Gupta wrote:
>>>> changes since v2
>>>>- dump log sanfu
>>>>
>>>> ---
>&
On 3/29/25 17:58, Jeff Law wrote:
> On 3/29/25 6:49 PM, Vineet Gupta wrote:
>> changes since v2
>> - dump log sanfu
>>
>> ---
>> vsetvl phase4 uses LCM guided info to insert VSETVL insns.
>> It has an additional loop to insert missing vsetvls on certain e
On 3/31/25 21:54, Jeff Law wrote:
> And if that's the case then you can't simply skip an abnormal edge. You
> have to do something sensible.
>
> That "something sensible" has traditionally been to ensure there is
> never a need propagated to an edge since you can't insert on an abnormal
> criti
On 4/8/25 02:12, Robin Dapp wrote:
>> However we still see lift up using those blocks - the earliest set computed
>> contained the supposedly elided bbs.
>>
>> Try lift up 0.
>>
>> earliest:
>> Edge(bb 16 -> bb 17): n_bits = 3, set = {1 }
>>
>> Try lift up 1.
>>
>>
On 4/8/25 12:27, Robin Dapp wrote:
Yay ! It does work. Awesome.
I've uploaded the further reduced test to PR/119533
>>> Hmm, I'm seeing the same ICE as before with my patch. Did you happen to
>>> change
>>> something else on your local tree still?
Yeah I had some debug stuff lying aro
g past
non-transparent blocks: That is taken care of by Robin's patch
"RISC-V: Do not lift up vsetvl into non-transparent blocks [PR119547]"
or a different yet related issue.
Reported-by: Heinrich Schuchardt
Signed-off-by: Vineet Gupta
PR target/119533
gcc/ChangeLog:
* con
Hi Robin,
On 4/8/25 21:56, Robin Dapp wrote:
Yay ! It does work. Awesome.
I've uploaded the further reduced test to PR/119533
>>> Hmm, I'm seeing the same ICE as before with my patch. Did you happen
>>> to change
>>> something else on your local tree still?
Ye
On 3/31/25 12:39, Jeff Law wrote:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): skip
EDGE_ABNORMAL.
gcc/testsuite/ChangeLog:
* go.dg/pr119533-riscv.go: New test.
>>> So presumably it wants to insert on the EH edge for a reason. Just
>>> skipping t
On 3/31/25 23:48, Heinrich Schuchardt wrote:
> On 3/30/25 01:49, Vineet Gupta wrote:
>> changes since v2
>> - dump log sanfu
>>
>> ---
>> vsetvl phase4 uses LCM guided info to insert VSETVL insns.
>> It has an additional loop to insert missing vsetvls on
On 4/8/25 16:32, Vineet Gupta wrote:
>>>>>> Yay ! It does work. Awesome.
>>>>>> I've uploaded the further reduced test to PR/119533
>>>>> Hmm, I'm seeing the same ICE as before with my patch. Did you happen to
>>>>> cha
On 4/8/25 13:47, Vineet Gupta wrote:
> On 4/8/25 12:27, Robin Dapp wrote:
>>>>> Yay ! It does work. Awesome.
>>>>> I've uploaded the further reduced test to PR/119533
>>>> Hmm, I'm seeing the same ICE as before with my patch. Did you happen
Hi Pan,
On 4/27/25 18:33, Li, Pan2 wrote:
> Kindly ping.
Sorry this got backed up as I'm working on FRM overhaul - if this is not super
urgent can you please wait for a few weeks for my work to be posted.
If you prefer this go in still, fine by me as well.
Thx,
-Vineet
>
> Pan
>
> -Origina
On 4/30/25 20:44, Jeff Law wrote:
> On 4/30/25 6:03 PM, Li, Pan2 wrote:
>>> Sorry this got backed up as I'm working on FRM overhaul - if this is not
>>> super
>>> urgent can you please wait for a few weeks for my work to be posted.
>>> If you prefer this go in still, fine by me as well.
>> Sure
On 4/30/25 20:44, Jeff Law wrote:
>>> Sorry this got backed up as I'm working on FRM overhaul - if this is not
>>> super
>>> urgent can you please wait for a few weeks for my work to be posted.
>>> If you prefer this go in still, fine by me as well.
>> Sure thing, feel free to ping me if there is
g past
non-transparent blocks: That is taken care of by Robin's patch
"RISC-V: Do not lift up vsetvl into non-transparent blocks [PR119547]"
for a different yet related issue.
Reported-by: Heinrich Schuchardt
Signed-off-by: Vineet Gupta
PR target/119533
gcc/ChangeLog:
On 3/3/25 15:18, Andrew Waterman wrote:
>> So in some convoluted way both the above scenarios have callee-saved
>> semantics
>> for FRM, except for the leaf function which unconditionally sets FRM where
>> this
>> save/restore is not done.
> I don't follow the last part about leaf functions. Unl
Hi Pan, Andrew
I'm trying to understand the semantics of FRM as it intersects with calling
convention.
psABI is not explicit about it and refers to C standard [1]
> On 2/14/25 03:39, Li, Pan2 wrote:
[snip]
> With option "-march=rv64gcv_zvfh -O3"
>
> 10 │ vxrm:
> 11 │ csrwi vxrm,
On 2/14/25 04:58, Jeff Law wrote:
> I'd guess it more work than it'd be worth. We're just not seeing
> vsetvls being all that problematical on our design. I do see a lot of
> seemingly gratutious changes in the vector config, but when we make
> changes to fix that we generally end up with wors
On 2/24/25 16:07, Edwin Lu wrote:
> See [1] thread for original patch which spawned this one.
>
> We are currently seeing the following code where we perform a vsetvl
> before a branching instruction against the avl.
>
> vsetvli a5,a1,e32,m1,tu,ma
> vle32.v v2,0(a0)
> sub
|0 / 0 |
PR target/119533
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): skip
EDGE_ABNORMAL.
gcc/testsuite/ChangeLog:
* go.dg/pr119533-riscv.go: New test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-vsetvl.cc
On 3/29/25 13:36, Andreas Schwab wrote:
>> + if (eg->flags & EDGE_ABNORMAL)
>> +{
>> + fprintf (dump_file, "\nskipping EDGE_ABNORMAL\n");
> This will crash if dump_file is NULL.
Sorry, last minute update.
Fixed, v2 posted.
Thx,
-Vineet
splitter.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr117722.c: Adjust output insn.
* gcc.target/riscv/rvv/autovec/pr119224.c: Add new test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/autovec.md | 3 ++-
.../gcc.target/riscv/rvv/autovec/pr117722.c
/119533
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): skip
EDGE_ABNORMAL.
gcc/testsuite/ChangeLog:
* go.dg/pr119533-riscv.go: New test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-vsetvl.cc | 6 +-
gcc/testsuite/go.dg/pr119533
On 3/25/25 00:45, Robin Dapp wrote:
>> - "TARGET_VECTOR"
>> + "TARGET_VECTOR && 0"
> Would you mind adding a comment here before committing, maybe even reference
> the PR? Not that we want to keep this around for long anyway but just to
> make
> sure :)
Of course, I pondered the same but the
and skip the
restore.
I've yet to figure out the implementation though.
Thx,
-Vineet
>
> ----
> juzhe.zh...@rivai.ai
>
>
> *From:* Vineet Gupta <mailto:vine...@rivosinc.com>
>
On 5/12/25 14:55, Jeff Law wrote:
test_float_point_frm_static:
1: frrma5 <--
2: fsrmi 2
3: fsrma5 <--
4: callnormalize_vl
5: frrma5 <--
6: fsrmi 3
7: fs
build, it ends up generating
net more FRM restores (writes) vs. the rest of this changeset.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_dynamic_frm_mode_p): Remove.
(riscv_mode_confluence): Ditto.
(TARGET_MODE_CONFLUENCE): Ditto.
Signed-off-by: Vineet Gupta
---
gcc/co
intenance.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_frm_mode_needed): Move static
state update here.
(frm_unknown_dynamic_p): Delete.
(riscv_frm_mode_after): Delete.
(riscv_mode_after): Remove call to riscv_frm_mode_after ().
Signed-off-by: Vineet Gupta
/ChangeLog:
* config/riscv/riscv.cc (riscv_emit_frm_mode_set): check
STATIC_FRM_P for trnsition to DYN.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv
23
xz_r600 600
---
4551 55 26234498 55 2623
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_frm_emit_after_bb_end): Delete.
(riscv_frm_mode_needed): Remove call riscv_frm_emit_a
nvestigated but could take more time.
Please review.
Thx,
-Vineet
Vineet Gupta (6):
emit-rtl: document next_nonnote_nondebug_insn_bb () can breach into
next BB
RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
RISC-V: frm/mode-switch: remove dubious frm edge insertion before
cal
ove.
(riscv_frm_mode_needed): Track call_insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c: Bump
expected FRRM by 1.
* gcc.target/riscv/rvv/base/pr119164.c: New test.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv
gcc/ChangeLog:
* emit-rtl.cc (next_nonnote_nondebug_insn): Update comments.
Signed-off-by: Vineet Gupta
---
gcc/emit-rtl.cc | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/gcc/emit-rtl.cc b/gcc/emit-rtl.cc
index 3e2c4309dee6..b78b29ecf989 100644
--- a/gcc/emit
On 5/10/25 07:17, Jeff Law wrote:
> On 5/9/25 2:27 PM, Vineet Gupta wrote:
>> This showed up when debugging the testcase for PR119164.
>>
>> RISC-V FRM mode-switching state machine has special handling for transitions
>> to and from a call_insn as FRM needs to saved
On 5/10/25 06:49, Jeff Law wrote:
> On 5/9/25 2:27 PM, Vineet Gupta wrote:
>> Hi,
>>
>> This came out of Rivos perf team reporting (shoutout to Siavash) that
>> some of the SPEC2017 workloads had unnecessary FRM wiggles, when
>> none were needed. The writes
On 5/12/25 17:26, Jeff Law wrote:
>>test_float_point_frm_static:
>>1: frrma5 <--
>> 2: fsrmi 2
>>3: fsrma5 <--
>> 4: callnormalize_vl
>>5: frrma5 <--
>> 6: fsrmi 3
On 5/10/25 07:27, Jeff Law wrote:
>
> On 5/9/25 2:27 PM, Vineet Gupta wrote:
>> Stumbled upon this when trying to wholesale rewrite frm switching code
>> and seeing what pieces needed to be retained from current implementation.
>>
>> My interpretation of how this
On 5/13/25 10:07, Vineet Gupta wrote:
>
>
> On 5/10/25 07:20, Jeff Law wrote:
>> On 5/9/25 2:27 PM, Vineet Gupta wrote:
>>> This is effectively reverting e5d1f538bb7d
>>> "(RISC-V: Allow different dynamic floating point mode to be merged)"
>>&
On 5/9/25 13:27, Vineet Gupta wrote:
> FRM mode switching state machine has DYN as default state which it also
> fallsback to after transitioning to other states such as DYN_CALL.
> Currently TARGET_MODE_EMIT generates a FRM restore on any transition to
> DYN leading to spurious/ex
+CC @pinskia
On 5/10/25 06:55, Jeff Law wrote:
>
> On 5/9/25 2:27 PM, Vineet Gupta wrote:
>> gcc/ChangeLog:
>>
>> * emit-rtl.cc (next_nonnote_nondebug_insn): Update comments.
>>
>> Signed-off-by: Vineet Gupta
>> ---
>> gcc/emit-rtl.cc |
On 5/22/25 05:12, Robin Dapp wrote:
>>> AFAICT the main difference to standard mode switching is that we (ab)use it
>>> to set the rounding mode to the value it had initially, either at function
>>> entry or after a call. That's different to regular mode switching which
>>> assumes "static" rou
On 5/26/25 01:18, Robin Dapp wrote:
>> 2. OK'ish: A bunch of testcases see more reads/writes as PRE of redundant
>> read/writes is punted to later passes which obviously needs more work.
>>
>> 3. NOK: We loose the ability to instrument local RM writes - especially in
>> the
>> testsuite.
>> e.g.
arc700 is legacy and there's no active development for it, so switch to
latest hs38_linux as default
Signed-off-by: Vineet Gupta
---
gcc/config/arc/arc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index bd1fe0a
//Claudiu
> ----
> *From:* Vineet Gupta
> *Sent:* Tuesday, June 1, 2021 10:42 PM
> *To:* gcc-patches@gcc.gnu.org
> *Cc:* Claudiu Zissulescu ;
> linux-snps-...@lists.infradead.org
> ; Vineet Gupta
> *Subject:* [PATCH] ARC: gcc driver default to
Enable big-endian suffixed dynamic linker per glibc multi-abi support.
And to avoid a future churn and version pairingi hassles, also allow
arc700 although glibc for ARC currently doesn't support it.
gcc/
-xx-xx Vineet Gupta
+
+ * config/arc/linux.h: GLIBC_DYNAMIC_LINKER suppo
uesday, March 31, 2020 1:07 PM
>> To: Vineet Gupta
>> Cc: linux-snps-...@lists.infradead.org; gcc-patches@gcc.gnu.org; Claudiu
>> Zissulescu
>>
>> Subject: Re: [PATCH] [ARC] Allow more ABIs in GLIBC_DYNAMIC_LINKER
>>
>> Pushed.
> Is this one eligible for being back-ported to older GCCs?
> At least GCC 9.x would be really good.
>
> -Alexey
>
FWIW this change needs a pairing glibc change so must NOT be included for
upcoming
2020.x release which still has old version of glibc !
-Vineet
On 3/31/20 10:57 AM, Vineet Gupta wrote:
> Well its a hard requirement considering glibc is still using gcc-9 !
>
> Thx,
> -Vineet
>
Hi Claudiu,
For glibc needs can this be backported to gcc-9 please !
Thx,
-Vineet
On 3/31/20 3:06 AM, Claudiu Zissulescu Ianculescu wrote:
> Pushed.
>
> Thank you,
> Claudiu
>
> On Sun, Mar 29, 2020 at 2:05 AM Vineet Gupta via Gcc-patches
> wrote:
>> Enable big-end
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