On 4/1/25 17:44, Jeff Law wrote:
> On 4/1/25 12:15 PM, Vineet Gupta wrote:
>> On 3/31/25 23:48, Heinrich Schuchardt wrote:
>>> On 3/30/25 01:49, Vineet Gupta wrote:
>>>> changes since v2
>>>>    - dump log sanfu
>>>>
>>>> ---
>>>> vsetvl phase4 uses LCM guided info to insert VSETVL insns.
>>>> It has an additional loop to insert missing vsetvls on certain edges.
>>>> Currently it asserts/aborts on encountering EDGE_ABNORMAL.
>>>> When enabling go frontend with V enabled, libgo build hits the assert.
>>>>
>>>> It seems to be safe to just skip the abnormal edge.
>>> Hello Vineet,
>>>
>>> Is there a test case where only following an abnormal edge between code
>>> blocks would require to call VSETVL?
>>>
>>> In the sketched code below following the exception would require VSETVL
>>> to be called while the edge from the try block to the finally block
>>> would not require this.
>>>
>>> try {
>>>     for (..) {
>>>             uint16_t vectorizable math
>>>             if (condition)
>>>                     throw exception
>>>             uint16_t vectorizable math
>>>     }
>>>     for (..) {
>>>             uint8_t vectorizable math
>>>     }
>>> } catch exception {
>>> } finally
>>>     for (..) {
>>>             uint8_t vectorizable math
>>>     }
>>> }
>> Yeah we are going to run testsuite with -fnon-call-exceptions to find such 
>> cases.
>>
>> But I'd argue, there is no need to optimize vsetvl for such esoteric cases 
>> (vs.
>> code complexity trade-off).
>> After all we'd just endup with an extra VSETVL in the finally block.
> I'd look at that skeleton code as a way to potentially trip this issue 
> without needing golang.

The best I could come up with, but that won't hit the issue

#pragma riscv intrinsic "vector"
typedef long unsigned int size_t;

int foo (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl, int cond, float *out)
{
  vfloat32m1_t result_1, result_2, result_3;
  try {
    result_1 = __riscv_vfadd_vv_f32m1 (op1, op2, vl);

    if (cond & 0x1)
      result_2 = __riscv_vfadd_vv_f32m1 (result_1, op2, vl);

    if (cond % 17)
      result_3 = __riscv_vfadd_vv_f32m1 (result_3, op2, vl);
    else
      result_3 = result_1;

    if (cond)
      throw 42;
  }
  catch (int i) {
  }

  result_2 = __riscv_vfadd_vv_f32m1 (result_3, op2, vl);
  *(vfloat32m1_t *)out = result_2;
 
  return 0;
}

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