The target clause in OpenMP is used to offload loop kernels to accelarator
peripeherals. target's 'map' clause is used to move data from and to the
accelarator. When the data is SVE type, it may not be suitable because of
various reasons i.e. the two SVE targets may not agree on vector size or
so
On 4/14/25 7:44 PM, Kyrylo Tkachov wrote:
Hi Tejas,
On 14 Apr 2025, at 16:04, Tejas Belagod wrote:
The operand order to gen_vcond_mask call in the vec_extract pattern is wrong.
Fix the order where predicate is operand 3.
Tested and bootstrapped on aarch64-linux-gnu. OK for trunk?
gcc
The operand order to gen_vcond_mask call in the vec_extract pattern is wrong.
Fix the order where predicate is operand 3.
Tested and bootstrapped on aarch64-linux-gnu. OK for trunk?
gcc/ChangeLog
* config/aarch64/aarch64-sve.md (vec_extract): Fix operand
order to gen_vcond_mask_*
On 4/15/25 1:56 PM, Richard Sandiford wrote:
Tejas Belagod writes:
The operand order to gen_vcond_mask call in the vec_extract pattern is wrong.
Fix the order where predicate is operand 3.
Tested and bootstrapped on aarch64-linux-gnu. OK for trunk?
gcc/ChangeLog
* config/aarch64
On 5/2/25 1:11 AM, Jakub Jelinek wrote:
On Thu, May 01, 2025 at 08:38:57PM +0100, Richard Sandiford wrote:
Tejas Belagod writes:
Fix udr-sve.c target test that to check for the correct results based on the
OpenMP clauses used. The test was first written with a misunderstood
functionality of
Ping (for trunk and GCC15)?
Thanks,
Tejas.
On 4/11/25 3:55 PM, Tejas Belagod wrote:
Fix udr-sve.c target test that to check for the correct results based on the
OpenMP clauses used. The test was first written with a misunderstood
functionality of the reduction clause.
Tested with aarch64
On 3/8/25 12:55 AM, Tejas Belagod wrote:
On 3/7/25 5:34 PM, Richard Biener wrote:
On Fri, 7 Mar 2025, Tejas Belagod wrote:
On 3/7/25 4:38 PM, Richard Biener wrote:
On Fri, 7 Mar 2025, Tejas Belagod wrote:
Given a vector mode and its corresponding element mode, this new new
language
hook
Update existing compile test with tests to cover C/C++ operations on svbool_t
type objects.
gcc/testsuite/ChangeLog:
* g++.dg/ext/sve-sizeless-1.C: Add new tests.
* g++.dg/ext/sve-sizeless-2.C: Add new tests.
* g++.target/aarch64/sve/acle/general-c++/gnu_vectors_1.C: Add n
Update test error message as svbool_t is not treated as a GNU vector.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/acle/general-c/svcount_1.c: Update message.
---
gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/svcount_1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
Support TARGET_MEM_REFs when walking subtress searching for ADDR_EXPR. This
scenario presents itself when walking MEM_REF subtrees looking for addr-taken
entities during the execute_update_addresses_taken () pass where address-taken
bitmaps are updated.
gcc/ChangeLog:
* gimple-walk.cc (w
Support a subset of C/C++ operations (bitwise, conditional etc.) on svbool_t.
gcc/ChangeLog:
* c-family/c-common.cc (c_build_vec_convert): Support vector boolean
types for __builtin_convertvector ().
(c_common_bool_type): New. Given precision and signedness, return the
Support subscript operation on svbool_t. This considers svbool_t as a packed
bit-vector of 1-bit boolean data.
gcc/ChangeLog:
* c-family/c-common.cc (convert_vector_to_array_for_subscript): Prepare
the first stage of the subscript subtree for a later gimplification
step.
Given a vector mode and its corresponding element mode, this new new language
hook returns a vector type that has properties of the vector mode and element
type of that of the element mode. For eg. on AArch64, given VNx16BI and QImode
it returns VNx16QI i.e. the wider mode to BImode that is an SVE
On 3/7/25 4:38 PM, Richard Biener wrote:
On Fri, 7 Mar 2025, Tejas Belagod wrote:
Given a vector mode and its corresponding element mode, this new new language
hook returns a vector type that has properties of the vector mode and element
type of that of the element mode. For eg. on AArch64
l_t != 0
Address-of: & on svbool_t[i] is not allowed.
sizeof(): sizeof (svbool_t[i]) is precision / 8 + 1
[] operator:
svbool_t[i] indexes bit i from the LSBit of svbool_t. For eg. svbool[4] indexes
the 5th bit from LSBit of svbool_t. The type of svbool_t[i] is boolean.
Tejas Belagod (6):
On 3/7/25 5:34 PM, Richard Biener wrote:
On Fri, 7 Mar 2025, Tejas Belagod wrote:
On 3/7/25 4:38 PM, Richard Biener wrote:
On Fri, 7 Mar 2025, Tejas Belagod wrote:
Given a vector mode and its corresponding element mode, this new new
language
hook returns a vector type that has properties of
On 3/10/25 7:21 PM, Richard Biener wrote:
On Sat, 8 Mar 2025, Tejas Belagod wrote:
On 3/8/25 12:55 AM, Tejas Belagod wrote:
On 3/7/25 5:34 PM, Richard Biener wrote:
On Fri, 7 Mar 2025, Tejas Belagod wrote:
On 3/7/25 4:38 PM, Richard Biener wrote:
On Fri, 7 Mar 2025, Tejas Belagod wrote
On 3/13/25 2:04 PM, Richard Biener wrote:
I think this is done by convert_vector_to_array_for_subscript in
c-common/, note that this handles lvalue conversion as well which
means it will not work in lvalue context where you'd possibly want
sth like a
TARGET_EXPR
but then the caller needs t
On 3/13/25 1:28 PM, Richard Biener wrote:
On Thu, 13 Mar 2025, Tejas Belagod wrote:
On 3/12/25 4:45 PM, Richard Biener wrote:
On Wed, 12 Mar 2025, Tejas Belagod wrote:
On 3/10/25 7:21 PM, Richard Biener wrote:
On Sat, 8 Mar 2025, Tejas Belagod wrote:
On 3/8/25 12:55 AM, Tejas Belagod
On 3/12/25 4:45 PM, Richard Biener wrote:
On Wed, 12 Mar 2025, Tejas Belagod wrote:
On 3/10/25 7:21 PM, Richard Biener wrote:
On Sat, 8 Mar 2025, Tejas Belagod wrote:
On 3/8/25 12:55 AM, Tejas Belagod wrote:
On 3/7/25 5:34 PM, Richard Biener wrote:
On Fri, 7 Mar 2025, Tejas Belagod wrote
patch also includes Richard's patch that the rest of the series is based on
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606741.html
Patches have been rebased, retested and bootstrapped on trunk. OK for trunk?
Richard Sandiford (1):
gomp: Various fixes for SVE types [PR101018]
Tej
Add a function to traverse down the pointer layers to the pointee type.
gcc/ChangeLog:
* tree.h (strip_pointer_types): New.
---
gcc/tree.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/gcc/tree.h b/gcc/tree.h
index 21f3cd5525c..580997b4e5d 100644
--- a/gcc/tree.h
+++ b/gcc/
The target clause in OpenMP is used to offload loop kernels to accelarator
peripeherals. target's 'map' clause is used to move data from and to the
accelarator. When the data is SVE type, it may not be suitable because of
various reasons i.e. the two SVE targets may not agree on vector size or
so
be hard to test.
Co-authored-by: Tejas Belagod
gcc/
PR middle-end/101018
* poly-int.h (can_and_p): New function.
* fold-const.cc (poly_int_binop): Use it to optimize BIT_AND_EXPRs
involving POLY_INT_CSTs.
* gimplify.cc (gimplify_bind_expr): Use poly_int_tree
7;re going to be part of a
separate patch series.
Patches have been rebased, retested and bootstrapped on aarch64-linux-gcc.
OK for trunk?
Richard Sandiford (1):
gomp: Various fixes for SVE types [PR101018]
Tejas Belagod (2):
Add function to strip pointer type and get down to the actu
.
It incorporates review comments from an earlier version of the series
https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674283.html
OK for trunk?
Thanks,
Tejas
Tejas Belagod (2):
AArch64: Add OpenMP target compile error tests
libgomp: Add AArch64 SVE target tests to libgomp
Add compile-only OpenMP error tests for target clause used with SVE types.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/gomp/gomp.exp: Test driver.
* gcc.target/aarch64/sve/gomp/target-device.c: New test.
* gcc.target/aarch64/sve/gomp/target-link.c: Likewise.
From: Tejas Belagod
This PR optimizes an SVE intrinsics sequence where
svlasta (svptrue_pat_b8 (SV_VL1), x)
a scalar is selected based on a constant predicate and a variable vector.
This sequence is optimized to return the correspoding element of a NEON
vector. For eg.
svlasta
From: Richard Sandiford
Date: Friday, May 19, 2023 at 3:20 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
> Am I correct to understand that we still need to check for the case when
> there's a re
From: Richard Sandiford
Date: Monday, June 12, 2023 at 2:15 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org , Tejas Belagod
Subject: Re: [PATCH v2] [PR96339] Optimise svlast[ab]
Tejas Belagod writes:
> From: Tejas Belagod
>
> This PR optimizes an SVE intrinsics seque
From: Kyrylo Tkachov
Date: Wednesday, June 14, 2023 at 10:11 PM
To: Prathamesh Kulkarni , Tejas Belagod
Cc: Richard Sandiford , gcc-patches@gcc.gnu.org
Subject: RE: [PATCH v2] [PR96339] Optimise svlast[ab]
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkach
On 7/3/23 1:31 PM, Richard Biener wrote:
On Mon, Jul 3, 2023 at 8:50 AM Tejas Belagod wrote:
On 6/29/23 6:55 PM, Richard Biener wrote:
On Wed, Jun 28, 2023 at 1:26 PM Tejas Belagod wrote:
From: Richard Biener
Date: Tuesday, June 27, 2023 at 12:58 PM
To: Tejas Belagod
Cc: gcc-patches
On 7/13/23 4:05 PM, Richard Biener wrote:
On Thu, Jul 13, 2023 at 12:15 PM Tejas Belagod wrote:
On 7/3/23 1:31 PM, Richard Biener wrote:
On Mon, Jul 3, 2023 at 8:50 AM Tejas Belagod wrote:
On 6/29/23 6:55 PM, Richard Biener wrote:
On Wed, Jun 28, 2023 at 1:26 PM Tejas Belagod wrote
On 7/17/23 5:46 PM, Richard Biener wrote:
On Fri, Jul 14, 2023 at 12:18 PM Tejas Belagod wrote:
On 7/13/23 4:05 PM, Richard Biener wrote:
On Thu, Jul 13, 2023 at 12:15 PM Tejas Belagod wrote:
On 7/3/23 1:31 PM, Richard Biener wrote:
On Mon, Jul 3, 2023 at 8:50 AM Tejas Belagod wrote
Hi,
Packed Boolean Vectors
--
I'd like to propose a feature addition to GNU Vector extensions to add packed
boolean vectors (PBV). This has been discussed in the past here[1] and a
variant has
been implemented in Clang recently[2].
With predication features being added to v
From: Richard Biener
Date: Monday, June 26, 2023 at 2:23 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors
On Mon, Jun 26, 2023 at 8:24 AM Tejas Belagod via Gcc-patches
wrote:
>
> Hi,
>
> Packed Boo
From: Richard Biener
Date: Tuesday, June 27, 2023 at 12:58 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors
On Tue, Jun 27, 2023 at 8:30 AM Tejas Belagod wrote:
>
>
>
>
>
> From: Richard Biener
> Date:
On 6/29/23 6:55 PM, Richard Biener wrote:
On Wed, Jun 28, 2023 at 1:26 PM Tejas Belagod wrote:
From: Richard Biener
Date: Tuesday, June 27, 2023 at 12:58 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [RFC] GNU Vector Extension -- Packed Boolean Vectors
On Tue, Jun 27
Transitive closures of architectural extensions have to be manually maintained
for AARCH64_OPT_EXTENSION list. Currently aes, sha2 and sha3 extensions add
AARCH64_FL_SIMD has their dependency - this does not automatically pull in the
transitive dependence of AARCH64_FL_FP from AARCH64_FL_SIMD's de
'+aes' and '+sha2' as opposed to the ambiguous catch-all '+crypto'.
[1] Section D17.2.61, C7.2.215
2022-01-11 Tejas Belagod
gcc/ChangeLog:
* config/aarch64/arm_neon.h (vmull_p64, vmull_high_p64, vaeseq_u8,
vaesdq_u8, vaesmcq_u8, vaesimc
Thanks for your comments, Richard.
From: Richard Sandiford
Date: Friday, May 12, 2023 at 1:02 AM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org , Tejas Belagod
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
> From: Tejas Belagod
>
> This PR opt
From: Richard Sandiford
Date: Tuesday, May 16, 2023 at 2:15 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
>> + {
>> +int i;
>> +int nelts = vector_cst_encoded_nelts (v);
>&g
From: Richard Sandiford
Date: Tuesday, May 16, 2023 at 5:36 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
>>> + {
>>> + b = build3 (BIT_FIELD_REF, TREE
: Likewise.
Thanks,
Tejas Belagod.
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index
c5638d096fa84a27b4ea397f62cd0d05a28e7c8c..48eddf64e05afe3788abfa05141f6544a9323ea1
100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
anch-protection'. The function attribute options override the command-
line options for the function scope.
Regression tested for arm-none-eabi. OK for trunk?
2021-11-11 Tejas Belagod
gcc/ChangeLog:
* config/arm/arm.c (arm_valid_target_attribute_rec): Add ARM function
Ping for this series.
Thanks,
Tejas.
> -Original Message-
> From: Gcc-patches bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
> Gcc-patches
> Sent: Thursday, October 28, 2021 12:41 PM
> To: Richard Earnshaw ; gcc-
> patc...@gcc.gnu.org
>
Hi,
This patch adds the -march feature +pacbti to Armv8.1-M Mainline.
This feature enables pointer signing and authentication instructions
on M-class architectures.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/Changelog:
* config/arm/arm-cpus.in: Define new
Hi,
Add -mbranch-protection option and its associated parsing routines.
This option enables the code-generation of pointer signing and
authentication instructions in function prologues and epilogues.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/ChangeLog
Hi,
Add targeting-checking entities for PACBTI in testsuite
framework.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* testsuite/lib/target-supports.exp
(check_effective_target_arm_pacbti_hw): New.
diff --git a/gcc/testsuite/lib/target
Hi,
This patch implements target feature macros when PACBTI is
enabled through the -march option or -mbranch-protection.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_BTI_DEFAULT
AUTG. Just generating PAC/AUT instructions
using -mbranch-protection will not enable authentication on the unwinder.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass): Introduce
new pseudo register
Hi,
This patch emits assembler directives for PACBTI build attributes
as defined by the ABI.
(https://github.com/ARM-software/abi-aa/releases/download/2021Q1/addenda32.pdf)
Tested on arm-none-eabi.
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* config/arm/arm.c (arm_file_start): Emit
Hi,
This patch adds a multilib for pacbti target feature.
Tested on arm-none-eabi. OK for trunk?
2021-10-04 Tejas Belagod
gcc/ChangeLog:
* config/arm/t-rmprofile: Add multilib rules for +pacbti.
diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile
index
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, October 11, 2021 1:58 PM
> To: Tejas Belagod ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.
>
> On 08/10/2021 13:17, Tejas Belagod via Gcc-patches wrote
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, October 11, 2021 1:29 PM
> To: Tejas Belagod ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch 1/7, Arm, GCC] Add Armv8.1-M Mainline target feature
> +pacbti.
>
> On 08/10/2021 13:17, Tejas Belag
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, October 11, 2021 1:58 PM
> To: Tejas Belagod ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch 2/7, Arm, GCC] Add option -mbranch-protection.
>
> On 08/10/2021 13:17, Tejas Belagod via Gcc-patches wrote
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, October 11, 2021 2:38 PM
> To: Tejas Belagod ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch 3/7, Arm, GCC] Add testsuite library support for PACBTI
> target.
>
> On 11/10/2021 14:36, Richard Earnsh
> -Original Message-
> From: Richard Earnshaw
> Sent: Monday, October 11, 2021 2:58 PM
> To: Tejas Belagod ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch 4/7, Arm. GCC] Implement target feature macros for
> PACBTI.
>
> On 08/10/2021 13:18, Tejas Belagod via G
> -Original Message-
> From: Gcc-patches bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
> Gcc-patches
> Sent: Friday, October 8, 2021 1:18 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch 5/7, Arm. GCC] Add pointer authentication for stack
> -Original Message-
> From: Gcc-patches bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
> Gcc-patches
> Sent: Friday, October 8, 2021 1:19 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch 6/7, Arm, GCC] Emit build attributes for PA
> -Original Message-
> From: Gcc-patches bounces+belagod=gcc.gnu@gcc.gnu.org> On Behalf Of Tejas Belagod via
> Gcc-patches
> Sent: Friday, October 8, 2021 1:19 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch 7/7, Arm, GCC] Introduce multilibs for PACBTI ta
'+aes' and '+sha2' as opposed to the ambiguous catch-all '+crypto'.
[1] Section D17.2.61, C7.2.215
2022-01-11 Tejas Belagod
gcc/
* config/aarch64/arm_neon.h: Gate AES and PMULL64 intrinsics
under target feature +aes as opposed to +crypto. Gate SH
From: Kyrylo Tkachov
Date: Tuesday, January 17, 2023 at 3:53 PM
To: Tejas Belagod , gcc-patches@gcc.gnu.org
Cc: Richard Sandiford , Richard Earnshaw
Subject: RE: [PATCH] AArch64: Gate various crypto intrinsics availability based
on features
Hi Tejas,
> -Original Message-
>
[Ping]
From: Tejas Belagod
Date: Thursday, March 16, 2023 at 5:09 PM
To: gcc-patches@gcc.gnu.org
Cc: Tejas Belagod , Richard Sandiford
Subject: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
From: Tejas Belagod
This PR optimizes an SVE intrinsics sequence where
svlasta (svptrue_pat_b8
From: Tejas Belagod
This PR optimizes an SVE intrinsics sequence where
svlasta (svptrue_pat_b8 (SV_VL1), x)
a scalar is selected based on a constant predicate and a variable vector.
This sequence is optimized to return the correspoding element of a NEON
vector. For eg.
svlasta
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