Re:[committed] [PATCH] AArch64: Fix operands order in vec_extract expander

[Tejas Belagod]

On 4/15/25 1:56 PM, Richard Sandiford wrote:

Tejas Belagod <tejas.bela...@arm.com> writes:

The operand order to gen_vcond_mask call in the vec_extract pattern is wrong.
Fix the order where predicate is operand 3.

Tested and bootstrapped on aarch64-linux-gnu. OK for trunk?

gcc/ChangeLog

        * config/aarch64/aarch64-sve.md (vec_extract<vpred><Vel>): Fix operand
        order to gen_vcond_mask_*.

Thanks, LGTM too.

Thanks, now applied to trunk as 31e16c8b75b.

Tejas.

Richard

---
  gcc/config/aarch64/aarch64-sve.md | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-sve.md 
b/gcc/config/aarch64/aarch64-sve.md
index 3dbd65986ec..d4af3706294 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -3133,9 +3133,9 @@
    "TARGET_SVE"
    {
      rtx tmp = gen_reg_rtx (<MODE>mode);
-    emit_insn (gen_vcond_mask_<mode><vpred> (tmp, operands[1],
-                                            CONST1_RTX (<MODE>mode),
-                                            CONST0_RTX (<MODE>mode)));
+    emit_insn (gen_vcond_mask_<mode><vpred> (tmp, CONST1_RTX (<MODE>mode),
+                                            CONST0_RTX (<MODE>mode),
+                                            operands[1]));
      emit_insn (gen_vec_extract<mode><Vel> (operands[0], tmp, operands[2]));
      DONE;
    }