On 01/05/13 16:09, James Greenhalgh wrote:
Hi,
The fcvt instructions also have forms which leave their integer
result as a scalar in the SIMD register set.
This patch adds those alternatives for the lceil family
of standard patterns.
Regression tested on aarch64-none-elf with no regressions.
On 01/05/13 18:45, Ian Bolton wrote:
From: Marcus Shawcroft [mailto:marcus.shawcr...@gmail.com]
+ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-
9\]+" } } */
+ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+,
x\[0-9\]+, lsl 3" } } */
Ian, The
On 1 May 2013, at 19:41, "Ian Bolton" wrote:
> This is a fix for this patch:
> http://gcc.gnu.org/ml/gcc-patches/2013-04/msg01621.html
>
> If someone compiles with -mgeneral-regs-only then those instructions
> shouldn't be used. We can enforce that by adding the fp attribute to
> the relevant a
On 1 May 2013, at 21:12, "Ian Bolton" wrote:
>> Can we have the patch attached ?
>
> OK
>
OK
/Marcus
OK
/Marcus
On 2 May 2013 15:56, Ian Bolton wrote:
> I previously fixed a bug with the patterns that generate TST.
>
> I added these testcases to make our regression testing more solid.
>
> They've been running on our internal branch for about a month.
>
> OK to commit to trunk?
>
> Cheers,
> Ian
OK and committed. Thankyou.
/Marcus
On 2 May 2013 19:04, Vidya Praveen wrote:
> Hello,
>
> This attached patch adds support to the scalar form of FABD
> instruction along with the compile & execute tests for the same.
>
> Regression tested on aarch64-none-elf with no issues.
>
> OK?
>
> Regards
OK and committed. Thankyou.
/Marcus
On 2 May 2013 19:21, Vidya Praveen wrote:
> Hello,
>
> This attached patch corrects the description for simd_fabd.
>
> OK?
>
> Regards
> VP
>
>
> gcc/ChangeLog
>
> 2013-05-02 Vidya Praveen
>
> * config/aarch64/aarch64-simd.md (simd_fabd): Correct t
OK
On 7 May 2013 11:35, Hurugalawadi, Naveen
wrote:
> Hi,
>
> Please find attached the patch that restricts the shift value in
> comparison operation between 0-4.
>
> Please review the patch and let me know if its okay?
>
> 2013-05-07 Naveen H.S
>
> * config/aarch64/aarch64.md
>
OK
/Marcus
On 7 May 2013 09:44, Sofiane Naci wrote:
> Hi,
>
> The attached patch is part of the ongoing work to enhance instruction
> scheduling opportunities in AArch64.
>
> This patch splits 2 alternatives of the aarch64_simd_mov pattern, which used
> to issue 2 consecutive instructions.
> Test
On 1 May 2013 10:50, Ian Bolton wrote:
> Thanks for the review. I've fixed this up in the attached patch, by
> counting the number of matches for the first rule and expecting it to
> match additional times to cover the overlap with the lsl based rule.
>
> I've also renamed the testcases in line w
On 30/04/13 16:27, Sofiane Naci wrote:
Hi,
The attached patch is part of the ongoing work to enhance instruction
scheduling opportunities in AArch64.
This patch splits a few alternatives of the movtf_aarch64 pattern, which
used to issue 2 consecutive instructions.
Tested successfully with a ful
On 9 May 2013 07:48, Venkataramanan Kumar
wrote:
> Hi Maintainers,
>
> The attach patch contains the following for aarch64 backend to enable
> gprof support.
>
> 1. Changes to "aarch64_return_addr" to get return address from a stack frame.
> 2. Defines macros associated with generating code for pr
OK
/Marcus
On 13 May 2013 11:38, Sofiane Naci wrote:
> Hi,
>
> This patch refactors the simd_mov split and fixes a few coding style issues.
> Tested successfully on a full aarch64-elf regression run.
>
> OK for trunk?
>
> Thanks
> Sofiane
On 14/05/13 12:11, Sofiane Naci wrote:
Hi,
This patch defines the "simd" attribute for the *movdi_aarch64 pattern.
Tested successfully with a full regression run on aarch64-elf.
OK for trunk?
Thanks
Sofiane
OK
/Marcus
OK
/M
On 14 May 2013 14:43, James Greenhalgh wrote:
>
> Hi,
>
> For a statement like:
>
> INT = FLOAT > FLOAT ? INT : INT.
>
> The vcond implementation in AArch64 is broken. We will try to force
> the INT value to a FLOAT register and will ICE.
>
> This patch fixes this.
>
> Regression suite ru
On 12/05/13 17:47, Venkataramanan Kumar wrote:
+# We support profiling for AArch64 linux target.
+if { [istarget aarch64*-linux-*]
+ && ($test_what == "-p" || $test_what == "-pg") } {
+ return 1
}
Can't this clause be removed completely now ?
We are not supporting profiling in "
On 22 May 2013 12:47, Vidya Praveen wrote:
> Hello,
>
> This patch adds support to AdvSIMD CLZ instruction and adds tests for the
> same.
> Regression test done for aarch64-none-elf with no issues.
>
> OK?
>
> Regards
> VP
>
> ---
>
> gcc/ChangeLog
>
> 2013-05-22 Vidya Praveen
>
> * conf
On 22 May 2013 16:18, Ian Bolton wrote:
> The test file scalar_intrinsics.c (in gcc.target/aarch64)
> is currently compile-only.
>
> If you attempt to make it run, as opposed to just generate
> assembler, you can't because it won't assemble.
>
> There are two issues causing trouble here:
>
> 1) Us
On 17 May 2013 19:20, Ian Bolton wrote:
> The MOVK instruction is currently not used when operand 2 is
> more than 16 bits, which leads to sub-optimal code.
>
> This patch improves those situations by removing the check and
> instead masking down to 16 bits within the new "X" format specifier
> I
On 22 May 2013 12:47, Vidya Praveen wrote:
> Hello,
>
> This patch adds support to AdvSIMD CLZ instruction and adds tests for the
> same.
> Regression test done for aarch64-none-elf with no issues.
>
> OK?
>
> Regards
> VP
>
> ---
>
> gcc/ChangeLog
>
> 2013-05-22 Vidya Praveen
>
> * conf
This patch refactors the current implementation of the
aarch64_mov_operand predicate in preparation for the addition of further
memory models. Regressed for aarch64-none-elf. Applied.
/Marcus
2013-05-23 Chris Schlumberger-Socha
Marcus Shawcroft
* config/aarch64
Hi, This patch switches the only use of the "Usa" constraint to use "S"
instead and removes the definition and documentation for "Usa".
Regressed for aarch64-none-elf. Applied.
/Marcus
2013-05-23 Chris Schlumberger-Socha
Marcus Shawcroft
This patch re-organizes the implementation of aarch64_classify_symbol in
preparation for add tiny absolute memory model support.
Regressed aarch64-none-elf, applied.
/Marcus
2013-05-29 Chris Schlumberger-Socha
Marcus Shawcroft
* config/aarch64/aarch64.c
Hi, This patch adds support for the tiny absolute memory model.
Regressed for aarch64-none-elf with each of
-mcmodel=tiny
-mcmodel=small
-mcmodel=small -fPIC
Applied.
/Marcus
2012-05-29 Chris Schlumberger-Socha
Marcus Shawcroft
* config/aarch64/aarch64-protos.h
On 29/05/13 14:08, Marcus Shawcroft wrote:
Hi, This patch adds support for the tiny absolute memory model.
Regressed for aarch64-none-elf with each of
-mcmodel=tiny
-mcmodel=small
-mcmodel=small -fPIC
Applied.
This time with patch attached, oops, sorry.
/Marcus
/Marcus
2012-05
On 29/05/13 13:55, Marcus Shawcroft wrote:
This patch re-organizes the implementation of aarch64_classify_symbol in
preparation for add tiny absolute memory model support.
Regressed aarch64-none-elf, applied.
/Marcus
2013-05-29 Chris Schlumberger-Socha
Marcus Shawcroft
-31 Marcus Shawcroft
* gcc.target/arm/pr56184.C: Add -fno-short-enums.diff --git a/gcc/testsuite/gcc.target/arm/pr56184.C b/gcc/testsuite/gcc.target/arm/pr56184.C
index db92db1..d44c1b4 100644
--- a/gcc/testsuite/gcc.target/arm/pr56184.C
+++ b/gcc/testsuite/gcc.target/arm/pr56184.C
@@ -1,5
Marcus Shawcroft
* g++.old-deja/g++.robertl/eb76.C: Add -fno-short-enums.diff --git a/gcc/testsuite/g++.old-deja/g++.robertl/eb76.C b/gcc/testsuite/g++.old-deja/g++.robertl/eb76.C
index c74e7bd..3125dc1 100644
--- a/gcc/testsuite/g++.old-deja/g++.robertl/eb76.C
+++ b/gcc/testsuite/g++.old
-31 Marcus Shawcroft
* g++.dg/torture/pr54684.C: Add -fno-short-enums.diff --git a/gcc/testsuite/g++.dg/torture/pr54684.C b/gcc/testsuite/g++.dg/torture/pr54684.C
index 40c47f3..4934011 100644
--- a/gcc/testsuite/g++.dg/torture/pr54684.C
+++ b/gcc/testsuite/g++.dg/torture/pr54684.C
@@ -1,4
The vect/no-section-anchors-vect-68.C test case results in a binary that
is tool large for the aarch64 tiny memory model. This patch disables
the test case for that memory model.
/Marcus
2013-05-31 Marcus Shawcroft
* gcc.dg/vect/no-section-anchors-vect-68.c:
Add dg-skip
This change allows -mcmodel=tiny -fPIC to use tiny addressing instead of
small for none GOT accesses.
Regressed for aarch64-none-elf with -mcmodel=tiny and -mcmodel=tiny -fPIC
Applied.
/Marcus
2013-05-31 Marcus Shawcroft
* config/aarch64/aarch64.c (aarch64_classify_symbol
Remove un-necessary braces. Applied.
/Marcus
2013-05-31 Marcus Shawcroft
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
Remove un-necessary braces.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 9c77888..f554550 100644
--- a
On 03/06/13 16:17, James Greenhalgh wrote:
---
gcc/
2013-04-22 James Greenhalgh
* config/aarch64/aarch64.c (aarch64_print_operand): Fix
asm_fprintf
format specifier in 'X' case.
OK.
R.
Hi,
This warning also occurs on gcc-4_8-branch, can I also backport the fix
to the
On 3 June 2013 17:31, Ian Bolton wrote:
> 13-06-03 Ian Bolton
>
> * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Change
> return type to bool for prototype.
> (aarch64_legitimate_constant_p): Check for true instead of not -1.
> (aarch64_simd_valid_im
On 3 June 2013 17:31, Ian Bolton wrote:
> 13-06-03 Ian Bolton
>
> * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): No
> longer static.
> (aarch64_simd_immediate_valid_for_move): Remove.
> (aarch64_simd_scalar_immediate_valid_for_move): Update call.
>
On 3 June 2013 17:32, Ian Bolton wrote:
> 2013-06-03 Ian Bolton
>
> * config/aarch64/aarch64.c (simd_immediate_info): Struct to hold
> information completed by aarch64_simd_valid_immediate.
> (aarch64_legitimate_constant_p): Update arguments.
> (aarch64_simd_val
On 3 June 2013 17:34, Ian Bolton wrote:
> 2013-06-03 Ian Bolton
>
> * config/aarch64/aarch64.c (simd_immediate_info): Remove
> element_char member.
> (sizetochar): Return signed char.
> (aarch64_simd_valid_immediate): Remove elchar and other
> unnecessar
On 3 June 2013 17:35, Ian Bolton wrote:
> 2013-06-03 Ian Bolton
>
> gcc/
> * config/aarch64/aarch64.md (*mov_aarch64): Call
> into function to generate MOVI instruction.
> * config/aarch64/aarch64.c (aarch64_simd_container_mode):
> New function.
> (aarc
On 1 June 2013 14:06, Jan Hubicka wrote:
> Hi,
> this patch cleanups way we handle aliases. The main point is to merge code
> that was previously done separately for variables and functions.
>
Hello, This patch appears to break both arm and aarch64. I don't
fully understand the mechanism. The
On 7 June 2013 20:58, Jan Hubicka wrote:
> Hi,
> I have comitted the following. Does it solve your problem?
>
> Honza
>
> Index: ChangeLog
> ===
> --- ChangeLog (revision 199834)
> +++ ChangeLog (working copy)
> @@ -1,3 +1,7 @@
d to stick to posix shell.
OK?
/Marcus
2013-06-11 Marcus Shawcroft
* dg-extract-results.sh (a_init, a_length, a_append, a_lookup): New.
* dg-extract-results.sh: Use array for VARIANTS.
Strip whitespace from temporary filenames. GAWK fragments to tolerate
On 11/06/13 13:55, Jakub Jelinek wrote:
On Tue, Jun 11, 2013 at 01:12:50PM +0100, Marcus Shawcroft wrote:
Hi,
The dg-extract-result.sh script is not tolerant of spaces in test variants.
Consider the following site.exp fragment:
set target_list [
list "arm-eabi-aem{-marm -march=
On 11/06/13 14:12, Jakub Jelinek wrote:
On Tue, Jun 11, 2013 at 02:07:50PM +0100, Marcus Shawcroft wrote:
On 11/06/13 13:55, Jakub Jelinek wrote:
On Tue, Jun 11, 2013 at 01:12:50PM +0100, Marcus Shawcroft wrote:
Hi,
The dg-extract-result.sh script is not tolerant of spaces in test variants
On 11/06/13 14:44, Sofiane Naci wrote:
Hi,
This patch split the simd aarch64_combine pattern.
This passes the full regression test suite in aarch64-elf.
OK for trunk?
-
Thanks
Sofiane
OK
/Marcus
OK
/Marcus
On 11 June 2013 14:43, Sofiane Naci wrote:
> Hi,
>
> This patch fixes a bug in the move_lo_quad_ pattern.
>
> The pattern, shown below, issues a scalar MOV instruction for vector modes:
>
> (define_insn "move_lo_quad_"
> [(set (match_operand:VQ 0 "register_operand" "=w,w,w")
>
On 14/06/13 14:55, Vidya Praveen wrote:
Hello,
This patch adds support to SMLAL/SMLSL/UMLAL/UMLSL instructions and adds tests
for the same. Regression test run for aarch64-none-elf with no regressions.
OK?
~VP
---
gcc/ChangeLog
2013-06-14 Vidya Praveen
* config/aarch64/aarch64-si
On 5 September 2014 09:04, Ramana Radhakrishnan
wrote:
>> On 09/04/2014 07:04 AM, Ramana Radhakrishnan wrote:
>>>
>>> gcc/Changelog
>>>
>>> 2014-09-04 Marcus Shawcroft
>>> Ramana Radhakrishnan
>>>
>>&g
On 5 September 2014 10:07, Kyrill Tkachov wrote:
> Ok for trunk?
>
> 2014-09-05 Kyrylo Tkachov
>
> PR target/61749
> * config/aarch64/aarch64-builtins.c (aarch64_types_quadop_qualifiers):
> Use qualifier_immediate for last operand. Rename to...
> (aarch64_types_ternop_lane_qua
+static unsigned HOST_WIDE_INT
+aarch64_asan_shadow_offset (void)
+{
+ return (HOST_WIDE_INT_1 << 36);
+}
+
Looking around various other ports I see magic numbers including 29,
41, 44 Help me understand why 36 is the right choice for aarch64?
Cheers
/Marcus
On 5 September 2014 15:49, Chris
On 8 September 2014 11:38, Alan Lawrence wrote:
> The existing vld1/vst1_1.c test in gcc.target/aarch64 covers only vld1_s8
> and vld1q_s16. This extends it to cover all int/float variants via
> token-pasting.
>
> Passing on aarch64-none-elf and aarch64_be-none-elf.
>
> gcc/testsuite/ChangeLog:
>
On 8 September 2014 11:35, Alan Lawrence wrote:
> This adds a test of all the variants of vld2, vld2q, vld3, vld3q, vld4, and
> vld4q. These all use typexNxM structs and the OI/CI/XImode mechanism, so the
> test cross-checks this against plain ol' vst1(q?).
>
> Cross-tested on aarch64-none-elf (pa
+
+main (int argc, char **argv)
+{
+
int main ?
Otherwise OK /Marcus
On 8 September 2014 11:43, Alan Lawrence wrote:
> This adds a test of the vld2_dup, vld2q_dup, vld3_dup, vld3q_dup, vld4_dup
> and vld4q_dup instrinsics.
>
> Passing on aarch64-none-elf and aarch64_be-none-elf.
>
> gcc/testsu
On 8 September 2014 11:49, Alan Lawrence wrote:
> At present there is no test coverage of the vld2_lane, vld2q_lane,
> vld3_lane, vld3q_lane, vld4_lane, vld4q_lane intrinsics. So this adds a test
> using the vld1 and vst1 intrinsics.
>
> Passing on aarch64-none-elf.
>
> Failing on aarch64_be-none-
On 8 September 2014 12:03, Alan Lawrence wrote:
> This adds a test of all the variants of vst2, vst2q, vst3, vst3q, vst4, and
> vst4q. These all use typexNxM structs and the OI/CI/XImode mechanism, so the
> test cross-checks this against plain ol' vld1(q?).
>
> Cross-tested on aarch64-none-elf (pa
On 9 September 2014 11:20, Alan Lawrence wrote:
> The 'scan-assembler-not not' test in
> gcc.target/aarch64/simd/int_comparisons_1.c fails on aarch64-linux-gnu
> because the compiler adds a ".note" at the end of the .s file. This patch
> tightens the regex to only match a not with surrounding whit
On 8 September 2014 17:45, Alan Lawrence wrote:
> Now that float64x1 is a vector type, we can convert between it and other
> same-sized vector types with a simple cast, as is already done for all other
> reinterprets not involving float64x1.
>
> This allows to remove the reinterpretv1df and reinte
On 8 September 2014 17:31, Alan Lawrence wrote:
> This adds a test thath checks the result of a vset_lane intrinsic is
> identical to the input apart from one value being changed.
>
> Test checks only one index per vset_lane_xxx in a somewhat adhoc fashion as
> the index has to be a compile-time i
On 8 September 2014 17:39, Alan Lawrence wrote:
> gcc/ChangeLog:
>
> * config/aarch64/arm_neon.h (aarch64_vset_lane_any): New (*2).
> (vset_lane_f32, vset_lane_f64, vset_lane_p8, vset_lane_p16,
> vset_lane_s8, vset_lane_s16, vset_lane_s32, vset_lane_s64,
> vset_lan
On 11 September 2014 13:15, James Greenhalgh wrote:
>
> Hi,
>
> I'd been putting this patch off in the hope that I might find
> time to move these intrinsics to a C/builtin implementation, but it
> is probably better to get them right for now and come back to improving
> them later.
>
> All four o
On 9 September 2014 13:08, Christophe Lyon wrote:
> On 9 September 2014 12:03, wrote:
>>
>>
>>> On Sep 9, 2014, at 2:50 AM, Marcus Shawcroft
>>> wrote:
>>>
>>> +static unsigned HOST_WIDE_INT
>>> +aarch64_asan_shad
On 17 September 2014 15:43, James Greenhalgh wrote:
>
> On Wed, Sep 17, 2014 at 09:30:31AM +0100, Richard Earnshaw wrote:
>> "=&r" is correct for an early-clobbered scratch.
>>
>> R.
>
> In that case...
>
> How is the attached patch for trunk? I've bootstrapped it on AArch64
> with -fstack-protect
On 18 September 2014 11:15, James Greenhalgh wrote:
> gcc/
>
> 2014-09-18 James Greenhalgh
>
> * config/aarch64/aarch64.md (stack_protect_test_): Mark
> scratch register as an output to placate register renaming.
>
> gcc/testsuite/
>
> 2014-09-18 James Greenhalgh
>
>
On 15 September 2014 15:48, Wilco Dijkstra wrote:
> Hi,
>
> This patch improves the register move costs for 128-bit types.
>
> OK for commit?
>
> ChangeLog:
> 2014-09-15 Wilco Dijkstra
>
> * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost):
> Add register move costs for
On 19 September 2014 18:28, Wilco Dijkstra wrote:
> This patch makes -fsched-pressure the default on AArch64, like on ARM. This
> improves performance and
> reduces codesize due to fewer unnecessary spills.
>
> OK for commit?
>
> ChangeLog:
> 2014-09-19 Wilco Dijkstra
>
> * gcc/common/
On 22 September 2014 12:16, Alan Lawrence wrote:
> Ok thanks Jeff. In that case I think I should draw this to the attention of
> the AArch64 maintainers to check the testsuite updates are OK before I
> commit...?
OK with me.
Cheers
/Marcus
On 4 September 2014 15:14, Jiong Wang wrote:
> this patch enabled stack shrink-wrap support on AArch64.
>
> no regression on aarch64-none-elf bare-metal.
> aarch64 bootstrap OK.
>
> ok to install?
>
> 2014-09-04 Renlin Li
>
> gcc/
> * config/aarch64/aarch64.md (return): New expand.
> (simple_r
On 18 September 2014 12:45, Alan Lawrence wrote:
> The gimple folding ties the AArch64 backend to the tree representation of
> the midend via the neon intrinsics. This code enables constant folding of
> Neon intrinsics reduction ops, so improves performance, but is not necessary
> for correctness.
On 18 September 2014 12:59, Alan Lawrence wrote:
> This migrates AArch64 over to the new optab for 'plus' reductions, i.e. so
> the define_expands produce scalars by generating a MOV to a GPR.
> Effectively, this moves the vget_lane inside every arm_neon.h intrinsic,
> into the inside of the defin
On 18 September 2014 13:02, Alan Lawrence wrote:
> Similarly to the previous patch (r/2205), this migrates AArch64 to the new
> reduce-to-scalar optabs for min and max. For consistency we apply the same
> treatment to the smax_nan and smin_nan patterns (used for __builtins), even
> though reduc_sm
On 18 September 2014 13:05, Alan Lawrence wrote:
> This gives us back the constant-folding of the neon-intrinsics that was
> removed in the first patch, but is now OK for bigendian too.
>
> bootstrapped on aarch64-none-linux-gnu.
> check-gcc on aarch64-none-elf and aarch64_be-none-elf.
>
> gcc/Cha
On 8 September 2014 11:29, Kyrill Tkachov wrote:
> Hi all,
>
> The included testcase currently ICEs at -O0 because vget_lane_f64 is a
> function, so if it's properly called with a constant argument but without
> constant propagation it will not be recognised as constant, causing an ICE.
> This pat
On 25 September 2014 16:18, Richard Henderson wrote:
> On 09/25/2014 08:05 AM, James Greenhalgh wrote:
>>
>> On Fri, Sep 19, 2014 at 05:57:06PM +0100, Richard Henderson wrote:
>>> On 09/11/2014 01:29 AM, James Greenhalgh wrote:
+;; Predicates used by the various SIMD shift operations. These
On 22 September 2014 19:41, Carrot Wei wrote:
> Hi
>
> The extended register width in add/adds/sub/subs/cmp instructions is
> not always the same as target register, it depends on both target
> register width and extension type. But in current implementation the
> extended register width is always
On 24 September 2014 16:06, James Greenhalgh wrote:
>
> Hi,
>
> As per the subject line this patch adds support for two arm_neon.h
> intrinsics that we had missed.
>
> We also need to fix the signature of vqdmulls_lane_s32, which is an
> obvious extension to this patch while we are in the area.
>
On 30 September 2014 15:27, Christophe Lyon wrote:
> On 10 July 2014 12:12, Marcus Shawcroft wrote:
>> On 1 July 2014 11:05, Christophe Lyon wrote:
>>> * documentation (README)
>>> * dejanu driver (neon-intrinsics.exp)
>>> * support macros (arm-neon-ref.h, c
On 17/06/13 16:03, Sofiane Naci wrote:
Hi,
This patch adds a r<-w alternative to the aarch64_dup_lane pattern and
updates the testcase gcc.target/aarch64/scalar_intrinsics.c accordingly.
The patch has been successfully tested on a full regression run in
aarch64-none-elf.
OK for trunk?
-
T
OK
/Marcus
On 17 June 2013 14:43, Yufeng Zhang wrote:
> Hi,
>
> This patch sets STACK_ARGUMENTS_SIZE with 0 for AArch64 as variadic
> arguments to 'bar' are passed in registers on this target.
>
> OK for the trunk?
>
> Thanks,
> Yufeng
>
> gcc/testsuite/
>
> * gcc.dg/torture/stackalign/bu
Hi, I've been looking at an issue in mysql compilation which appears
to be due to this patch.
On 10 May 2013 18:27, Martin Jambor wrote:
> Hi,
>
> as we discover targets of previously indirect calls in ipa-inline and
> ipa-cp, we sometimes figure out that the targets are not a function.
> One ty
On 25/06/13 17:04, Yufeng Zhang wrote:
This patch carries out minor refactoring on aarch64_add_offset; it
replaces 'DImode' and 'Pmode' with 'mode'.
OK for the trunk?
OK
/Marcus
On 25/06/13 17:06, Yufeng Zhang wrote:
This patch adds a new parameter 'mode' of type 'enum machine_mode mode'
to aarch64_force_temporary, and updates the calls to it.
OK for the trunk?
OK
/Marcus
This test case is too large to fit in the aarch64 tiny memory model...
OK?
/Marcus
2013-06-28 Marcus Shawcroft
* testsuite/libgomp.fortran/strassen.f90:
Add dg-skip-if aarch64_tiny.diff --git a/libgomp/testsuite/libgomp.fortran/strassen.f90 b/libgomp/testsuite
This patch replaces the use of aarch64_symbolic_constant_p with the
(very similar) aarch64_classify_symbolic_expression.
Tested on aarch64-none-elf. Committed.
/Marcus
2013-06-28 Marcus Shawcroft
* config/aarch64/aarch64-protos.h
(aarch64_classify_symbol_expression
Updating a comment w.r.t address models.
/Marcus
2013-06-28 Marcus Shawcroft
* config/aarch64/aarch64-protos.h (aarch64_symbol_type):
Update comment w.r.t SYMBOL_TINY_ABSOLUTE.diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index c9d64c6
Fixing the layout in aarch64_cannot_force_const_mem()...
/Marcus
2013-06-28 Marcus Shawcroft
* config/aarch64/aarch64.c (aarch64_cannot_force_const_mem):
Adjust layout.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index a394283..fc7fe5a 100644
--- a/gcc
On 27 June 2013 17:09, Ian Bolton wrote:
> 2013-06-27 Ian Bolton
>
> gcc/
> * config/aarch64/aarch64.md (*extr_insv_reg): New pattern.
>
> testsuite/
> * gcc.target/aarch64/bfxil_1.c: New test.
> * gcc.target/aarch64/bfxil_2.c: Likewise.
>
OK
/Marcus
On 24 June 2013 16:57, Ian Bolton wrote:
> 2013-06-24 Ian Bolton
>
> * gcc.target/config/aarch64/insv_1.c: Update to show it doesn't work
> on big endian.
> * gcc.target/config/aarch64/insv_2.c: New test for big endian.
> * lib/target-supports.exp: Define aarch6
On 25 June 2013 17:48, Tejas Belagod wrote:
> 2013-06-25 Tejas Belagod
>
> gcc/
> * config/aarch64/aarch64-protos.h (cpu_vector_cost): New.
> (tune_params): New member 'const vec_costs'.
> * config/aarch64/aarch64.c (generic_vector_cost): New.
> (generic_tunings
On 25 June 2013 18:04, Ian Bolton wrote:
> 2013-06-25 Ian Bolton
>
> gcc/
> * config/aarch64/aarch64-simd.md (absdi2): Support abs for
> DI mode.
>
> testsuite/
> * gcc.target/aarch64/abs_1.c: New test.
OK
/Marcus
On 02/07/13 15:14, Yufeng Zhang wrote:
gcc/
* config/aarch64/aarch64.h (enum arm_abi_type): Remove.
(ARM_ABI_AAPCS64): Ditto.
(arm_abi): Ditto.
(ARM_DEFAULT_ABI): Ditto.
OK
/Marcus
On 02/07/13 10:01, James Greenhalgh wrote:
2013-07-02 James Greenhalgh
* config/aarch64/aarch64-builtins.c
(aarch64_simd_expand_builtin): Handle AARCH64_SIMD_STORE1.
* config/aarch64/aarch64-simd-builtins.def (ld1): New.
(st1): Likewise.
* config/aarch
hin
a single instruction, the actual effect is to look for the three tokens,
in order, anywhere in the dump file. The test fails for at least arm-*
and aarch64-* where we happen to have the appropriate three tokens
spread through the dump file.
/Marcus
2013-07-04 Marcus Shawcroft
On 10 July 2013 16:06, Andreas Schwab wrote:
> This is expected by some software (SWI Prolog checks for it).
>
> Andreas.
OK, Thank you.
... this time copying in gcc-patches from an account that won't get bounced...
/Marcus
On 12/07/13 11:25, Tejas Belagod wrote:
Hi,
This patch adds support for AdvSIMD MOVI/MVNI Vd., #imm8, MSL, #amount.
OK?
Thanks,
Tejas Belagod
ARM.
Changelog:
2013-07-12 Tejas Belagod
gcc/
* config/aarch64/aarch64-protos.h
(aarch64_simd_immediate_valid_for_move): Remove.
On 12 Jul 2013, at 19:49, "Ian Bolton" wrote:
>
> 2013-07-12 Ian Bolton
>
> gcc/
> * config/aarch64/arm_neon.h (vabs_s64): New function.
>
> testsuite/
> * gcc.target/aarch64/scalar_intrinsics.c (test_vabs_s64): Added new
> test.
OK
/Marcus
Hi,
Adding support for tiny model GOT access. Regressed, committed.
/Marcus
2013-07-15 Marcus Shawcroft
* config/aarch64/aarch64-protos.h (aarch64_symbol_type):
Define SYMBOL_TINY_GOT, update comment.
* config/aarch64/aarch64.c
On 04/07/13 09:17, James Greenhalgh wrote:
I've committed this as r200634.
As this is a bug-fix I'd like to backport it to the 4.8 branch.
I've attached a copy of the patch that applies to 4.8
and run it through testing on aarch64-none-elf with no issues.
Is this OK to commit to gcc-4_8-branch
On 26 June 2013 23:35, Yufeng Zhang wrote:
> This patch updates the AArch64 backend to support the small absolute and
> small PIC addressing models for ILP32; it also updates a number of other
> backend macros and hooks in order to support ILP32.
>
> OK for the trunk?
OK
/Marcus
On 2 July 2013 19:53, Yufeng Zhang wrote:
> Hi Andrew,
>
> Please find the updated patch in the attachment that addresses your
> comments.
>
> It now builds both ilp32 and lp64 multilibs by default, with the
> --with-multilib-list support remaining to provide options to turn off one of
> them.
>
>
On 26 June 2013 23:39, Yufeng Zhang wrote:
> This patch updates assign_parm_find_data_types to assign passed_mode and
> nominal_mode with the mode of the built pointer type instead of the
> hard-coded Pmode in the case of pass-by-reference. This is in line with the
> assignment to passed_mode and
On 26 June 2013 23:42, Yufeng Zhang wrote:
> gcc/
> * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define _ILP32
> and __ILP32__ when the ILP32 model is in use.
>
OK
/Marcus
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