On 01/05/13 16:09, James Greenhalgh wrote:
Hi,
The fcvt instructions also have forms which leave their integer
result as a scalar in the SIMD register set.
This patch adds those alternatives for the lceil family
of standard patterns.
Regression tested on aarch64-none-elf with no regressions.
Thanks,
James
---
2013-05-01 James Greenhalgh <james.greenha...@arm.com>
gcc/
* config/aarch64/aarch64.md
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): Add vector
register to vector register alternative.
(fix_trunc<GPF:mode><GPI:mode>2): Likewise.
(fixuns_trunc<GPF:mode><GPI:mode>2): Likewise.
gcc/testsuite/
* gcc.target/aarch64/scalar-fcvt.c: New.
OK
/Marcus
