RE: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

Thanks Robin. Sorry for not mentioned that it depends on another patch https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619536.html, which is in the reviewing queue. Yes, totally agree we can remove the comments for some parameters excepts the Boolean ones, as well as the term data related.

RE: [PATCH] VECT: Add LEN_FOLD_EXTRACT_LAST pattern

Committed as passed both the regression and bootstrap tests in x86, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Tuesday, August 22, 2023 7:08 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com Subjec

RE: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

Thanks Jeff for comments, and sorry for late response. The background comes from the CALL insn. For the RISC-V dynamic rounding mode we need to 1. restore the frm BEFORE call, to avoid the static rounding mode pollute the call. 2. Backup the frm AFTER call, to ensure the frm value after call is

RE: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

Thanks Jeff for comments. > Understood. So the natural question is why does x86/sh not need this > for its mode switching? Don't all the same issues exist on those > targets as well? AFAIK, it comes from the different design principle between the risc-v and x86/arm intrinsic API. The risc-v

RE: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

Thanks Jeff. > That implies a save/restore pair around the call (possibly optimized so > that we minimize the number of save/restores). I would have expected > x86 to already be doing this. But maybe there's some ABI thing around > mmx vs x86 state that allows it to be avoided Very simil

RE: [PATCH v1] RISC-V: Refactor RVV class by frm_op_type template arg

demo It looks like add a case OP_TYPE_vx but actually not. As Jeff pre-approved, will commit the v2 (add gcc_assert suggested by kito) around the end of this week if no more comments. Pan -Original Message- From: Gcc-patches On Behalf Of Li, Pan2 via Gcc-patches Sent: Tuesday, August

RE: [PATCH v2] RISC-V: Refactor RVV class by frm_op_type template arg

Committed, thanks Kito. Pan From: Kito Cheng Sent: Thursday, August 24, 2023 3:44 PM To: Li, Pan2 Cc: GCC Patches ; 钟居哲 ; Robin Dapp ; Jeff Law ; Wang, Yanzhang Subject: Re: [PATCH v2] RISC-V: Refactor RVV class by frm_op_type template arg LGTM Pan Li via Gcc-patches mailto:gcc-patches@gc

RE: [PATCH v1] RISC-V: Fix one typo in autovec.md pattern comment

Thanks Kito. Looks need some additional change and will send the V2 for this. Pan From: Kito Cheng Sent: Thursday, August 24, 2023 3:44 PM To: Li, Pan2 Cc: GCC Patches ; 钟居哲 ; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Fix one typo in autovec.md pattern comment LGTM Pan Li via Gcc-patch

RE: [PATCH v2] RISC-V: Fix one typo in autovec.md pattern comment

Committed, thanks Juzhe. Pan From: 钟居哲 Sent: Thursday, August 24, 2023 4:37 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v2] RISC-V: Fix one typo in autovec.md pattern comment LGTM juzhe.zh...@rivai.ai

RE: [PATCH] VECT: Apply LEN_FOLD_EXTRACT_LAST into loop vectorizer

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Thursday, August 24, 2023 2:39 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com Subject: Re: [PATCH] VECT: Apply LEN_FOLD_EXTRACT_LAST into loo

RE: [PATCH V2] gimple_fold: Support COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS gimple fold

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Sandiford via Gcc-patches Sent: Thursday, August 24, 2023 6:34 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; rguent...@suse.de Subject: Re: [PATCH V2] gimple_fold: Support COND_LEN_FNMA/COND_LEN

RE: [PATCH] RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Thursday, August 24, 2023 7:03 PM To: 钟居哲 ; gcc-patches Cc: rdapp@gmail.com; kito.cheng ; kito.cheng ; Jeff Law Subject: Re: [PATCH] RISC-V: Add COND_LEN_FNMA/COND_LEN_

RE: [PATCH v1] RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovec

Thanks Kito, will commit it after VFMADD, VFMSAC. Pan -Original Message- From: Kito Cheng Sent: Thursday, August 24, 2023 10:24 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFNMSAC/VFNMSUB

RE: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

m: Gcc-patches On Behalf Of Li, Pan2 via Gcc-patches Sent: Thursday, August 24, 2023 12:54 PM To: Jeff Law ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ; kito.ch...@gmail.com Subject: RE: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook Thanks Jeff. > That implie

RE: [PATCH V2] RISC-V: Support LEN_FOLD_EXTRACT_LAST auto-vectorization

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Thursday, August 24, 2023 6:23 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com; jeffreya...@gmail.com Subjec

RE: [PATCH] RISC-V: Fix uninitialized probability for GIMPLE IR tests

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Monday, August 28, 2023 8:59 PM To: Juzhe-Zhong Cc: GCC Patches ; Kito Cheng Subject: Re: [PATCH] RISC-V: Fix uninitialized probability for GIMPLE IR tests LGTM Juzhe-Zhong

RE: [PATCH v1] RISC-V: Fix one ICE for vect test vect-multitypes-5

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Tuesday, August 29, 2023 9:46 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; Wang, Yanzhang ; juzhe.zh...@rivai.ai Subject: Re: [PATCH v1] RISC-V: Fix one ICE for vect test vect-multitypes-5 LGTM, thanks :) On Tue,

RE: Re: [PATCH] RISC-V: Enable movmisalign for VLS modes

Committed, thanks Jeff and Kito. Pan -Original Message- From: Gcc-patches On Behalf Of ??? Sent: Wednesday, August 30, 2023 6:27 AM To: Jeff Law ; kito.cheng Cc: gcc-patches ; kito.cheng Subject: Re: Re: [PATCH] RISC-V: Enable movmisalign for VLS modes > OK for the trunk. Thanks. Wil

RE: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Wednesday, August 30, 2023 10:57 AM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com Subject: Re: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX v

RE: [PATCH] test: Fix XPASS of RVV

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Wednesday, August 30, 2023 6:24 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] test: Fix XPASS of RVV On Wed, 30 Aug 2023, Juzhe-Zhong wrote: > X

RE: [PATCH] test: Add xfail for riscv_vector

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Wednesday, August 30, 2023 4:36 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] test: Add xfail for riscv_vector On Wed, 30 Aug 2023, Juzhe-Zhong w

RE: [PATCH] test: Add xfail into slp-reduc-7.c for RVV VLA vectorization

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Wednesday, August 30, 2023 8:23 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] test: Add xfail into slp-reduc-7.c for RVV VLA vectorization On We

RE: [PATCH] test: Adapt slp-26.c check for RVV

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Wednesday, August 30, 2023 8:23 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] test: Adapt slp-26.c check for RVV On Wed, 30 Aug 2023, Juzhe-Zhong

RE: [PATCH] RISC-V: Add Vector cost model framework for RVV

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Thursday, August 31, 2023 8:39 PM To: Robin Dapp Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; Juzhe-Zhong Subject: Re: [PATCH] RISC-V: Add Vector cost model framework

RE: [PATCH v1] RISC-V: Support rounding mode for VFMADD/VFMACC autovec

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Thursday, August 31, 2023 9:10 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFMADD/VFMACC autovec LGTM On Thu, Aug 24

RE: [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Thursday, August 31, 2023 9:09 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec LGTM On Thu, Aug 24

RE: [PATCH v1] RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode

Committed, thanks Juzhe. Pan From: 钟居哲 Sent: Friday, September 1, 2023 3:28 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode LGTM。 juzhe.zh...@rivai.ai

RE: [PATCH] RISC-V: Add dynamic LMUL compile option

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Friday, September 1, 2023 5:58 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com Subject: Re: [PATCH] RISC-V: Add dynamic LMUL compi

RE: [PATCH] RISC-V: Enable VECT_COMPARE_COSTS by default

Committed, thank Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Friday, September 1, 2023 5:58 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com Subject: Re: [PATCH] RISC-V: Enable VECT_COMPARE_COS

RE: [PATCH v1] RISC-V: Support FP MAX/MIN autovec for VLS mode

Committed, thanks Kito. Pan From: Kito Cheng Sent: Saturday, September 2, 2023 11:41 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Support FP MAX/MIN autovec for VLS mode Ok Pan Li via Gcc-patches mailto:gcc-patches@gcc.gn

RE: [PATCH v1] RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Monday, September 4, 2023 3:29 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; Wang, Yanzhang ; juzhe.zh...@rivai.ai Subject: Re: [PATCH v1] RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic LGTM On Mon, Sep 4, 202

RE: [PATCH v1] RISC-V: Support FP SGNJ autovec for VLS mode

Committed, thanks Juzhe. Pan From: juzhe.zh...@rivai.ai Sent: Tuesday, September 5, 2023 7:14 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Support FP SGNJ autovec for VLS mode LGTM juzhe.zh...@rivai

RE: [PATCH v1] RISC-V: Fix incorrect folder for VRGATHERI16 test case

Committed, thanks Juzhe and sorry for my silly mistake. Pan From: juzhe.zhong Sent: Wednesday, September 6, 2023 8:53 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, Yanzhang ; kito.ch...@gmail.com Subject: Re: [PATCH v1] RISC-V: Fix incorrect folder for VRGATHERI16 test case lg

RE: [PATCH] RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295]

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Wednesday, September 6, 2023 9:38 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS AVL

RE: [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Wednesday, September 6, 2023 9:39 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com Subject: Re: [PATCH] RISC-V: Remove unreasonable

RE: [PATCH] RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313]

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Thursday, September 7, 2023 11:39 AM To: Juzhe-Zhong Cc: GCC Patches ; Kito Cheng Subject: Re: [PATCH] RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313]

RE: [PATCH] RISC-V: Fix incorrect nregs calculation for VLS modes

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Friday, September 8, 2023 4:12 PM To: Juzhe-Zhong Cc: GCC Patches ; Kito Cheng Subject: Re: [PATCH] RISC-V: Fix incorrect nregs calculation for VLS modes LGTM Juzhe-Zhong

RE: [PATCH] RISC-V: Suppress bogus warning for VLS types

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Friday, September 8, 2023 4:27 PM To: Juzhe-Zhong Cc: GCC Patches ; Kito Cheng Subject: Re: [PATCH] RISC-V: Suppress bogus warning for VLS types LGTM Juzhe-Zhong 於 2023年9月

RE: [PATCH] RISC-V: Fix dump FILE of VSETVL PASS[PR111311]

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Sunday, September 10, 2023 9:22 AM To: Juzhe-Zhong Cc: GCC Patches ; Kito Cheng Subject: Re: [PATCH] RISC-V: Fix dump FILE of VSETVL PASS[PR111311] LGTM Juzhe-Zhong 於 2023

RE: [PATCH V2] RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm

Committed, thanks Jeff. Pan -Original Message- From: Gcc-patches On Behalf Of Jeff Law via Gcc-patches Sent: Sunday, September 10, 2023 11:25 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com Subject: Re: [PATCH V2] RISC-V: Avoid unnecessary sl

RE: [PATCH] RISC-V: Expand fixed-vlmax/vls vector permutation in targethook

Committed, thanks Jeff. Pan -Original Message- From: Gcc-patches On Behalf Of Jeff Law via Gcc-patches Sent: Sunday, September 10, 2023 9:38 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com Subject: Re: [PATCH] RISC-V: Expand fixed-vlmax/vls v

RE: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

nserting at end of previous block from the comments. Pan -Original Message- From: Gcc-patches On Behalf Of Li, Pan2 via Gcc-patches Sent: Thursday, August 24, 2023 12:54 PM To: Jeff Law ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ; kito.ch...@gmail.com Subject: R

RE: [PATCH] RISC-V: Remove redundant functions

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Monday, September 11, 2023 5:26 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com Subject: Re: [PATCH] RISC-V: Remove redundant functions LGTM On Mon, Sep

RE: Re: [PATCH v1] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

> -if (overloaded_p && instance.pred == PRED_TYPE_m) > +if (overloaded_p) Thanks for pointing this out, my misunderstanding for policy function result in this change as mistake, will send V2 for this. > Plz change it into : Actually, it is not easy to convert to this approach as aarc

RE: [PATCH v1] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

> No. You must construct instance. 'strcmp' is very ugly. Strcmp here is defensive code here for early exit if not found (can be removed for correctness), which is not required to find the right declaration. Pan From: juzhe.zhong Sent: Monday, September 11, 2023 8:20 PM To: Li, Pan2 Cc: kito.

RE: [PATCH] RISC-V: Enable RVV scalable vectorization by default[PR111311]

Committed, thanks Jeff. Pan -Original Message- From: Gcc-patches On Behalf Of Jeff Law via Gcc-patches Sent: Monday, September 11, 2023 9:12 PM To: juzhe.zh...@rivai.ai; gcc-patches Cc: Kito.cheng ; kito.cheng Subject: Re: [PATCH] RISC-V: Enable RVV scalable vectorization by default[

RE: RE: [PATCH v1] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

For function instance with void or void arguments, it is easy as you mentioned as below. For generate API (to get the right hash), you need to build the rvv_type_info, predications_type_index and rvv_op_info from the arglist (aka vec) from hook. Then we need to construct above parameters from o

RE: RE: [PATCH v1] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

We cannot leverage this instance for correctness. The rfun of below code is the overloaded builtin is for the overloaded function, which is registered as void xxx(void) as aarch64 did to avoid the conflict. Let’s take vmv_v_i32m1 as example in rfun table. Index 0: void vmv_v(void) overloaded In

RE: RE: [PATCH v1] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

Got it, will have a try. Pan From: juzhe.zh...@rivai.ai Sent: Tuesday, September 12, 2023 9:30 AM To: Li, Pan2 Cc: kito.cheng ; gcc-patches ; Wang, Yanzhang Subject: Re: RE: [PATCH v1] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic Add a function call get_non_overloaded_inst

RE: [PATCH v2] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

>I think it's better to move 'get_non_overloaded_instance' into function_base. Sure. > Plz rewrite the comments, don't mention aarch64 sve. Sure >Could you run your rvv intrinsic api ci with this patch? >I am worrying that the resolve stuff will destroy the existing APi support. This patch only e

RE: [PATCH V5] RISC-V: Support Dynamic LMUL Cost model

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Tuesday, September 12, 2023 7:07 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com Subject: Re: [PATCH V5] RISC-V: Support Dynamic L

RE: [PATCH v1] RISC-V: Remove unused structure in cost model

Committed, thanks Jeff. Pan -Original Message- From: Jeff Law Sent: Tuesday, September 12, 2023 9:12 PM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: Wang, Yanzhang ; kito.ch...@gmail.com; juzhe.zh...@rivai.ai Subject: Re: [PATCH v1] RISC-V: Remove unused structure in cost model On 9/1

RE: [PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Wednesday, September 13, 2023 2:16 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit LGTM :) On Wed, Sep 13,

RE: [PATCH] RISC-V: Support VLS modes VEC_EXTRACT auto-vectorization

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Wednesday, September 13, 2023 8:46 PM To: juzhe.zh...@rivai.ai; gcc-patches Cc: rdapp@gmail.com; kito.cheng ; Kito.cheng ; jeffreyalaw Subject: Re: [PATCH] RISC-V: Supp

RE: [PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Thursday, September 14, 2023 3:56 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH V3] RIS

RE: [PATCH] RISC-V: Support VLS modes mask operations

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Thursday, September 14, 2023 10:23 PM To: Juzhe-Zhong Cc: GCC Patches ; Kito Cheng ; Jeff Law ; Robin Dapp Subject: Re: [PATCH] RISC-V: Support VLS modes mask operations LG

RE: Re: [PATCH v3] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

Thanks Juzhe for comments, got the point and will have a try for hashmap liked approach to get the non-overloaded later in PATCH v4. Sorry for that in the middle of something. Pan From: juzhe.zh...@rivai.ai Sent: Friday, September 15, 2023 10:21 AM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wa

RE: [PATCH v3] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

Thanks Lehua, actually Yes. Consider we will have a try for hashmap way and will keep you posted. Pan -Original Message- From: Lehua Ding Sent: Friday, September 15, 2023 10:29 AM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: Wang, Yanzhang ; kito.ch...@gmail.com; juzhe.zh...@rivai.ai Su

RE: [PATCH] test: Isolate slp-1.c check of target supports vect_strided5

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Friday, September 15, 2023 5:38 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com; richard.sandif...@arm.com Subject: Re: [PATCH] test: Isolate slp-

RE: [PATCH] test: Block slp-16.c check for target support vect_strided6

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Friday, September 15, 2023 5:38 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com; richard.sandif...@arm.com Subject: Re: [PATCH] test: Block slp-16

RE: [PATCH] test: Block vect_strided5 for slp-34-big-array.c SLP check

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Friday, September 15, 2023 6:07 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com Subject: Re: [PATCH] test: Block vect_strided5 for slp-34-big-arra

RE: [PATCH] test: Block SLP check of slp-34.c for vect_strided5

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Friday, September 15, 2023 6:07 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com Subject: Re: [PATCH] test: Block SLP check of slp-34.c for vect_st

RE: [PATCH] test: Block SLP check of slp-35.c for vect_strided5

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Friday, September 15, 2023 6:07 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com Subject: Re: [PATCH] test: Block SLP check of slp-35.c for vect_st

RE: [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode

Committed, thanks Juzhe. Pan From: 钟居哲 Sent: Saturday, September 16, 2023 7:21 AM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode lgtm juzhe.zh...@rivai.ai

RE: [PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]

Committed, thanks Robin. Pan -Original Message- From: Gcc-patches On Behalf Of Robin Dapp via Gcc-patches Sent: Friday, September 15, 2023 11:44 PM To: 钟居哲 ; Jeff Law ; kito.cheng Cc: rdapp@gmail.com; gcc-patches ; kito.cheng Subject: Re: [PATCH V4] RISC-V: Expand VLS mode to sc

RE: [PATCH v1] RISC-V: Bugfix for scalar move with merged operand

> I must be missing something. Doesn't insn 10 broadcast the immediate > 0x2 to both elements of r142?!? What am I missing? Thanks Jeff for comments. The insn 10 is VECTOR_SCALAR_MOV, aka vmv.s.x from the asm code. Pan -Original Message- From: Jeff Law Sent: Sunday, September 17, 2

RE: [PATCH] RISC-V: Support VLS modes reduction[PR111153]

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Monday, September 18, 2023 4:20 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jeffreya...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH] RISC-V:

RE: [PATCH] RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC]

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Monday, September 18, 2023 4:01 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH] RISC-V:

RE: [PATCH v1] RISC-V: Bugfix for scalar move with merged operand

Thanks Robin, let's wait Jeff's confirmation for this. Pan -Original Message- From: Robin Dapp Sent: Monday, September 18, 2023 6:01 PM To: Jeff Law ; Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; Wang, Yanzhang ; kito.ch...@gmail.com Subject: Re: [

RE: [PATCH v1] RISC-V: Bugfix for scalar move with merged operand

Committed, thanks Jeff and Robin. Pan -Original Message- From: Jeff Law Sent: Tuesday, September 19, 2023 1:44 AM To: Robin Dapp ; Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ; kito.ch...@gmail.com Subject: Re: [PATCH v1] RISC-V: Bugfix for scalar move

RE: [PATCH v1] RISC-V: Support VLS mode for vec_set

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Monday, September 18, 2023 11:36 AM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Support VLS mode for vec_set LGTM On Mon, Sep 18, 2023 at 11:27 A

RE: [PATCH] RISC-V: Allow Vector IOR(V1, NOT V1) optimiztion

; rguent...@suse.de; Wang, Yanzhang ; richard.sandif...@arm.com Subject: Re: [PATCH] RISC-V: Allow Vector IOR(V1, NOT V1) optimiztion On Tue, Apr 18, 2023 at 9:59 AM Richard Biener wrote: > > On Tue, Apr 18, 2023 at 3:31 AM Li, Pan2 via Gcc-patches > wrote: > > > > Passed

RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization

Oh, I see. The message need to be re-generated. Thank you for pointing out, will update ASPA. Pan -Original Message- From: Richard Biener Sent: Wednesday, April 19, 2023 2:40 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; richard.sandif...@a

RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization

Hi Richard, Do you have any idea about this? I leverage git gcc-commit-mklog, it will generate something as below. It looks no text after colon. I am not sure if I need to add something by myself. gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): <=

RE: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

Passed the X86 bootstrap and regression tests. Pan -Original Message- From: Li, Pan2 Sent: Wednesday, April 19, 2023 11:21 AM To: gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang ; Li, Pan2 Subject: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) sho

RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization

Thank you for information. Updated the v3 version as below. https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616154.html Pan -Original Message- From: Richard Biener Sent: Wednesday, April 19, 2023 4:52 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@s

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

Sure thing. For Changlog, I consider it was generated automatically in previous. LOL. Pan -Original Message- From: Kito Cheng Sent: Wednesday, April 19, 2023 5:46 PM To: juzhe.zh...@rivai.ai Cc: Li, Pan2 ; gcc-patches ; Kito.cheng ; Wang, Yanzhang Subject: Re: Re: [PATCH] RISC-V: All

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

Update the Patch v2 for more detail information for clarification. Please help to review continuously. https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html Pan -Original Message- From: Li, Pan2 Sent: Wednesday, April 19, 2023 6:33 PM To: Kito Cheng ; juzhe.zh...@rivai.ai Cc

RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.

Hi Kito, There is one patch reviewed already and I suppose it will be ok after GCC 14 open. Could you please help to double check about it? Pann -Original Message- From: Gcc-patches On Behalf Of Li, Pan2 via Gcc-patches Sent: Wednesday, March 29, 2023 6:39 PM To: juzhe.zh...@rivai.ai

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

Kindly ping for the PATCH v2. Just FYI there will be some underlying investigation based on this PATCH like VMSEQ. Pan -Original Message- From: Li, Pan2 Sent: Wednesday, April 19, 2023 7:27 PM To: 'Kito Cheng' ; 'juzhe.zh...@rivai.ai' Cc: 'gcc-patches' ; 'Kito.cheng' ; Wang, Yanzhang

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

n_insn, at optabs.cc:8102 8 | vbool64_t mask = *(vbool64_t*) (in + 100); | ^~~~ 0x130d278 maybe_gen_insn(insn_code, unsigned int, expand_operand*) ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8102 On Fri, Apr 21, 2023 at 5:47 PM Li, Pan2 via Gcc-patch

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

pr 21, 2023 at 7:17 PM Li, Pan2 via Gcc-patches wrote: > > Thanks kito, will try to reproduce this issue and keep you posted. > > Pan > > -Original Message- > From: Kito Cheng > Sent: Friday, April 21, 2023 6:17 PM > To: Li, Pan2 > Cc: juzhe.zh...@rivai.ai;

RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.

: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal. Hi Kito, There is one patch reviewed already and I suppose it will be ok after GCC 14 open. Could you please help to double check about it? Pann -Original Message- From: Gcc-patches On Behalf Of Li, Pan2 via Gcc

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

ation Second thought on this, we should just add define_split rather than define_insn_and_split, otherwise we might hit the same issue again, and I expect the split pattern will only used in combine pass. On Sat, Apr 22, 2023 at 1:34 PM Li, Pan2 via Gcc-patches wrote: > > Hi Kito > &g

RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.

rror: hook declined to update refs/heads/master On Mon, Apr 24, 2023 at 7:14 PM Li, Pan2 via Gcc-patches wrote: > > Hi, > > Just synced this patch with upstream, and passed the X86 bootstrap and > regression test already. > > Pan > > -Original Message- > F

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

gt; Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization Second thought on this, we should just add define_split rather than define_insn_and_split, otherwise we might hit the same issue again, and I expect the split pattern will only used in combine pass. On Sa

RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.

Please see: https://gcc.gnu.org/codingconventions.html#ChangeLogs remote: *** remote: error: hook declined to update refs/heads/master On Mon, Apr 24, 2023 at 7:14 PM Li, Pan2 via Gcc-patches wrote: > > Hi, > > Just synced this patch with upstream, and passed the X86 bootstrap and >

RE: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization

H] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization Second thought on this, we should just add define_split rather than define_insn_and_split, otherwise we might hit the same issue again, and I expect the split pattern will only used in combine pass. On Sat, Apr 22, 2023 at 1:34 PM Li

RE: [PATCH v3] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal

Thanks a lot, kito, will pay more attention for the changelogs. Pan From: Kito Cheng Sent: Wednesday, April 26, 2023 11:30 AM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v3] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal Committed, t

RE: [PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API

Great! Thanks yanzhang. Could you please help to add some text about the changes below? Or kito may meet some error by git hook when commit the PATCH. gcc/ChangeLog: * config/riscv/vector-iterators.md: <- add text for change. gcc/testsuite/ChangeLog: *

RE: [PATCH] RISC-V: Legitimise the const0_rtx for RVV load/store address

Thanks Kito. It comes from some experience of Ju-Zhe for auto vectorization in previous. Pan -Original Message- From: Kito Cheng Sent: Wednesday, April 26, 2023 9:24 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang Subject: Re:

RE: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR

Thanks Kito for the better approach. It works well with the prepared test cases but I may have one question about the semantics of the vector_move_operand. The defined predicate of vector_move_operand composes of (non-imm || (const vector && (reload_completed ? constraint_vi (op) : constraint_wc

RE: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR

Thanks, kito. Yes, you are right. I am investigating this right now from simplify rtl. Given we have one similar case VMORN in previous. Pan -Original Message- From: Kito Cheng Sent: Friday, April 28, 2023 2:41 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang,

RE: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR

Passed both the X86 bootstrap and regression test. Pan -Original Message- From: Li, Pan2 Sent: Friday, April 28, 2023 2:45 PM To: Kito Cheng Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: RE: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMC

RE: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API

Kindly ping for this ICE fix. Pan -Original Message- From: Wang, Yanzhang Sent: Wednesday, April 26, 2023 9:06 PM To: gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 ; Wang, Yanzhang Subject: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API From:

RE: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR

Cool, Thank you! Pan -Original Message- From: Kito Cheng Sent: Friday, April 28, 2023 8:37 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR pushed, thanks!

RE: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET

Thanks Jeff for comments. It makes sense to me. For the EQ operator we should have CONSTM1. Does this mean s390 parts has similar issue here? Then for instructions like VMSEQ, we need to adjust the simplify_rtx up to a point. Please help to correct me if any mistake. Thank you again. Pan

RE: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET

Hi Jeff Just have a try in simplify_rtx for this optimization in PATCH v2. Could you please help to share any idea about this when you free? Thank you! https://gcc.gnu.org/pipermail/gcc-patches/2023-April/617117.html Pan -Original Message- From: Li, Pan2 Sent: Saturday, April 29, 2023

RE: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET

Thanks all for comments. Summary what I have learned from the mail thread as below. Please feel free to correct me if any mistake. 1. The RVV VMSET has tail policy and the high bits of target register can be overridden to 1 or retain the value they held according to the ISA. 2. The semantics of

RE: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET

Thanks all for comments, will work with kito to make it happen. Pan -Original Message- From: Jeff Law Sent: Wednesday, May 3, 2023 12:28 AM To: Kito Cheng Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang ; Andrew Waterman Subject: Re: [PATCH] RISC-V: Allo

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