Thanks Kito. It comes from some experience of Ju-Zhe for auto vectorization in
previous.
Pan
-----Original Message-----
From: Kito Cheng <kito.ch...@gmail.com>
Sent: Wednesday, April 26, 2023 9:24 PM
To: Li, Pan2 <pan2...@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang <yanzhang.w...@intel.com>
Subject: Re: [PATCH] RISC-V: Legitimise the const0_rtx for RVV load/store
address
LGTM, pushed to trunk
> This patch try to legitimise the const0_rtx (aka zero register) as the
> base register for the RVV load/store instructions.
>
> For example:
> vint32m1_t test_vle32_v_i32m1_shortcut (size_t vl) {
> return __riscv_vle32_v_i32m1 ((int32_t *)0, vl); }
The example is kind of counter intuitive to me, I know it's legal from ISA spec
level, but can't understand why it's useful...until I saw you mention auto vec
and index load - I realized this is optimization for gather/scatter code gen.
