Hi all,
This patch reimplements the MD patterns for the
UHADD,SHADD,UHSUB,SHSUB,URHADD,SRHADD instructions using
standard RTL operations rather than unspecs. The correct RTL representations
involves widening
the inputs before adding them and halving, followed by a truncation back to the
origina
Hi all,
This patch converts the patterns for the integer widen and pairwise-add
instructions
to standard RTL operations. The pairwise addition withing a vector can be
represented
as an addition of two vec_selects, one selecting the even elements, and one
selecting odd.
Thus for the intrinsic vp
> -Original Message-
> From: Christophe Lyon
> Sent: Tuesday, May 30, 2023 3:00 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Chris Sidebottom
> Cc: Christophe Lyon
> Subject: [PATCH] [arm][testsuite]: Fix ACLE data-intrinsics testcases
>
> data-intrinsics-assembly.c forces -ma
Ok.
Thanks,
Kyrill
From: Christophe Lyon
Sent: Tuesday, May 30, 2023 4:44 PM
To: Kyrylo Tkachov
Cc: gcc-patches@gcc.gnu.org; Stam Markianos-Wright
Subject: Re: [PATCH] [arm] testsuite: make mve_intrinsic_type_overloads-int.c
libc-agnostic
Ping?
On Tue, 23 May 2023 at 16:59, Stamatis Markia
Hi all,
If the output code for a define_insn just does a switch (which_alternative)
with no other computation we can almost always
replace it with more compact MD syntax for each alternative in a
mult-alternative '@' block.
This patch cleans up some such patterns in the aarch64 backend, making t
Hi all,
This patch goes through the various alphabet soup saturating multiplication
patterns, including those in TARGET_RDMA
and annotates them with . Many other patterns are widening and
always write the full 128-bit vectors
so this annotation doesn't apply to them. Nothing out of the ordinary
Hi all,
This straightforward patch annotates the dotproduct instructions, including the
i8mm ones.
Tests included.
Nothing unexpected here.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/99195
Hi all,
We can use the X registers to load and store 64-bit vector modes, we just need
to add the alternatives
to the mov patterns. This straightforward patch does that and for the pair
variants too.
For the testcase in the code we now generate the optimal assembly without any
superfluous
GP<->
Hi all,
We've received requests to optimise the attached intrinsics testcase.
We currently generate:
foo_1:
uaddlp v0.4s, v0.8h
uaddlv d31, v0.4s
fmovx0, d31
ret
foo_2:
uaddlp v0.4s, v0.8h
addvs31, v0.4s
fmovw0, s31
ret
Hi all,
Now that we've got the annotations we can get rid of explicit
!BYTES_BIG_ENDIAN and BYTES_BIG_ENDIAN patterns for the narrowing shift
instructions.
This allows us to clean up the expanders as well.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to tru
Hi all,
Having converted the patterns for the URSRA,SRSRA instructions to standard RTL
codes we can also
easily convert the non-accumulating forms URSHR,SRSHR.
This patch does that, reusing the various helpers and predicates from that
patch in a straightforward way.
This allows GCC to perform th
Hi all,
The aarch64_addpdi pattern is redundant as the reduc_plus_scal_ pattern
can already generate
the required form of the ADDP instruction, and is mostly folded to GIMPLE early
on so can benefit from more optimisations.
Though it turns out that we were missing the folding for the unsigned va
Hi all,
Similar to the ADDLP instructions the non-widening ADDP ones can be
represented by adding the odd lanes with the even lanes of a vector.
These instructions take two vector inputs and the architecture spec
describes the operation as concatenating them together before going
through it with p
Hi all,
This patch removes UNSPEC_SQXTUN and uses organic RTL codes to represent the
operation.
SQXTUN is an odd one. It's described in the architecture as "Signed saturating
extract Unsigned Narrow".
It's not a straightforward ss_truncate nor a us_truncate.
It is a sort of truncating signed cla
Hi all,
This patch implements RTL constant-folding for the SS_TRUNCATE and US_TRUNCATE
codes.
The semantics are a clamping operation on the argument with the min and max of
the narrow mode,
followed by a truncation. The signedness of the clamp and the min/max extrema
is derived from
the signedn
Hi Richard,
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, June 9, 2023 7:08 PM
> To: Kyrylo Tkachov via Gcc-patches
> Cc: Kyrylo Tkachov
> Subject: Re: [PATCH] simplify-rtx: Implement constant folding of
> SS_TRUNCATE, US_TRUNCATE
>
> Kyr
Hi all,
After discussing the -mtp= option with Arm's LLVM developers we'd like to extend
the functionality of the option somewhat.
First of all, there is another TPIDR register that can be used to read the
thread pointer:
TPIDRRO_EL0 (which can also be accessed by AArch32 under another name) so i
Hi all,
After discussing the -mtp= option with Arm's LLVM developers we'd like to extend
the functionality of the option somewhat.
There are actually 3 system registers that can be accessed for the thread
pointer
in aarch32: tpidrurw, tpidruro, tpidrprw. They are all read through the CP15
co-pr
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Prathamesh
> Kulkarni via Gcc-patches
> Sent: Wednesday, June 14, 2023 8:13 AM
> To: Tejas Belagod
> Cc: Richard Sandiford ; gcc-
> patc...@gcc.gnu.org
> Subject: Re: [PATCH v2] [PR96339] O
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, July 13, 2023 11:22 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH 1/2] [testsuite,arm]: Make nomve_fp_1.c require arm_fp
>
> If GCC is configured with the de
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, July 13, 2023 11:22 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH 2/2] [testsuite,arm]: Make mve_fp_fpu[12].c accept single or
> double precision FPU
>
> Thi
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, July 13, 2023 11:22 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 1/6] arm: [MVE intrinsics] Factorize vcaddq vhcaddq
>
> Factorize vca
Hi Tamar,
Let me be the latest to offer my apologies for the slow review.
> -Original Message-
> From: Tamar Christina
> Sent: Wednesday, June 8, 2022 3:49 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
> ; Richard Sandiford
>
> Subjec
> -Original Message-
> From: Richard Sandiford
> Sent: Wednesday, July 13, 2022 9:14 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Kyrylo Tkachov
>
> Subject: [PATCH] arm: Replace arm_builtin_vectorized_function [PR106253]
>
> This patch extends the fix for PR106253 to AArc
> -Original Message-
> From: Tamar Christina
> Sent: Monday, August 8, 2022 10:28 AM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org
> Cc: nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Richard Sandiford
>
> Subject: RE: [PATCH 1/2]AArch64 Fix 128-bit sequential consistency atomic
> operat
> -Original Message-
> From: Tamar Christina
> Sent: Wednesday, June 8, 2022 3:50 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Ramana Radhakrishnan
> ; Richard Earnshaw
> ; ni...@redhat.com; Kyrylo Tkachov
>
> Subject: [PATCH 2/2][AArch32] Fix 128-bit sequential consistency atomic
> oper
Ok.
Thanks,
Kyrill
From: Stam Markianos-Wright
Sent: Saturday, August 19, 2023 12:42 PM
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
Subject: [PING][PATCH] arm: Remove unsigned variant of vcaddq_m
(Pinging since I realised that this is required for my later Low Overhead
Hi all,
In the testcase for this patch we try to vec_concat the lowpart and highpart of
a vector, but the lowpart is expressed as a subreg.
simplify-rtx.cc does not recognise this and combine ends up trying to match:
Trying 7 -> 8:
7: r93:V2SI=vec_select(r95:V4SI,parallel)
8: r97:V4SI=vec
This patch reimplements the MD patterns for the instructions that
perform narrowing right shifts with optional rounding and saturation
using standard RTL codes rather than unspecs.
There are four groups of patterns involved:
* Simple narrowing shifts with optional signed or unsigned truncation:
S
The first patch in the series has some fallout in the testsuite,
particularly gcc.target/aarch64/shrn-combine-2.c.
Our previous patterns for SHRN matched both
(truncate (ashiftrt (x) (N))) and (truncate (lshiftrt (x) (N))
as these are equivalent for the shift amounts involved.
In our refactoring, h
Similar to the low-half patterns, we want to match both ashiftrt and
lshiftrt with the truncate for SHRN2. We reuse the SHIFTRT iterator
and the AARCH64_VALID_SHRN_OP check to help, but because we expand the
high-half patterns by their gen_* names we need to disambiguate all the
different trunc+sh
Some instructions from the previous patch have scalar forms:
SQSHRN,SQRSHRN,UQSHRN,UQRSHRN,SQSHRUN,SQRSHRUN.
This patch converts the patterns for these to use standard RTL codes.
Their MD patterns deviate slightly from the vector forms mostly due to
things like operands being scalar rather than vec
Hi all,
This patch series reimplements the MD patterns for the instructions that
perform narrowing right shifts with optional rounding and saturation
using standard RTL codes rather than unspecs. This includes the scalar
forms and the *2 forms that write to the high half of the result vector.
Thi
This patch is large in lines of code, but it is a fairly regular
extension of the first patch as it converts the high-half patterns
to standard RTL codes in the same fashion as the first patch did for the
low-half ones.
This now allows us to remove the unspec codes for these instructions as
there a
Hi all,
We've been asked to optimise the testcase in this patch of a 64-bit ADDP with
the low and high halves of the same 128-bit vector. This can be done by a
single .4s ADDP followed by just reading the bottom 64 bits. A splitter for
this is quite straightforward now that all the vec_concat stuf
Hi all,
This patch converts the SVE load gather patterns to the new compact syntax
that Tamar introduced. This allows for a future patch I want to contribute
to add more alternatives that are better viewed in the more compact form.
The lines in some patterns are >80 long now, but I think that's u
Hi all,
The architecture recommends that load-gather instructions avoid using the same
Z register for the load address and the destination, and the Software
Optimization
Guides for Arm cores recommend that as well.
This means that for code like:
#include
svuint64_t
food (svbool_t p, uint64_t *i
Hi all,
aarch64_simd_rsra_rnd_imm_vec is now used for more than just RSRA
and accepts more than just vectors so rename it to make it more
truthful.
The aarch64_simd_rshrn_imm_vec is now unused and can be deleted.
No behavioural change intended.
Bootstrapped and tested on aarch64-none-linux-gnu.
P
Hi all,
In the scalar pattern for SQRSHRUN it's a bit clearer to use DWI instead of
V2XWIDE
to make it more clear that no vector modes are involved.
No behavioural change intended.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
* conf
Hi Christophe,
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, June 26, 2023 4:03 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Sandiford
> Cc: Christophe Lyon
> Subject: [PATCH] arm: Fix MVE intrinsics support with LTO (PR target/110268)
>
> After the recen
Hi Christophe,
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, July 6, 2023 4:21 PM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; Richard Sandiford
>
> Subject: Re: [PATCH] arm: Fix MVE intrinsics support with LTO (PR
> target/110268)
>
>
>
> On Wed, 5 Jul 2023 a
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, July 7, 2023 8:52 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH] testsuite: Add _link flavor for several arm_arch* and arm*
> effective-targets
>
> For arm tar
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, July 7, 2023 8:52 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH] doc: Document arm_v8_1m_main_cde_mve_fp
>
> The arm_v8_1m_main_cde_mve_fp family of effective
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, July 10, 2023 2:09 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH v2] arm: Fix MVE intrinsics support with LTO (PR
> target/110268)
>
> After the recent MVE int
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, July 10, 2023 2:59 PM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
>
> Subject: Re: [PATCH] testsuite: Add _link flavor for several arm_arch* and
> arm* effective-targets
>
>
>
> On Mon, 10 Jul 2023
Hi Alexandre,
> -Original Message-
> From: Alexandre Oliva
> Sent: Friday, February 17, 2023 7:06 AM
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> ramana@gmail.com; Kyrylo Tkachov
> Subject: [PATCH] [arm] disable aes-1742098 mitigation for a72 combine tes
Hi all,
Here's a patch that fleshes out the changes.html entries for arm and aarch64.
I did a quick scan through appropriately filtered git logs and wrote up stuff
that I think is user-visible,
but please shout if you know of things that should be highlighted as there's
been much great work done
Hi all,
With the cleanup of the arch features in GCC 13 the comment on the FLAGS field
in aarch64-cores.def
is now outdated. It's now a comma-separated list rather than a bitwise or.
Spotted while reviewing an aarch64-cores.def patch.
Update the comment.
Pushing to trunk.
Thanks,
Kyrill
gcc/Cha
Pushing as obvious.
gcc/ChangeLog:
* config/aarch64/aarch64.md (aarch64_abs): Fix typo in comment.
typo.patch
Description: typo.patch
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo
> Tkachov via Gcc-patches
> Sent: Monday, February 27, 2023 10:00 AM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH][committed] aarch64: Fix typo in comm
> -Original Message-
> From: Alexandre Oliva
> Sent: Friday, February 17, 2023 7:39 AM
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> ramana@gmail.com; Kyrylo Tkachov
> Subject: [PATCH] [PR104882] [arm] require mve hw for mve run test
>
>
> The pr10488
> -Original Message-
> From: Alexandre Oliva
> Sent: Friday, February 17, 2023 7:36 AM
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> ramana@gmail.com; Kyrylo Tkachov ;
> Andrea Corallo
> Subject: [PATCH] [arm] complete vmsr/vmrs blank and case adjustment
> -Original Message-
> From: Alexandre Oliva
> Sent: Friday, February 17, 2023 7:14 AM
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw
> Subject: [PATCH] [PR51534] [arm] split out pr51534 test for softfp
>
>
> The test uses arm_hard_ok and arm_softfp_ok as if t
> -Original Message-
> From: Alexandre Oliva
> Sent: Friday, February 17, 2023 7:12 AM
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw
> Subject: [PATCH] [arm] adjust expectations for armv8_2-fp16-move-[12].c
>
>
> Commit 3a7ba8fd0cda387809e4902328af2473662b6a4
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Alexandre
> Oliva via Gcc-patches
> Sent: Friday, March 3, 2023 8:24 AM
> To: Christophe Lyon
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] [arm] adjust tests for quotes around +cdec
Hi all,
This patch cleans up some almost-duplicate patterns for the XTN, SQXTN, UQXTN
instructions.
Using the attributes we can remove the BYTES_BIG_ENDIAN and
!BYTES_BIG_ENDIAN cases,
as well as the intrinsic expanders that select between the two.
Tests are also added. Thankfully the diffstat
Hi all,
This patch deletes the explicit BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN patterns
for the QSHRN instructions in favour
of annotating a single one with . This allows simplification of
the expander too.
Tests are added to ensure that we still optimise away the concat-with-zero use
case.
Bo
Hi all,
Moving onto the saturating instructions, this one goes through the simple
add/sub ones.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_q)
Hi all,
Another straightforward patch annotating patterns for the zip1, zip2, uzp1,
uzp2, rev* instructions, plus tests.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/99195
* config/aarch64/a
Hi all,
This patch is a no-op as it removes the explicit vec-concat-zero patterns in
favour of vczle/vczbe.
This allows us to delete the explicit expander too. Tests are added to ensure
the optimisation required
still triggers.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-no
> -Original Message-
> From: Christophe Lyon
> Sent: Wednesday, May 10, 2023 2:31 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 15/20] arm: [MVE intrinsics] add unary_acc shape
>
> This patch adds t
> -Original Message-
> From: Christophe Lyon
> Sent: Wednesday, May 10, 2023 2:30 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/20] arm: [MVE intrinsics] factorize vcmp
>
> Factorize vcmp so that
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, May 11, 2023 9:21 AM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org;
> Richard Earnshaw ; Richard Sandiford
>
> Subject: Re: [PATCH 15/20] arm: [MVE intrinsics] add unary_acc shape
>
>
>
> On 5/10/23 16:52, Kyrylo Tkachov
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, May 11, 2023 1:19 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/24] arm: [MVE intrinsics] factorize vaddlvaq
>
> Factorize vaddlvaq
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 12, 2023 10:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/26] arm: [MVE intrinsics] add binary_widen_opt_n shape
>
> This patch
Hi all,
Straightforward like previous patches in this series.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_s): Rename to...
(aarch64_s)
Hi all,
This instalment of the series goes through the vector comparison patterns in
the backend.
One wart are the int64x1_t comparisons that this patch doesn't touch.
Those are a bit trickier because they have define_insn_and_split mechanisms for
falling back to
GP reg comparisons after reload
> -Original Message-
> From: Richard Sandiford
> Sent: Monday, May 15, 2023 10:01 AM
> To: Evandro Menezes via Gcc-patches
> Cc: evandro+...@gcc.gnu.org; Evandro Menezes ;
> Kyrylo Tkachov ; Tamar Christina
>
> Subject: Re: [PATCH] aarch64: Add SVE instruction types
>
> Evandro Menez
Hi all,
We are missing cases for combining of FACGE/FACGT instructions. In the testcase
of the patch we generate:
foo:
fabsv3.4s, v0.4s
fabsv0.4s, v1.4s
fabsv1.4s, v2.4s
fcmgt v0.4s, v3.4s, v0.4s
fcmgt v1.4s, v3.4s, v1.4s
b g
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Richard Biener
> via Gcc-patches
> Sent: Monday, May 15, 2023 8:59 AM
> To: Thomas Neumann
> Cc: Sören Tempel ; gcc-patches@gcc.gnu.org;
> al...@ayaya.dev
> Subject: Re: [PATCH] Fix asserti
> -Original Message-
> From: Thomas Neumann
> Sent: Monday, May 15, 2023 2:06 PM
> To: Kyrylo Tkachov ; Richard Biener
>
> Cc: Sören Tempel ; gcc-patches@gcc.gnu.org;
> al...@ayaya.dev
> Subject: Re: [PATCH] Fix assertion for unwind-dw2-fde.c btree changes
>
> > Hello, this patch break
Hi Richard,
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Richard
> Sandiford via Gcc-patches
> Sent: Tuesday, May 9, 2023 7:48 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: [PATCH 2/6] aarch64: Allow moves after t
> -Original Message-
> From: Richard Sandiford
> Sent: Monday, May 15, 2023 3:18 PM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 2/6] aarch64: Allow moves after tied-register intrinsics
>
> Kyrylo Tkachov writes:
> > Hi Richard,
> >
> >> -Original Mess
Hi Evandro,
I created a new attribute so I didn’t have to extend the “type” attribute that
lives in config/arm/types.md. As that attribute and file lives in the arm
backend but SVE is AArch64-only I didn’t want to add logic to the arm backend
as it’s not truly shared.
The granularity has been s
Hi Stam,
> -Original Message-
> From: Stam Markianos-Wright
> Sent: Tuesday, May 16, 2023 2:32 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Andrea Corallo
> Subject: [GCC12 backport] arm: MVE testsuite and backend bugfixes
>
> Hi all,
>
> We've recently
> -Original Message-
> From: Stam Markianos-Wright
> Sent: Wednesday, May 17, 2023 2:41 PM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Andrea Corallo
>
> Subject: [GCC12 backport] arm: MVE testsuite and backend bugfixes
>
>
> On 17/05/2023 10:26, Kyrylo Tka
Hi all,
While optimising some vector math library code with intrinsics we stumbled upon
the issue in the testcase.
The compiler should be generating a FACGT instruction but instead we generate:
foo(__Float32x4_t, __Float32x4_t, __Float32x4_t):
fabsv0.4s, v0.4s
adrpx0, .LC0
Hi all,
This patch expresses the intrinsics for the SRA and RSRA instructions with
standard RTL codes rather than relying on UNSPECs.
These instructions perform a vector shift right plus accumulate with an
optional rounding constant addition for the RSRA variant.
There are a number of interesting
Hi all,
In this PR we ICE because the substituted pattern for mla "lost" its predicate
and constraint for operand 0
because the define_subst template:
[(set (match_operand: 0)
(vec_concat:
(match_dup 1)
(match_operand:VDZ 2 "aarch64_simd_or_scalar_imm_zero")))])
Uses
Hi Alex,
> -Original Message-
> From: Alex Coplan
> Sent: Thursday, May 11, 2023 12:15 PM
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo Tkachov
>
> Subject: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]
>
> Hi,
>
>
Hi all,
As the PR says we shouldn't be using qualifier_unsigned for the return type of
the __ssat intrinsics.
UNSIGNED_SAT_BINOP_UNSIGNED_IMM_QUALIFIERS already exists for that.
This was just a thinko.
This patch fixes this and the warning with -Wconversion goes away.
Bootstrapped and tested on
Hi all,
Continuing the series of straightforward annotations, this one handles the
normal (not widening or narrowing) vector shifts.
Tests included.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/9919
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Thursday, May 18, 2023 12:14 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: [PATCH] aarch64: Implement vector FP absolute compare intrinsics
> with builtins
>
> Hi all,
>
> While optimising some vector math libra
Ping.
Thanks,
Kyrill
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo
> Tkachov via Gcc-patches
> Sent: Thursday, May 18, 2023 4:19 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] stor-layout, aarch64: E
> -Original Message-
> From: Alex Coplan
> Sent: Thursday, May 25, 2023 11:26 AM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
>
> Subject: Re: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]
>
> Hi Kyrill,
>
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo
> Tkachov via Gcc-patches
> Sent: Thursday, May 25, 2023 11:48 AM
> To: Alex Coplan
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
>
Hi all,
This patch implements a number of scalar data processing intrinsics from ACLE
that were requested by some users. Some of these have fast single-instruction
sequences for Armv6 and later, but even for earlier versions they can still emit
an inline sequence or a call to libgcc (and ACLE reco
Hi all,
This patch annotates the complex add and mla patterns for vec-concat-zero.
Testing showed an interesting bug in our MD patterns where they were defined to
match:
(plus:VHSDF (match_operand:VHSDF 1 "register_operand" "0")
(unspec:VHSDF [(match_operand:VHSDF 2 "r
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, May 25, 2023 1:25 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov
> Cc: Christophe Lyon
> Subject: [PATCH 1/1] arm: merge MVE_5 and MVE_6 iterators
>
> MVE_5 and MVE_6 iterators are the same: this patch replaces MVE_6 wi
> -Original Message-
> From: Gcc-patches On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 21 January 2021 13:37
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] Fix typo in arm_mve.h __arm_vcmpneq_s8 return type
>
> Like all vcmp intrinsics, __arm_vcmpneq_s8 should return a mve_p
Hi all,
The aarch64_sqdmll patterns are of the form:
[(set (match_operand: 0 "register_operand" "=w")
(SBINQOPS:
(match_operand: 1 "register_operand" "0")
(ss_ashift:
(mult:
(sign_extend:
(match_operand:VSD_HSI 2 "re
Hi all,
We ICE here because we end up comparing a poly_int64 with a scalar using <=
rather than known_le.
This patch fixes that in the way richi suggests in the PR.
Bootstrapped and tested on aarch64-none-linux-gnu.
Ok for trunk?
Thanks,
Kyrill
gcc/ChangeLog:
PR tree-optimization/9876
> -Original Message-
> From: Tamar Christina
> Sent: 21 January 2021 18:54
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Ramana Radhakrishnan
> ; Richard Earnshaw
> ; ni...@redhat.com; Kyrylo Tkachov
>
> Subject: [PATCH]Arm: Add NEON and MVE complex mul, mla and mls
> patterns.
>
> Hi All,
Hi Richard,
> -Original Message-
> From: Richard Sandiford
> Sent: 22 January 2021 13:09
> To: Kyrylo Tkachov via Gcc-patches
> Cc: Kyrylo Tkachov
> Subject: Re: [PATCH] tree-ssa-mathopts: Use proper poly_int64 comparison
> with param_avoid_fma_max_bits [PR 98766
Hi all,
This patch adds the arm and aarch64 sections changes.html for GCC 11.
There's more than that that went into the release, but this can serve as a
starting point for filling the sections in.
Pushing to the repo.
Thanks,
Kyrill
wwwdocs-arm.patch
Description: wwwdocs-arm.patch
Hi Christophe,
> -Original Message-
> From: Gcc-patches On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 26 January 2021 18:03
> To: gcc Patches
> Subject: arm: Adjust cost of vector of constant zero
>
> Neon vector comparisons have a dedicated version when comparing with
> consta
> -Original Message-
> From: Jonathan Wright
> Sent: 26 January 2021 11:43
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Sandiford
>
> Subject: [PATCH] aarch64: Use RTL builtins for integer mla_n intrinsics
>
> Hi,
>
> As subject, this patch rewrites integer mla_n Neon
> -Original Message-
> From: Christophe Lyon
> Sent: 27 January 2021 13:12
> To: Kyrylo Tkachov
> Cc: Kyrylo Tkachov via Gcc-patches
> Subject: Re: arm: Adjust cost of vector of constant zero
>
> On Wed, 27 Jan 2021 at 10:15, Kyrylo Tkachov
> w
> -Original Message-
> From: Christophe Lyon
> Sent: 27 January 2021 13:56
> To: Kyrylo Tkachov
> Cc: Kyrylo Tkachov via Gcc-patches
> Subject: Re: arm: Adjust cost of vector of constant zero
>
> On Wed, 27 Jan 2021 at 14:44, Kyrylo Tkachov
> wrote:
>
From: Jonathan Wright
Sent: 27 January 2021 12:57
To: Richard Sandiford ; Kyrylo Tkachov
Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
Subject: Re: [PATCH] aarch64: Use GCC vector extensions for integer mls
intrinsics
I have re-written this to use RTL builtins - regression tested and boots
1 - 100 of 711 matches
Mail list logo
