[PATCH][committed] aarch64: PR target/99195 annotate simple narrowing patterns for vec-concat-zero

Wed, 10 May 2023 02:42:06 -0700 

Hi all,

This patch cleans up some almost-duplicate patterns for the XTN, SQXTN, UQXTN 
instructions.
Using the <vczle><vczbe> attributes we can remove the BYTES_BIG_ENDIAN and 
!BYTES_BIG_ENDIAN cases,
as well as the intrinsic expanders that select between the two.
Tests are also added. Thankfully the diffstat comes out negative \O/.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

        * config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le): Delete.
        (aarch64_xtn<mode>_insn_be): Likewise.
        (trunc<mode><Vnarrowq>2): Rename to...
        (trunc<mode><Vnarrowq>2<vczle><vczbe>): ... This.
        (aarch64_xtn<mode>): Move under the above.  Just emit the truncate RTL.
        (aarch64_<su>qmovn<mode>): Likewise.
        (aarch64_<su>qmovn<mode><vczle><vczbe>): New define_insn.
        (aarch64_<su>qmovn<mode>_insn_le): Delete.
        (aarch64_<su>qmovn<mode>_insn_be): Likewise.

gcc/testsuite/ChangeLog:

        * gcc.target/aarch64/simd/pr99195_4.c: Add tests for vmovn, vqmovn.

Attachment: vcxtn.patch
Description: vcxtn.patch

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