RE: [PATCH 01/20] arm: [MVE intrinsics] factorize vcmp

[Kyrylo Tkachov via Gcc-patches]

> -----Original Message-----
> From: Christophe Lyon <christophe.l...@arm.com>
> Sent: Wednesday, May 10, 2023 2:30 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <kyrylo.tkac...@arm.com>;
> Richard Earnshaw <richard.earns...@arm.com>; Richard Sandiford
> <richard.sandif...@arm.com>
> Cc: Christophe Lyon <christophe.l...@arm.com>
> Subject: [PATCH 01/20] arm: [MVE intrinsics] factorize vcmp
> 
> Factorize vcmp so that they use the same pattern.
> 

Besides my comments on patch 15/20, this series looks good.
So once that patch is resolved, this series is ok for trunk.
Thanks,
Kyrill

> 2022-10-25  Christophe Lyon  <christophe.l...@arm.com>
> 
>       gcc/
>       * config/arm/iterators.md (MVE_CMP_M, MVE_CMP_M_F,
> MVE_CMP_M_N)
>       (MVE_CMP_M_N_F, mve_cmp_op1): New.
>       (isu): Add VCMP*
>       (supf): Likewise.
>       * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>):
> Rename into ...
>       (@mve_vcmp<mve_cmp_op>q_n_<mode>): ... this.
>       (mve_vcmpeqq_m_f<mode>, mve_vcmpgeq_m_f<mode>)
>       (mve_vcmpgtq_m_f<mode>, mve_vcmpleq_m_f<mode>)
>       (mve_vcmpltq_m_f<mode>, mve_vcmpneq_m_f<mode>): Merge into
> ...
>       (@mve_vcmp<mve_cmp_op1>q_m_f<mode>): ... this.
>       (mve_vcmpcsq_m_u<mode>, mve_vcmpeqq_m_<supf><mode>)
>       (mve_vcmpgeq_m_s<mode>, mve_vcmpgtq_m_s<mode>)
>       (mve_vcmphiq_m_u<mode>, mve_vcmpleq_m_s<mode>)
>       (mve_vcmpltq_m_s<mode>, mve_vcmpneq_m_<supf><mode>):
> Merge into
>       ...
>       (@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>): ... this.
>       (mve_vcmpcsq_m_n_u<mode>,
> mve_vcmpeqq_m_n_<supf><mode>)
>       (mve_vcmpgeq_m_n_s<mode>, mve_vcmpgtq_m_n_s<mode>)
>       (mve_vcmphiq_m_n_u<mode>, mve_vcmpleq_m_n_s<mode>)
>       (mve_vcmpltq_m_n_s<mode>, mve_vcmpneq_m_n_<supf><mode>):
> Merge
>       into ...
>       (@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>): ... this.
>       (mve_vcmpeqq_m_n_f<mode>, mve_vcmpgeq_m_n_f<mode>)
>       (mve_vcmpgtq_m_n_f<mode>, mve_vcmpleq_m_n_f<mode>)
>       (mve_vcmpltq_m_n_f<mode>, mve_vcmpneq_m_n_f<mode>):
> Merge into ...
>       (@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>): ... this.
> ---
>  gcc/config/arm/iterators.md | 108 ++++++++++
>  gcc/config/arm/mve.md       | 414 +++---------------------------------
>  2 files changed, 135 insertions(+), 387 deletions(-)
> 
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index 3c70fd7f56d..ef9fae0412b 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -583,6 +583,47 @@ (define_int_iterator MVE_FP_CREATE_ONLY [
>                    VCREATEQ_F
>                    ])
> 
> +;; MVE comparison iterators
> +(define_int_iterator MVE_CMP_M [
> +                  VCMPCSQ_M_U
> +                  VCMPEQQ_M_S VCMPEQQ_M_U
> +                  VCMPGEQ_M_S
> +                  VCMPGTQ_M_S
> +                  VCMPHIQ_M_U
> +                  VCMPLEQ_M_S
> +                  VCMPLTQ_M_S
> +                  VCMPNEQ_M_S VCMPNEQ_M_U
> +                  ])
> +
> +(define_int_iterator MVE_CMP_M_F [
> +                  VCMPEQQ_M_F
> +                  VCMPGEQ_M_F
> +                  VCMPGTQ_M_F
> +                  VCMPLEQ_M_F
> +                  VCMPLTQ_M_F
> +                  VCMPNEQ_M_F
> +                  ])
> +
> +(define_int_iterator MVE_CMP_M_N [
> +                  VCMPCSQ_M_N_U
> +                  VCMPEQQ_M_N_S VCMPEQQ_M_N_U
> +                  VCMPGEQ_M_N_S
> +                  VCMPGTQ_M_N_S
> +                  VCMPHIQ_M_N_U
> +                  VCMPLEQ_M_N_S
> +                  VCMPLTQ_M_N_S
> +                  VCMPNEQ_M_N_S VCMPNEQ_M_N_U
> +                  ])
> +
> +(define_int_iterator MVE_CMP_M_N_F [
> +                  VCMPEQQ_M_N_F
> +                  VCMPGEQ_M_N_F
> +                  VCMPGTQ_M_N_F
> +                  VCMPLEQ_M_N_F
> +                  VCMPLTQ_M_N_F
> +                  VCMPNEQ_M_N_F
> +                  ])
> +
>  (define_int_iterator MVE_VMAXVQ_VMINVQ [
>                    VMAXAVQ_S
>                    VMAXVQ_S VMAXVQ_U
> @@ -655,6 +696,37 @@ (define_code_attr mve_addsubmul [
>                (plus "vadd")
>                ])
> 
> +(define_int_attr mve_cmp_op1 [
> +              (VCMPCSQ_M_U "cs")
> +              (VCMPEQQ_M_S "eq") (VCMPEQQ_M_U "eq")
> +              (VCMPGEQ_M_S "ge")
> +              (VCMPGTQ_M_S "gt")
> +              (VCMPHIQ_M_U "hi")
> +              (VCMPLEQ_M_S "le")
> +              (VCMPLTQ_M_S "lt")
> +              (VCMPNEQ_M_S "ne") (VCMPNEQ_M_U "ne")
> +              (VCMPEQQ_M_F "eq")
> +              (VCMPGEQ_M_F "ge")
> +              (VCMPGTQ_M_F "gt")
> +              (VCMPLEQ_M_F "le")
> +              (VCMPLTQ_M_F "lt")
> +              (VCMPNEQ_M_F "ne")
> +              (VCMPCSQ_M_N_U "cs")
> +              (VCMPEQQ_M_N_S "eq") (VCMPEQQ_M_N_U "eq")
> +              (VCMPGEQ_M_N_S "ge")
> +              (VCMPGTQ_M_N_S "gt")
> +              (VCMPHIQ_M_N_U "hi")
> +              (VCMPLEQ_M_N_S "le")
> +              (VCMPLTQ_M_N_S "lt")
> +              (VCMPNEQ_M_N_S "ne") (VCMPNEQ_M_N_U "ne")
> +              (VCMPEQQ_M_N_F "eq")
> +              (VCMPGEQ_M_N_F "ge")
> +              (VCMPGTQ_M_N_F "gt")
> +              (VCMPLEQ_M_N_F "le")
> +              (VCMPLTQ_M_N_F "lt")
> +              (VCMPNEQ_M_N_F "ne")
> +              ])
> +
>  (define_int_attr mve_insn [
>                (VABDQ_M_S "vabd") (VABDQ_M_U "vabd") (VABDQ_M_F
> "vabd")
>                (VABDQ_S "vabd") (VABDQ_U "vabd") (VABDQ_F "vabd")
> @@ -836,6 +908,26 @@ (define_int_attr isu    [
>                (VCLSQ_M_S "s")
>                (VCLZQ_M_S "i")
>                (VCLZQ_M_U "i")
> +              (VCMPCSQ_M_N_U "u")
> +              (VCMPCSQ_M_U "u")
> +              (VCMPEQQ_M_N_S "i")
> +              (VCMPEQQ_M_N_U "i")
> +              (VCMPEQQ_M_S "i")
> +              (VCMPEQQ_M_U "i")
> +              (VCMPGEQ_M_N_S "s")
> +              (VCMPGEQ_M_S "s")
> +              (VCMPGTQ_M_N_S "s")
> +              (VCMPGTQ_M_S "s")
> +              (VCMPHIQ_M_N_U "u")
> +              (VCMPHIQ_M_U "u")
> +              (VCMPLEQ_M_N_S "s")
> +              (VCMPLEQ_M_S "s")
> +              (VCMPLTQ_M_N_S "s")
> +              (VCMPLTQ_M_S "s")
> +              (VCMPNEQ_M_N_S "i")
> +              (VCMPNEQ_M_N_U "i")
> +              (VCMPNEQ_M_S "i")
> +              (VCMPNEQ_M_U "i")
>                (VMOVNBQ_M_S "i") (VMOVNBQ_M_U "i")
>                (VMOVNBQ_S "i") (VMOVNBQ_U "i")
>                (VMOVNTQ_M_S "i") (VMOVNTQ_M_U "i")
> @@ -2082,6 +2174,22 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s")
> (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
>                      (VMAXAQ_M_S "s")
>                      (VMINAQ_S "s")
>                      (VMINAQ_M_S "s")
> +                    (VCMPCSQ_M_N_U "u")
> +                    (VCMPCSQ_M_U "u")
> +                    (VCMPEQQ_M_N_S "s") (VCMPEQQ_M_N_U "u")
> +                    (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u")
> +                    (VCMPGEQ_M_N_S "s")
> +                    (VCMPGEQ_M_S "s")
> +                    (VCMPGTQ_M_N_S "s")
> +                    (VCMPGTQ_M_S "s")
> +                    (VCMPHIQ_M_N_U "u")
> +                    (VCMPHIQ_M_U "u")
> +                    (VCMPLEQ_M_N_S "s")
> +                    (VCMPLEQ_M_S "s")
> +                    (VCMPLTQ_M_N_S "s")
> +                    (VCMPLTQ_M_S "s")
> +                    (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u")
> +                    (VCMPNEQ_M_S "s") (VCMPNEQ_M_U "u")
>                      ])
> 
>  ;; Both kinds of return insn.
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 45bca6d6215..191d1268ad6 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -695,7 +695,7 @@ (define_insn
> "@mve_vcmp<mve_cmp_op>q_<mode>"
>  ;;
>  ;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_,
> vcmpleq_n_, vcmpltq_n_, vcmpneq_n_])
>  ;;
> -(define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>"
> +(define_insn "@mve_vcmp<mve_cmp_op>q_n_<mode>"
>    [
>     (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
>       (MVE_COMPARISONS:<MVE_VPRED>
> @@ -1766,18 +1766,23 @@ (define_insn "mve_vrmlaldavhq_<supf>v4si"
>  ])
> 
>  ;;
> -;; [vcmpeqq_m_f])
> +;; [vcmpeqq_m_f]
> +;; [vcmpgeq_m_f]
> +;; [vcmpgtq_m_f]
> +;; [vcmpleq_m_f]
> +;; [vcmpltq_m_f]
> +;; [vcmpneq_m_f]
>  ;;
> -(define_insn "mve_vcmpeqq_m_f<mode>"
> +(define_insn "@mve_vcmp<mve_cmp_op1>q_m_f<mode>"
>    [
>     (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
>       (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
>                   (match_operand:MVE_0 2 "s_register_operand" "w")
>                   (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
> "Up")]
> -      VCMPEQQ_M_F))
> +      MVE_CMP_M_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        eq, %q1, %q2"
> +  "vpst\;vcmpt.f%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %q2"
>    [(set_attr "type" "mve_move")
>     (set_attr "length""8")])
>  ;;
> @@ -1954,257 +1959,47 @@ (define_insn "mve_vaddvaq_p_<supf><mode>"
> 
>  ;;
>  ;; [vcmpcsq_m_n_u])
> -;;
> -(define_insn "mve_vcmpcsq_m_n_u<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPCSQ_M_N_U))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.u%#<V_sz_elem>        cs, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpcsq_m_u])
> -;;
> -(define_insn "mve_vcmpcsq_m_u<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_2 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPCSQ_M_U))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.u%#<V_sz_elem>        cs, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s])
> -;;
> -(define_insn "mve_vcmpeqq_m_n_<supf><mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPEQQ_M_N))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.i%#<V_sz_elem>        eq, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpeqq_m_u, vcmpeqq_m_s])
> -;;
> -(define_insn "mve_vcmpeqq_m_<supf><mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_2 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPEQQ_M))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.i%#<V_sz_elem>        eq, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpgeq_m_n_s])
> -;;
> -(define_insn "mve_vcmpgeq_m_n_s<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPGEQ_M_N_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.s%#<V_sz_elem>        ge, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpgeq_m_s])
> -;;
> -(define_insn "mve_vcmpgeq_m_s<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_2 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPGEQ_M_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.s%#<V_sz_elem>        ge, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpgtq_m_n_s])
> -;;
> -(define_insn "mve_vcmpgtq_m_n_s<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPGTQ_M_N_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.s%#<V_sz_elem>        gt, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpgtq_m_s])
> -;;
> -(define_insn "mve_vcmpgtq_m_s<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_2 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPGTQ_M_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.s%#<V_sz_elem>        gt, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmphiq_m_n_u])
> -;;
> -(define_insn "mve_vcmphiq_m_n_u<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPHIQ_M_N_U))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.u%#<V_sz_elem>        hi, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmphiq_m_u])
> -;;
> -(define_insn "mve_vcmphiq_m_u<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_2 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPHIQ_M_U))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.u%#<V_sz_elem>        hi, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpleq_m_n_s])
> -;;
> -(define_insn "mve_vcmpleq_m_n_s<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPLEQ_M_N_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.s%#<V_sz_elem>        le, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpleq_m_s])
> -;;
> -(define_insn "mve_vcmpleq_m_s<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_2 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPLEQ_M_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.s%#<V_sz_elem>        le, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpltq_m_n_s])
> -;;
> -(define_insn "mve_vcmpltq_m_n_s<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPLTQ_M_N_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.s%#<V_sz_elem>        lt, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpltq_m_s])
> -;;
> -(define_insn "mve_vcmpltq_m_s<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_2 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPLTQ_M_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.s%#<V_sz_elem>        lt, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpneq_m_n_u, vcmpneq_m_n_s])
>  ;;
> -(define_insn "mve_vcmpneq_m_n_<supf><mode>"
> +(define_insn "@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>"
>    [
>     (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
>       (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
>                      (match_operand:<V_elem> 2 "s_register_operand" "r")
>                      (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPNEQ_M_N))
> +      MVE_CMP_M_N))
>    ]
>    "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.i%#<V_sz_elem>        ne, %q1, %2"
> +  "vpst\;vcmpt.<isu>%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %2"
>    [(set_attr "type" "mve_move")
>     (set_attr "length""8")])
> 
>  ;;
> -;; [vcmpneq_m_s, vcmpneq_m_u])
> +;; [vcmpcsq_m_u]
> +;; [vcmpeqq_m_u, vcmpeqq_m_s]
> +;; [vcmpgeq_m_s]
> +;; [vcmpgtq_m_s]
> +;; [vcmphiq_m_u]
> +;; [vcmpleq_m_s]
> +;; [vcmpltq_m_s]
> +;; [vcmpneq_m_s, vcmpneq_m_u]
>  ;;
> -(define_insn "mve_vcmpneq_m_<supf><mode>"
> +(define_insn "@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>"
>    [
>     (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
>       (unspec:<MVE_VPRED> [(match_operand:MVE_2 1
> "s_register_operand" "w")
>                      (match_operand:MVE_2 2 "s_register_operand" "w")
>                      (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPNEQ_M))
> +      MVE_CMP_M))
>    ]
>    "TARGET_HAVE_MVE"
> -  "vpst\;vcmpt.i%#<V_sz_elem>        ne, %q1, %q2"
> +  "vpst\;vcmpt.<isu>%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %q2"
>    [(set_attr "type" "mve_move")
>     (set_attr "length""8")])
> 
> @@ -2785,177 +2580,22 @@ (define_insn "mve_vcmlaq<mve_rot><mode>"
> 
>  ;;
>  ;; [vcmpeqq_m_n_f])
> -;;
> -(define_insn "mve_vcmpeqq_m_n_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPEQQ_M_N_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        eq, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpgeq_m_f])
> -;;
> -(define_insn "mve_vcmpgeq_m_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_0 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPGEQ_M_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        ge, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpgeq_m_n_f])
> -;;
> -(define_insn "mve_vcmpgeq_m_n_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPGEQ_M_N_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        ge, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpgtq_m_f])
> -;;
> -(define_insn "mve_vcmpgtq_m_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_0 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPGTQ_M_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        gt, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpgtq_m_n_f])
> -;;
> -(define_insn "mve_vcmpgtq_m_n_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPGTQ_M_N_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        gt, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpleq_m_f])
> -;;
> -(define_insn "mve_vcmpleq_m_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_0 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPLEQ_M_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        le, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpleq_m_n_f])
> -;;
> -(define_insn "mve_vcmpleq_m_n_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPLEQ_M_N_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        le, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpltq_m_f])
> -;;
> -(define_insn "mve_vcmpltq_m_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_0 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPLTQ_M_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        lt, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpltq_m_n_f])
> -;;
> -(define_insn "mve_vcmpltq_m_n_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:<V_elem> 2 "s_register_operand" "r")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPLTQ_M_N_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        lt, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
> -;; [vcmpneq_m_f])
> -;;
> -(define_insn "mve_vcmpneq_m_f<mode>"
> -  [
> -   (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
> -     (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
> -                    (match_operand:MVE_0 2 "s_register_operand" "w")
> -                    (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPNEQ_M_F))
> -  ]
> -  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        ne, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
> -;;
>  ;; [vcmpneq_m_n_f])
>  ;;
> -(define_insn "mve_vcmpneq_m_n_f<mode>"
> +(define_insn "@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>"
>    [
>     (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
>       (unspec:<MVE_VPRED> [(match_operand:MVE_0 1
> "s_register_operand" "w")
>                      (match_operand:<V_elem> 2 "s_register_operand" "r")
>                      (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -      VCMPNEQ_M_N_F))
> +      MVE_CMP_M_N_F))
>    ]
>    "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> -  "vpst\;vcmpt.f%#<V_sz_elem>        ne, %q1, %2"
> +  "vpst\;vcmpt.f%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %2"
>    [(set_attr "type" "mve_move")
>     (set_attr "length""8")])
> 
> --
> 2.34.1