ewise.
(neon_vld4): Likewise.
(neon_vld4qa): Likewise.
(neon_vld4qb): Likewise.
(neon_vld4_dup): Likewise.
(neon_vld2_dupv8bf): New.
(neon_vld3_dupv8bf): Likewise.
(neon_vld4_dupv8bf): Likewise.
Kyrill
Thanks,
Delia
On 3/4/20 5:20 PM, Kyrill Tkachov wrote:
Hi Delia,
On 3
Hi all,
The two affected SVE2 patterns in this patch output a movprfx'ed
instruction in their second alternative
but don't set the "movprfx" attribute, which will result in the wrong
instruction length being assumed by the midend.
This patch fixes that in the same way as the other SVE pattern
Hi Jakub,
On 3/11/20 7:22 AM, Jakub Jelinek wrote:
Hi!
abs_hwi asserts that the argument is not HOST_WIDE_INT_MIN and as the
(invalid) testcase shows, the function can be called with such an offset.
The following patch is IMHO minimal fix, absu_hwi unlike abs_hwi
allows even
that value and wi
onfig/aarch64/atomics.md (aarch64_atomic__lse):
The scratch register need not be early-clobber. Document the reason
why we cannot use ST.
From-SVN: r265703
On 2/27/20, 12:06 PM, "Kyrill Tkachov" wrote:
Hi Sebastian,
On 2/27/20 4:53 PM, Pop, Seba
Hi Delia,
On 3/11/20 5:49 PM, Delia Burduv wrote:
This patch fixes a bug introduced by my earlier patch (
https://gcc.gnu.org/pipermail/gcc-patches/2020-March/541680.html ).
It introduces a new scalar builtin type that was missing in the original
patch.
Bootstrapped cleanly on arm-none-linux-gn
On 3/11/20 5:59 PM, Kyrill Tkachov wrote:
Hi Delia,
On 3/11/20 5:49 PM, Delia Burduv wrote:
This patch fixes a bug introduced by my earlier patch (
https://gcc.gnu.org/pipermail/gcc-patches/2020-March/541680.html ).
It introduces a new scalar builtin type that was missing in the original
Hi Srinath,
On 3/10/20 6:19 PM, Srinath Parvathaneni wrote:
Hello Kyrill,
This patch addresses all the comments in patch version v2.
(version v2)
https://gcc.gnu.org/pipermail/gcc-patches/2020-February/540415.html
Hello,
This patch creates the required framework for MVE ACLE intrinsic
Hi Srinath,
On 3/10/20 6:19 PM, Srinath Parvathaneni wrote:
Hello Kyrill,
This patch addresses all the comments in patch version v2.
(version v2)
https://gcc.gnu.org/pipermail/gcc-patches/2020-February/540416.html
Hello,
This patch is part of MVE ACLE intrinsics framework.
This patch
Hi Srinath,
On 3/10/20 6:19 PM, Srinath Parvathaneni wrote:
Hello Kyrill,
This patch addresses all the comments in patch version v2.
(version v2)
https://gcc.gnu.org/pipermail/gcc-patches/2020-February/540417.html
Hello,
This patch is part of MVE ACLE intrinsics framework.
The patch
Hi Matt,
On 9/24/19 5:04 AM, Matt Turner wrote:
When -march=native is passed to host_detect_local_cpu to the backend,
it overrides all command lines after it. That means
$ gcc -march=native -march=armv8-a
is treated as
$ gcc -march=armv8-a -march=native
Prune joined switches with Negative a
Hi all,
On 9/10/19 1:34 PM, Stam Markianos-Wright wrote:
Hi all,
This is a minor patch that fixes the entry for the fp16fml feature in
GCC's aarch64-option-extensions.def.
As can be seen in the Linux sources here
https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/cpuinfo.c#L69
Hi all,
On 8/22/19 10:16 AM, Kyrill Tkachov wrote:
Hi all,
The optimisation to optimise:
typedef unsigned long long u64;
void bar(u64 *x)
{
*x = 0xabcdef10abcdef10;
}
from:
mov x1, 61200
movk x1, 0xabcd, lsl 16
movk x1, 0xef10, lsl 32
Hi all,
This patch is part of a series to implement the SIMD32 ACLE intrinsics [1].
The interesting parts implementation-wise involve adding support for
setting and reading
the Q bit for saturation and the GE-bits for the packed SIMD instructions.
That will come in a later patch.
For now, this
Hi all,
This patch implements some more SIMD32, but these ones have a DImode
result+addend.
Apart from that there's nothing too exciting about them.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Will commit to trunk within the next day or two.
Thanks,
Kyrill
2019-09-25 Kyrylo Tkacho
On 9/24/19 7:47 PM, Matt Turner wrote:
When -march=native is passed to host_detect_local_cpu to the backend,
it overrides all command lines after it. That means
$ gcc -march=native -march=armv8-a
is treated as
$ gcc -march=armv8-a -march=native
Prune joined switches with Negative and Rejec
Hi all,
On 9/3/19 9:35 AM, Shaokun Zhang wrote:
The DCache clean & ICache invalidation requirements for instructions
to be data coherence are discoverable through new fields in CTR_EL0.
Let's support the two bits if they are enabled, the CPU core will
not execute the unnecessary DCache clean or
Hi all,
On 2/6/19 1:52 PM, Kyrill Tkachov wrote:
[resending with patch compressed]
Hi all,
We're somewhat inconsistent in arm_neon.h when it comes to using the
implementation namespace for local
identifiers. This means things like:
#define hash_abcd 0
#define hash_e 1
#define wk 2
#in
On 8/22/19 4:53 PM, Kyrill Tkachov wrote:
Hi all,
We currently have a nasty error when trying to use the __crc*
intrinsics with an -mfloat-abi=hard.
That is because the target pragma guarding them uses armv8-a+crc that
does not include fp by default.
So we get errors like:
error: '-m
On 9/25/19 10:24 PM, James Greenhalgh wrote:
On Tue, Sep 24, 2019 at 02:40:20PM +0100, Kyrill Tkachov wrote:
Hi all,
On 8/22/19 10:16 AM, Kyrill Tkachov wrote:
Hi all,
The optimisation to optimise:
typedef unsigned long long u64;
void bar(u64 *x)
{
*x
On 9/26/19 8:02 AM, Ramana Radhakrishnan wrote:
Hi,
I'm pleased to announce that the GCC steering committee has appointed
Kyrylo Tkachov and Richard Sandiford as AArch64 maintainers.
Please join me in congratulating them both on their additional roles
in the community. Kyrill / Richard, please
On 9/25/19 12:10 PM, Kyrill Tkachov wrote:
On 9/24/19 7:47 PM, Matt Turner wrote:
> When -march=native is passed to host_detect_local_cpu to the backend,
> it overrides all command lines after it. That means
>
> $ gcc -march=native -march=armv8-a
>
> is treated as
>
&
On 9/26/19 4:12 PM, Jeff Law wrote:
On 9/26/19 12:49 AM, Jakub Jelinek wrote:
> On Wed, Sep 25, 2019 at 10:06:13PM -0600, Jeff Law wrote:
>> (insn 13 12 14 2 (set (reg:SI 124)
>> (const_int -939524096 [0xc800])) "j.c":10:54 161
>> {*arm_movsi_insn}
>> (nil))
>>
>> (insn
On 9/26/19 4:32 PM, Jeff Law wrote:
On 9/26/19 9:14 AM, Kyrill Tkachov wrote:
On 9/26/19 4:12 PM, Jeff Law wrote:
On 9/26/19 12:49 AM, Jakub Jelinek wrote:
On Wed, Sep 25, 2019 at 10:06:13PM -0600, Jeff Law wrote:
(insn 13 12 14 2 (set (reg:SI 124)
(const_int -939524096
On 9/27/19 4:17 PM, Richard Earnshaw (lists) wrote:
On 26/09/2019 07:49, Jakub Jelinek wrote:
> On Wed, Sep 25, 2019 at 10:06:13PM -0600, Jeff Law wrote:
>> (insn 13 12 14 2 (set (reg:SI 124)
>> (const_int -939524096 [0xc800])) "j.c":10:54 161
>> {*arm_movsi_insn}
>>
Hi Richard,
On 10/3/19 1:45 PM, Richard Sandiford wrote:
Noticed while debugging the arm bootstrap failure.
Tested on arm-linux-gnueabihf. OK to install?
Richard
2019-10-03 Richard Sandiford
gcc/
* config/arm/arm.c (arm_print_value): Use real_to_decimal
to print CONST_DOU
Hopefully an obvious amendment.
Will test out the new git repo soon!
Thanks,
Kyrill
commit ddf1524244ac30ab3473d0df6d8e76d5c9a42276
Author: Kyrylo Tkachov
Date: Wed Oct 9 16:15:00 2019 +0100
[gcccmission.html] Replace cvs with version control
diff --git a/htdocs/gccmission.html b/htdo
On 10/10/19 10:18 AM, Richard Sandiford wrote:
Kyrill Tkachov writes:
Hopefully an obvious amendment.
Will test out the new git repo soon!
Thanks,
Kyrill
commit ddf1524244ac30ab3473d0df6d8e76d5c9a42276
Author: Kyrylo Tkachov
Date: Wed Oct 9 16:15:00 2019 +0100
[gcccmission.html
Hi Kugan,
On 10/10/19 2:55 AM, Kugan Vivekanandarajah wrote:
As reported in Linaro bug report
(https://bugs.linaro.org/show_bug.cgi?id=4636 ; there is no
reproducible testcase provided), for some applications, we see
(insn 126 125 127 9 (set (reg:DF 189)
(fma:DF (reg:DF 126 [ _74 ])
Hi Andre,
On 10/10/19 11:28 AM, Andre Vieira (lists) wrote:
Hi Kyrill,
On 10/10/2019 10:53, Kyrill Tkachov wrote:
>
>
> I'm a bit surprised that TARGET_FMA (which just checks isa_bit_vfpv4)
> doesn't imply TARGET_VFP_DOUBLE.
> Can one really have a VFPV4 single-pre
On 10/10/19 7:37 PM, Gerald Pfeifer wrote:
On Thu, 10 Oct 2019, Kyrill Tkachov wrote:
Not sure whether this is supposed to be a living document or just a
record of what the mission statement was when egcs became GCC. The
date at the top is still 1999-04-22.
Ah, I hadn't considered that.
Hi Richard,
On 10/15/19 8:17 AM, Richard Biener wrote:
This makes allow-store-data-races adjustable per function by making it
a regular option rather than a --param.
Note that the kernel has --param=allow-store-data-races=0 in its build
flags.
I guess that will break unless they rename it
On 10/15/19 5:29 PM, Gerald Pfeifer wrote:
On Mon, 14 Oct 2019, Kyrill Tkachov wrote:
Surely would be fine with me.
I see, thanks. Here's a proposed patch then.
My previous mail was meant to pre-approve your patch. ;-)
Right, I meant to take it as such, but got distracted wit
Hi all,
This patch implements the recently published[1] __rndr and __rndrrs
intrinsics used to access the RNG in Armv8.5-A.
The __rndrrs intrinsics can be used to reseed the generator too.
They are guarded by the __ARM_FEATURE_RNG feature macro.
A quirk with these intrinsics is that they store
On 11/14/19 10:07 AM, Richard Henderson wrote:
The existing definition using register class CC_REG does not
work because CC_REGNUM does not support normal modes, and so
fails to match register_operand. Use a non-register constraint
and the cc_register predicate instead.
* config/arm/c
Hi Richard,
On 11/14/19 10:07 AM, Richard Henderson wrote:
I've put the implementation into config/arm/aarch-common.c, so
that it can be shared between the two targets. This required
a little bit of cleanup to the CC modes and constraints to get
the two targets to match up.
Changes for v2:
*
Hi Prathamesh,
On 11/14/19 6:47 PM, Prathamesh Kulkarni wrote:
Hi,
As suggested in PR, the attached patch falls back to distributing
rshift over plus_expr instead of fallback widening -> arithmetic ->
narrowing sequence, if target support is not available.
Bootstrap+tested on x86_64-unknown-linu
On 11/18/19 12:54 PM, Tamar Christina wrote:
OK to backport to GCC 9?
Yes.
Thanks,
Kyrill
Thanks,
Tamar
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org
On Behalf Of Kyrill Tkachov
Sent: Tuesday, September 24, 2019 14:32
To: Stam Markianos-Wright ; gcc-
patc
Hi Dennis,
On 11/12/19 5:32 PM, Dennis Zhang wrote:
Hi Kyrill,
On 12/11/2019 15:57, Kyrill Tkachov wrote:
On 11/12/19 3:50 PM, Dennis Zhang wrote:
Hi Kyrill,
On 12/11/2019 09:40, Kyrill Tkachov wrote:
Hi Dennis,
On 11/7/19 1:48 PM, Dennis Zhang wrote:
Hi Kyrill,
I have rebased the patch
On 11/19/19 1:41 PM, Dennis Zhang wrote:
Hi Kyrill,
On 19/11/2019 11:21, Kyrill Tkachov wrote:
Hi Dennis,
On 11/12/19 5:32 PM, Dennis Zhang wrote:
Hi Kyrill,
On 12/11/2019 15:57, Kyrill Tkachov wrote:
On 11/12/19 3:50 PM, Dennis Zhang wrote:
Hi Kyrill,
On 12/11/2019 09:40, Kyrill
Hi Srinath,
On 11/21/19 4:32 PM, Srinath Parvathaneni wrote:
Hello,
This patch fixes arm acle testcase crc_hf_1.c by modifying the
compiler options directive.
Regression tested on arm-none-eabi and found no regressions.
Ok for trunk? If ok, please commit on my behalf, I don't have the
comm
Hi Wilco,
On 11/19/19 3:11 PM, Wilco Dijkstra wrote:
ping
Various CPUs have max_cond_insns set to 5 due to historical reasons.
Benchmarking shows that max_cond_insns=2 is fastest on modern Cortex-A
cores, so change it to 2 for all Cortex-A cores.
Hmm, I'm not too confident on that. I'd suppor
On 12/2/19 12:14 PM, Wilco Dijkstra wrote:
Add support for Cortex-A76, Ares and Neoverse N1 cpu names in GCC8 branch.
2019-11-29 Wilco Dijkstra
* config/aarch64/aarch64-cores.def (ares): Define.
(cortex-a76): Likewise.
(neoverse-n1): Likewise.
* config/aarch
On 12/3/19 1:45 PM, Wilco Dijkstra wrote:
Hi,
Part 2, split off from
https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00399.html
To enable cores to use the correct max_cond_insns setting, use the
core-specific
tuning when a CPU/tune is selected unless -mrestrict-it is explicitly set.
On Cor
On 31/07/18 22:48, James Greenhalgh wrote:
On Fri, Jul 20, 2018 at 04:37:34AM -0500, Vlad Lazar wrote:
> Hi,
>
> The patch adds implementations for the NEON intrinsics vabsd_s64 and
vnegd_s64.
>
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ihi0073/latest/ar
Hi Steve,
On 31/07/18 23:24, Steve Ellcey wrote:
Here is a new version of my patch to support the Aarch64 SIMD ABI [1]
in GCC. I think this is complete enought to be considered for check
in. I wrote a few new tests and put them in a new gcc.target/torture
directory so they would be run with mu
Hi Siddhesh,
On 02/08/18 11:23, Siddhesh Poyarekar wrote:
There was a typo in the pipeline description where DUP was assigned to
the vector pipes for quad mode ops when it really only uses the VTOG
pipes. Fixing this does not show any noticeable difference in
performance (there's a very small b
Hi Kai,
On 13/08/18 17:48, Kai Tietz wrote:
I repost updated patch containing ChangeLog entry.
Regards,
Kai
I think I understand what this patch does, please correct me if I'm wrong.
You model the processors micro-ops and some A64 instructions use multiple
micro-ops.
This is what the falkor_
On 15/08/18 09:21, Tamar Christina wrote:
Hi All,
I'd like to ask for permissions to backport of this patch to GCC 8?
Ok. Please bundle the testcase in the backport as well.
Thanks,
Kyrill
Thanks,
Tamar
-Original Message-
From: Kyrill Tkachov
Sent: Tuesday, July 31, 2018
Hi Tamar,
On 26/07/18 12:01, Tamar Christina wrote:
Hi Thomas,
> -Original Message-
> From: Thomas Preudhomme
> Sent: Thursday, July 26, 2018 09:29
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Ramana Radhakrishnan
> ; Richard Earnshaw
> ; ni...@redhat.com; Kyrylo Tkachov
Hi Szabolcs,
On 17/08/18 18:18, Szabolcs Nagy wrote:
On 15/08/18 16:51, Martin Sebor wrote:
> On 08/15/2018 04:28 AM, James Greenhalgh wrote:
>> On Tue, Aug 14, 2018 at 09:34:08PM -0500, Martin Sebor wrote:
>>> On 08/14/2018 09:24 AM, Martin Sebor wrote:
On 08/14/2018 09:08 AM, Martin Sebor
Hi all,
This patch aims to optimise sequences involving uses of 1.0 / sqrt (a) under
-freciprocal-math and -funsafe-math-optimizations.
In particular consider:
x = 1.0 / sqrt (a);
r1 = x * x; // same as 1.0 / a
r2 = a * x; // same as sqrt (a)
If x, r1 and r2 are all used further on in the cod
Hi all,
On 22/08/18 15:57, Janne Blomqvist wrote:
On Wed, Aug 22, 2018 at 4:16 PM, Szabolcs Nagy
wrote:
> gfortran now always uses MAX_EXPR/MIN_EXPR for MAX/MIN intrinsics, so the
> AArch64 specific FMAX/FMIN tests are no longer valid.
>
> 2018-08-22 Szabolcs Nagy
>
> * gfortran.dg/m
Hi Richard,
On 23/08/18 11:13, Richard Sandiford wrote:
Kyrill Tkachov writes:
Hi all,
This patch aims to optimise sequences involving uses of 1.0 / sqrt (a) under
-freciprocal-math and -funsafe-math-optimizations.
In particular consider:
x = 1.0 / sqrt (a);
r1 = x * x; // same as 1.0
Hi all,
On 28/08/18 23:15, James Greenhalgh wrote:
On Fri, Aug 03, 2018 at 11:28:08AM -0500, Matthew Malcomson wrote:
On 02/08/18 20:18, James Greenhalgh wrote:
On Tue, Jul 31, 2018 at 04:53:19AM -0500, Matthew Malcomson wrote:
Fixing the ilp32 issue that Christophe found.
The existing testc
Hi Christophe,
On 13/07/18 17:10, christophe.l...@st.com wrote:
From: Christophe Lyon
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/
* config/arm/arm.opt: Add -mfdpic option.
Change-Id: Ie5c4ed7434488933de6133186da09cd3ea1291a7
diff --git a/gcc/config/arm/arm.opt
Hi Christophe,
On 13/07/18 17:10, christophe.l...@st.com wrote:
From: Christophe Lyon
The FDPIC register is hard-coded to r9, as defined in the ABI.
We have to disable tailcall optimizations if we don't know if the
target function is in the same module. If not, we have to set r9 to
the value
On 13/07/18 17:10, christophe.l...@st.com wrote:
From: Christophe Lyon
The new arm-uclinuxfdpiceabi target behaves pretty much like
arm-linux-gnueabi. In order the enable the same set of features, we
have to update several configure scripts that generally match targets
like *-*-linux*: in mos
On 13/07/18 17:11, christophe.l...@st.com wrote:
From: Christophe Lyon
The main difference with existing support is that function addresses
are function descriptor addresses instead. This means that all code
dealing with function pointers now has to cope with function
descriptors instead.
Fo
Hi Christophe,
On 13/07/18 17:11, christophe.l...@st.com wrote:
From: Christophe Lyon
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/
* config/arm/arm.c (arm_compute_save_reg0_reg12_mask): Handle
FDPIC.
(thumb1_compute_save_core_reg_mask): Likewise.
Hi Christophe,
On 13/07/18 17:11, christophe.l...@st.com wrote:
From: Christophe Lyon
In FDPIC mode, the trampoline generated to support pointers to nested
functions looks like:
.word trampoline address
.word trampoline GOT address
ldrr12, [pc, #8]
Ping.
https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01496.html
Thanks,
Kyrill
On 23/08/18 18:09, Kyrill Tkachov wrote:
Hi Richard,
On 23/08/18 11:13, Richard Sandiford wrote:
Kyrill Tkachov writes:
Hi all,
This patch aims to optimise sequences involving uses of 1.0 / sqrt (a) under
Hi all,
I'm committing this as obvious.
Thanks,
Kyrill
2018-08-31 Kyrylo Tkachov
* ipa-inline.c (can_inline_edge_by_limits_p): Fix typos in comment.
diff --git a/gcc/ipa-inline.c b/gcc/ipa-inline.c
index a84d1d9ad3e45935eff51f00b8f6b5058a691c9e..025788522fbe602e1d190a30ccea006b9ab053c5
On 30/08/18 16:53, Sam Tebbs wrote:
On 08/28/2018 11:53 PM, James Greenhalgh wrote:
> Hm, I'm not very sure about the naming here; "left consecutive" isn't a
> common phrase to denote the mask you're looking for (exact_log2 (-i) != -1
> if I'm reading right), and is misleading 0x is '
On 31/08/18 16:27, Sam Tebbs wrote:
On 08/31/2018 11:59 AM, Kyrill Tkachov wrote:
>
> On 30/08/18 16:53, Sam Tebbs wrote:
>>
>>
>> On 08/28/2018 11:53 PM, James Greenhalgh wrote:
>> > Hm, I'm not very sure about the naming here; "left consecutive&q
Hi Steve,
On 20/08/18 18:37, Steve Ellcey wrote:
On Tue, 2018-08-07 at 12:15 -0500, Segher Boessenkool wrote:
> > +/* { dg-final { scan-assembler-not "\[ \t\]stp\tq\[01234567\]" } }
> > */
> That's [0-7] but maybe you find [01234567] more readable here.
Segher, I fixed all the issues you poin
Hi Richard,
On 31/08/18 12:07, Richard Biener wrote:
> On Thu, 30 Aug 2018, Kyrill Tkachov wrote:
>
>> Ping.
>>
>> https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01496.html
>>
>> Thanks,
>> Kyrill
>>
>> On 23/08/18 18:09, Kyrill Tkachov wro
On 04/09/18 15:31, Richard Biener wrote:
On Tue, 4 Sep 2018, Kyrill Tkachov wrote:
Hi Richard,
On 31/08/18 12:07, Richard Biener wrote:
On Thu, 30 Aug 2018, Kyrill Tkachov wrote:
Ping.
https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01496.html
Thanks,
Kyrill
On 23/08/18 18:09, Kyrill
Hi all,
Another vec_merge simplification that's missing is transforming:
(vec_merge (vec_duplicate x) (vec_concat (y) (z)) (const_int N))
into
(vec_concat x z) if N == 1 (0b01) or
(vec_concat y x) if N == 2 (0b10)
For the testcase in this patch on aarch64 this allows us to try matching during
c
Hi all,
Another vec_merge simplification that's missing from simplify-rtx.c is
transforming
a vec_merge of two vec_duplicates. For example:
(set (reg:V2DF 80)
(vec_merge:V2DF (vec_duplicate:V2DF (reg:DF 84))
(vec_duplicate:V2DF (reg:DF 81))
(const_int 2)))
Can be transformed
Hi all,
On top of the previous vec_merge simplifications [1] we can add this pattern to
perform
a store of a vec_concat of two 64-bit values in distinct registers as an STP.
This avoids constructing such a vector explicitly in a register and storing it
as
a Q register.
This way for the code in
On 02/05/17 16:37, Tamar Christina wrote:
Hi All,
This patch adjusts the cost model so that when both sdiv and udiv are possible
it prefers udiv over sdiv. This was done by making sdiv slightly more expensive
instead of making udiv cheaper to keep the baseline costs of a division the same
as be
: Kyrill Tkachov; GCC Patches
Cc: nd; Ramana Radhakrishnan; Richard Earnshaw; ni...@redhat.com
Subject: RE: [PATCH][GCC][ARM] Adjust costs so udiv is preferred over sdiv when
both are valid. [Patch (2/2)]
Hi Kyrill,
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index
On 12/06/17 14:53, James Greenhalgh wrote:
Hi,
In the AArch64 backend and scheduling models there is some confusion as to
what the load1/load2 etc. scheduling types refer to. This leads to us using
load1/load2 in two contexts - for a variety of 32-bit, 64-bit and 128-bit
loads in AArch32 and 12
On 13/06/17 11:12, Tamar Christina wrote:
Hi All,
This fixes the failing test gcc.target/arm/sdiv_costs_1.c by
requiring arm_arch_v8a_ok.
OK for trunk?
Ok.
Thanks,
Kyrill
gcc/testsuite/
2017-06-13 Tamar Christina
* gcc.target/arm/sdiv_costs_1.c:
Require arm_arch_v8a_o
Hi James,
On 12/06/17 14:57, James Greenhalgh wrote:
Hi,
PR71778 is an ICE when you pass a non-constant argument to an intrinsic
which requires a constant.
This ICE was introduced after we rewrote some of the builtin handling for
Neon intrinsics, the issue is that after throwing an error in
ar
On 16/06/17 10:07, James Greenhalgh wrote:
On Wed, Jun 14, 2017 at 11:21:30AM +0100, Kyrill Tkachov wrote:
<...>
That movv2di expander is the one in vec-common.md that ends up calling
neon_make_constant. I wonder why const0_rtx passed its predicate check
(that would require a V2
On 19/06/17 17:16, James Greenhalgh wrote:
On Fri, Jun 16, 2017 at 11:07:41AM +0100, Kyrill Tkachov wrote:
On 16/06/17 10:07, James Greenhalgh wrote:
On Wed, Jun 14, 2017 at 11:21:30AM +0100, Kyrill Tkachov wrote:
<...>
That movv2di expander is the one in vec-common.md that e
Hi Andrew,
On 20/06/17 06:06, Andrew Pinski wrote:
On Tue, Feb 28, 2017 at 4:29 AM, Kyrill Tkachov
wrote:
Hi all,
For the testcase in this patch we currently generate:
foo:
mov w1, 0
ldaxr w2, [x0]
cmp w2, 3
bne .L2
stxrw3, w1
Hi all,
As Andrew pointed out, the patch at r248921
(https://gcc.gnu.org/ml/gcc-patches/2017-02/msg01648.html)
that allowed const0_rtx as an argument to the compare-exchange
patterns was incomplete. It didn't extend the TARGET_LSE patterns as well,
causing the expander to generate
an invalid pa
Hi Thomas,
On 23/06/17 16:48, Thomas Preudhomme wrote:
Hi Kyrill,
On 10/04/17 15:01, Kyrill Tkachov wrote:
Hi Prakhar,
Sorry for the delay,
On 22/03/17 10:46, Prakhar Bahuguna wrote:
The GCC documentation in section 6.60.8 ARM Floating Point Status and Control
Intrinsics states that the
Hi Christophe,
On 07/06/17 10:13, Christophe Lyon wrote:
Hi,
On 2 June 2017 at 16:19, Christophe Lyon wrote:
Hi,
I have recently updated the dejagnu version I use for
cross-testing arm and aarch64 toolchains to 1.6+. One of the side
effects was mentioned by Jonathan in
https://gcc.gnu.org/m
Hi Michael,
On 23/06/17 21:44, Michael Collison wrote:
This patch cleans up warning messages due to unused variables and overly
complicated loop structures.
Okay for trunk?
Ok.
Thanks,
Kyrill
2017-03-30 Michael Collison
PR target/68535
* config/arm/arm.c (gen_ldm_seq):
Hi Thomas,
On 28/06/17 15:49, Thomas Preudhomme wrote:
On 20/06/17 13:44, Christophe Lyon wrote:
The results with a more recent trunk (r249356)) are here:
http://people.linaro.org/~christophe.lyon/cross-validation/gcc-test-patches/249356-consistent_neon_check.patch/report-build-info.html
Th
On 30/06/17 16:41, Thomas Preudhomme wrote:
Ping?
Best regards,
Thomas
On 28/06/17 12:35, Thomas Preudhomme wrote:
Ping?
Best regards,
Thomas
On 26/06/17 12:32, Thomas Preudhomme wrote:
Hi,
As raised by Christophe Lyon, fpscr.c FAILs because arm_fp_ok and arm_fp
are not defined in GCC 5
On 29/06/17 14:55, Thomas Preudhomme wrote:
Hi,
The driver is missing MIDR information for processors ARM Cortex-R7 and
Cortex-R8 to support -march/-mcpu/-mtune=native on the command line.
This patch adds the missing information.
ChangeLog entry is as follows:
*** gcc/ChangeLog ***
2017-01-3
Hi all,
While doing some unrelated work the gcc.target/aarch64/simd/vminmaxnm_1.c
testcase started failing for me.
Upon investigation it turns out that it breaks the C strict aliasing rules in
the CHECK macro by casting
a pointer to an incompatible type and dereferencing it. GCC even warns abou
Hi Andre,
On 08/11/17 05:12, Andre McCurdy wrote:
The following commit added the FL_LPAE flag to FL_FOR_ARCH7VE, but
neglected to also add it to the armv7ve compatible cores defined in
arm-cores.def.
https://github.com/gcc-mirror/gcc/commit/af2d9b9e58e8be576c53d94f30c48c68146b0c98
The result i
Hi Tamar,
On 06/11/17 16:48, Tamar Christina wrote:
Hi All,
This patch does a small refactoring to arm_option_override to extract the
part that sets the global state variables so they can be changed without
changing other global field that we do not want to change after the
initial
configurat
On 06/06/17 14:17, James Greenhalgh wrote:
On Tue, Jun 06, 2017 at 09:40:44AM +0100, Kyrill Tkachov wrote:
Hi all,
On top of the previous vec_merge simplifications [1] we can add this pattern to
perform
a store of a vec_concat of two 64-bit values in distinct registers as an STP.
This avoids
Hi Thomas,
On 08/11/17 09:50, Thomas Preudhomme wrote:
Hi,
A number of instructions are output in assembler form by
output_return_instruction () when compiling a function with the
cmse_nonsecure_entry attribute for Armv8-M Mainline with hardfloat float
ABI. However, the corresponding thumb2_cms
On 08/11/17 19:21, Andre McCurdy wrote:
The following commit added the FL_LPAE flag to FL_FOR_ARCH7VE, but
neglected to also add it to the armv7ve compatible cores defined in
arm-cores.def.
https://github.com/gcc-mirror/gcc/commit/af2d9b9e58e8be576c53d94f30c48c68146b0c98
The result is that gcc
Hi Dominic,
On 10/11/17 09:36, Dominik Inführ wrote:
Hi,
this patch tries to refine the instruction scheduling model for X-Gene.
Improved performance for 456.hmmer and 464.h264ref (about 1%). Also splits the
model into multiple automatons, therefore smaller binary and faster build time.
Surv
Hi Christophe,
On 10/11/17 08:43, Christophe Lyon wrote:
Hi,
The attached testsuite patch makes
gcc.target/arm/copysign_softfloat_1.c UNSUPPORTED on
arm-none-linux-gnueabihf, rather than FAIL/UNRESOLVED because of a
link failure since the toolchain startup code is in hard-float ABI
while the te
Hi Jakub,
On 10/11/17 13:59, Jakub Jelinek wrote:
Hi!
This is something Uros requested in the PR, at least with BIT_NOT_EXPRs
it is easy. Previous store merging changes required that bit_not_p
is equal on all stores in the group (in all 3 spots, i.e. on the result
of BIT_{AND,IOR,XOR}_EXPR and
Hi Thomas,
On 10/11/17 11:57, Thomas Preudhomme wrote:
Sorry for the garbled email, I guess I did a middle click paste which
sometimes
paste things several times. Let me try again:
For the most part, testcases under gcc.target/arm/cmse/baseline and
gcc.target/arm/cmse/mainline are duplicate co
On 13/11/17 11:09, Dominik Inführ wrote:
Oh sure, I've now successfully bootstrapped on arm-linux-gnueabihf and
aarch64-unknown-linux-gnu.
Dominik
Thanks Dominik,
This is ok for trunk.
Kyrill
On 10 Nov 2017, at 10:53, Kyrill Tkachov wrote:
Hi Dominic,
On 10/11/17 09:36, Do
On 15/11/17 08:49, Dominik Inführ wrote:
Could you please commit it for me? I don’t have commit rights.
Ah, of course.
Committed with r254759.
Thanks,
Kyrill
Thanks,
Dominik
On 13 Nov 2017, at 12:27, Kyrill Tkachov wrote:
On 13/11/17 11:09, Dominik Inführ wrote:
Oh sure, I'v
Hi Kugan,
On 07/11/17 04:10, Kugan Vivekanandarajah wrote:
Hi,
Attached patch implements the vld1_*_x2 intrinsics as defined by the
neon document.
Bootstrap for the latest patch is ongoing on aarch64-linux-gnu. Is
this OK for trunk if no regressions?
This looks mostly ok to me (though I ca
Hi Tamar,
On 10/11/17 10:56, Tamar Christina wrote:
Hi Sandra,
I've respun the patch with the docs changes you requested.
Regards,
Tamar
> -Original Message-
> From: Sandra Loosemore [mailto:san...@codesourcery.com]
> Sent: 07 November 2017 03:38
> To: Tamar Christina; gcc-patches@gcc
Hi Jeff,
I think you attached the wrong patch to this mail...
Kyrill
On 15/11/17 06:32, Jeff Law wrote:
So the next group of changes is focused on breaking down evrp into an
analysis engine and the actual optimization pass. The analysis engine
can be embedded into other dom walker passes qui
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