Hi all,
This patch implements some more SIMD32, but these ones have a DImode
result+addend.
Apart from that there's nothing too exciting about them.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Will commit to trunk within the next day or two.
Thanks,
Kyrill
2019-09-25 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/arm.md (arm_<simd32_op>): New define_insn.
* config/arm/arm_acle.h (__smlald, __smlaldx, __smlsld, __smlsldx):
Define.
* config/arm/arm_acle.h: Define builtins for the above.
* config/arm/iterators.md (SIMD32_DIMODE): New int_iterator.
(simd32_op): Handle the above.
* config/arm/unspecs.md: Define unspecs for the above.
2019-09-25 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* gcc.target/arm/acle/simd32.c: Update test.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index d091f6744b5054428fdd11c6c10a4628c7a52d9e..b6db276b87f597ff7611060b9f856311dcd3b98a 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -5088,6 +5088,17 @@
[(set_attr "predicable" "yes")
(set_attr "type" "alu_dsp_reg")])
+(define_insn "arm_<simd32_op>"
+ [(set (match_operand:DI 0 "s_register_operand" "=r")
+ (unspec:DI
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")
+ (match_operand:DI 3 "s_register_operand" "0")] SIMD32_DIMODE))]
+ "TARGET_INT_SIMD"
+ "<simd32_op>%?\\t%Q0, %R0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "type" "smlald")])
+
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "s_register_operand")
(float_extend:DF (match_operand:SF 1 "s_register_operand")))]
diff --git a/gcc/config/arm/arm_acle.h b/gcc/config/arm/arm_acle.h
index 9c6f12d556654b094a23a327c030820172a03a4c..248a355d00239a8724e46b9203c818906a4d4908 100644
--- a/gcc/config/arm/arm_acle.h
+++ b/gcc/config/arm/arm_acle.h
@@ -403,8 +403,37 @@ __usada8 (uint8x4_t __a, uint8x4_t __b, uint32_t __c)
return __builtin_arm_usada8 (__a, __b, __c);
}
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__smlald (int16x2_t __a, int16x2_t __b, int64_t __c)
+{
+ return __builtin_arm_smlald (__a, __b, __c);
+}
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__smlaldx (int16x2_t __a, int16x2_t __b, int64_t __c)
+{
+ return __builtin_arm_smlaldx (__a, __b, __c);
+}
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__smlsld (int16x2_t __a, int16x2_t __b, int64_t __c)
+{
+ return __builtin_arm_smlsld (__a, __b, __c);
+}
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__smlsldx (int16x2_t __a, int16x2_t __b, int64_t __c)
+{
+ return __builtin_arm_smlsldx (__a, __b, __c);
+}
+
#endif
+
#pragma GCC push_options
#ifdef __ARM_FEATURE_CRC32
#ifdef __ARM_FP
diff --git a/gcc/config/arm/arm_acle_builtins.def b/gcc/config/arm/arm_acle_builtins.def
index c675fc46dae6552b8762e9bbb6147d8a6d15133a..0021c0036ad7e1bddef6553a900c9eaf145037b6 100644
--- a/gcc/config/arm/arm_acle_builtins.def
+++ b/gcc/config/arm/arm_acle_builtins.def
@@ -75,3 +75,7 @@ VAR1 (BINOP, smusd, si)
VAR1 (BINOP, smusdx, si)
VAR1 (UBINOP, usad8, si)
VAR1 (UBINOP, usada8, si)
+VAR1 (TERNOP, smlald, di)
+VAR1 (TERNOP, smlaldx, di)
+VAR1 (TERNOP, smlsld, di)
+VAR1 (TERNOP, smlsldx, di)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 538f5bf6b0116f49b27eef589b0140aa7792e976..8c9f7121951ba319fcb6cf4c73e186f3764917c2 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -443,6 +443,9 @@
UNSPEC_UQSUB16 UNSPEC_SMUSD UNSPEC_SMUSDX
UNSPEC_SXTAB16 UNSPEC_UXTAB16 UNSPEC_USAD8])
+(define_int_iterator SIMD32_DIMODE [UNSPEC_SMLALD UNSPEC_SMLALDX
+ UNSPEC_SMLSLD UNSPEC_SMLSLDX])
+
(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
(define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE])
@@ -1051,7 +1054,9 @@
(UNSPEC_UQSAX "uqsax") (UNSPEC_UQSUB16 "uqsub16")
(UNSPEC_SMUSD "smusd") (UNSPEC_SMUSDX "smusdx")
(UNSPEC_SXTAB16 "sxtab16") (UNSPEC_UXTAB16 "uxtab16")
- (UNSPEC_USAD8 "usad8")])
+ (UNSPEC_USAD8 "usad8") (UNSPEC_SMLALD "smlald")
+ (UNSPEC_SMLALDX "smlaldx") (UNSPEC_SMLSLD "smlsld")
+ (UNSPEC_SMLSLDX "smlsldx")])
;; Both kinds of return insn.
(define_code_iterator RETURNS [return simple_return])
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 08a6cd77ce08d8c9cf42abcf3c9277b769043cfd..78f88d5fa09f424a9ab638053cc4fe068aa19368 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -123,6 +123,10 @@
UNSPEC_SMUSDX ; Represent the SMUSDX operation.
UNSPEC_USAD8 ; Represent the USAD8 operation.
UNSPEC_USADA8 ; Represent the USADA8 operation.
+ UNSPEC_SMLALD ; Represent the SMLALD operation.
+ UNSPEC_SMLALDX ; Represent the SMLALDX operation.
+ UNSPEC_SMLSLD ; Represent the SMLSLD operation.
+ UNSPEC_SMLSLDX ; Represent the SMLSLDX operation.
])
diff --git a/gcc/testsuite/gcc.target/arm/acle/simd32.c b/gcc/testsuite/gcc.target/arm/acle/simd32.c
index f5c116d13968eefa42bea86b1e44bba8c66d7b77..e43ea96befdcbc581f61cb3fa798a49f13cd640a 100644
--- a/gcc/testsuite/gcc.target/arm/acle/simd32.c
+++ b/gcc/testsuite/gcc.target/arm/acle/simd32.c
@@ -244,3 +244,35 @@ test_usada8 (uint8x4_t a, uint8x4_t b, uint32_t c)
}
/* { dg-final { scan-assembler-times "\tusada8\t...?, ...?, ...?, ...?" 1 } } */
+
+int64_t
+test_smlald (int16x2_t a, int16x2_t b, int64_t c)
+{
+ return __smlald (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\tsmlald\t...?, ...?, ...?, ...?" 1 } } */
+
+int64_t
+test_smlaldx (int16x2_t a, int16x2_t b, int64_t c)
+{
+ return __smlaldx (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\tsmlaldx\t...?, ...?, ...?, ...?" 1 } } */
+
+int64_t
+test_smlsld (int16x2_t a, int16x2_t b, int64_t c)
+{
+ return __smlsld (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\tsmlsld\t...?, ...?, ...?, ...?" 1 } } */
+
+int64_t
+test_smlsldx (int16x2_t a, int16x2_t b, int64_t c)
+{
+ return __smlsldx (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\tsmlsldx\t...?, ...?, ...?, ...?" 1 } } */
