LGTM
On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding wrote:
>
> This patch add combine patterns to combine vfsgnj.vv + vcond_mask
> to mask vfsgnj.vv. For vfsgnjx.vv, it can not be produced in midend
> currently. We will send another patch to take this issue.
>
> gcc/ChangeLog:
>
> * config/r
LGTM, thanks :)
On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding wrote:
>
> This patch adds combine patterns to combine vmulh[u].vv + vcond_mask
> to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend
> currently. We will send another patch to take this issue.
>
> gcc/ChangeLog:
>
>
LGTM with a minor comment.
> @@ -4054,7 +4060,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const
> bb_info *bb) const
> }
>
>/* Step1: Reshape the VL/VTYPE status to make sure everything compatible.
> */
> - auto_vec pred_cfg_bbs = get_dominated_by
> (CDI_POST_DOMINATORS, cfg_bb);
lgtm
On Thu, Sep 14, 2023 at 3:52 PM Juzhe-Zhong wrote:
>
> update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp.
>
> This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE
>
> update v2 -> v3: Remove redundant format.
>
> PR target/111395
>
> gcc/Chang
On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong wrote:
>
> This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
>
> I notice that previous patch (V2 patch) cause additional execution fail of
> pr69719.c
> This FAIL is because of the latent BUG of VSETVL PASS.
>
> So this patch include
Could you check if it work correctly for rv64gcv_zve32x? add testcase
no matter if it works or not :)
On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
wrote:
>
> Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in
> vec_extract optab ?
>
>
>
> juzhe.zh...@rivai.ai
>
>
Yeah, try pr111391.c with rv64gc_zve32x (NO v, my mistake in last mail
:P), maybe add a testcase pr111391-zve32x.c that just include
pr111391.c and set dg option to rv64gc_zve32x
On Thu, Sep 14, 2023 at 5:24 PM juzhe.zh...@rivai.ai
wrote:
>
> You mean try pr111391.c
> that I added with rv64gcv_z
LGTM
Juzhe-Zhong 於 2023年9月14日 週四 20:44 寫道：
> This patch support mask operations (comparison and logical).
>
> This patch reduce these FAILs of "vect" testsuite:
> FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects
> scan-tree-dump dce7 "<=\\s*.+{ 255,.+}"
> FAIL: gcc.dg/vect/vect-bi
LGTM too :)
On Thu, Sep 14, 2023 at 10:11 PM 钟居哲 wrote:
>
> LGTM.
> It's obvious you fixed my previous redundant codes.
> Thanks.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Lehua Ding
> Date: 2023-09-13 20:31
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
LGTM
On Thu, Sep 14, 2023 at 11:51 PM Lehua Ding wrote:
>
> This patch add combine pattern to combine extend and reduce sum
> to widen reduce sum. The pattern in autovec.md was adjusted as
> needed. Note that the current vectorization cannot generate reduce
> openrand which is LMUL=M8, because th
I am thinking what we are doing is something like we are allowing
scalar mode within the vector register, so...not sure should we try to
implement that within the mov pattern?
I guess we need some inputs from Jeff.
e.g.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0ec
LGTM
On Fri, Sep 15, 2023 at 1:06 PM Lehua Ding wrote:
> This patch refactors expand_reduction, remove the reduction_type argument
> and add insn_flags argument to determine the passing of the operands.
> ops has also been modified to restrict it to only two cases and to remove
> operand that ar
I guess another solution is using reg_or_subregno instead of REGNO, but
that should not catch more cases, and just more run-time check, so this
version is LGTM.
LGTM
On Mon, Sep 18, 2023 at 11:27 AM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to add the VLS support vec_set, both INT
> and FP are included.
>
> Give sample code as below:
>
> typedef long long vl_t \
> __attribute__((vector_size(2 * sizeof (long long;
>
>
I think it's not make too much sense to back port GCC14's change to
GCC 13, removing phase 6 optimization is reasonable to me, so LGTM :)
On Mon, Sep 18, 2023 at 2:44 PM juzhe.zh...@rivai.ai
wrote:
>
> Thanks for fixing it.
> I am ok remove phase 6 optimization which has many latent bugs (in GCC
LGTM :)
On Mon, Sep 18, 2023 at 3:07 PM Juzhe-Zhong wrote:
>
> We have largely supportted VLS modes. Only move patterns of VLS modes are
> different from VLS patterns. The rest of them are the same.
>
> We always extend the current VLA patterns with VLSmodes:
>
> VI --> V_VLSI
> VF --> V_VLSF
>
>
is bugfix be backported to GCC 13 now? If so, how can I do it?
>
> On 2023/8/31 10:12, Lehua Ding wrote:
> > Committed to the trunk and backported to GCC 13 one week later.
> > Thanks Juzhe and Kito.
> >
> > On 2023/8/31 9:44, Kito Cheng via Gcc-patches wrote:
> >
LGTM
On Sun, Sep 17, 2023 at 10:07 AM Juzhe-Zhong wrote:
>
> This patch supports VLS reduction vectorization.
>
> It can optimize the current reduction vectorization codegen with current COST
> model.
>
> #define DEF_REDUC_PLUS(TYPE)\
> TYPE __attribute__ ((noinline, noclone)
I may missed that one time too, not on plane yet, but need to go bed
earlier due to my flight is in next day early morning...
On Mon, Sep 18, 2023 at 11:07 PM Palmer Dabbelt wrote:
>
> My flight to the Cauldron lands in the middle of the meeting, so I'm
> going to miss it. In theory it's all set
LGTM, thanks for fixing that :)
On Tue, Sep 19, 2023 at 8:54 AM Tsukasa OI via Gcc-patches
wrote:
>
> From: Tsukasa OI
>
> riscv-builtins.cc includes riscv-cmo.def and riscv-scalar-crypto.def
> (making dependencies) but their dependencies must be explicitly defined at
> the configuration file, t
Hi Andrew:
I am not sure the reason why some targets pick different numbers.
It seems it's not only target dependent but also OS dependent[1].
For RV32, I think using 1<<29 like other 32 bit targets is fine.
[1]
https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/asan/asan_mapping.
On Fri, Aug 21, 2020 at 12:04 AM Palmer Dabbelt wrote:
>
> On Wed, 19 Aug 2020 02:25:37 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> > Hi Andrew:
> >
> > I am not sure the reason why some targets pick different numbers.
> > It seems it's not only target dependent but also OS dependent[1].
> >
> >
Hi Gerald:
Thanks for your patch :)
On Sun, Aug 23, 2020 at 6:19 PM Gerald Pfeifer wrote:
>
> Pushed. Gerald
>
> ---
> htdocs/readings.html | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/htdocs/readings.html b/htdocs/readings.html
> index b960eb8c..978d566c 100644
> --
Hi Maciej:
Thanks for your patch, I tried to compile all target libraries with
-O0 and got link error as you describe, it's really confusing about
the error message, __pthread_mutex_lock and __pthread_mutex_unlock are
undefined, it turns out the root cause is the __umoddi3 called
_Unwind_Resume an
Hi Maciej:
I just found the mail thread about div mod with -fnon-call-exceptions,
I think keeping the default LIB2_DIVMOD_EXCEPTION_FLAGS unchanged
should be the best way to go.
Non-call exceptions and libcalls
https://gcc.gnu.org/legacy-ml/gcc/2001-06/msg01108.html
Non-call exceptions and libca
Hi Maciej:
Thanks for your explanation, I am OK with this change for the RISC-V port now,
but I think I don't have permission to approve this patch since it's
more than RISC-V port specific,
maybe you need approval from Richard Biener.
On Wed, Aug 26, 2020 at 12:33 AM Maciej W. Rozycki via Gcc-p
Hi Maciej:
LGTM, thanks for your patch!
On Sat, Aug 29, 2020 at 9:19 PM Maciej W. Rozycki via Gcc-patches
wrote:
>
> Use `-fasynchronous-unwind-tables' rather than `-fexceptions
> -fnon-call-exceptions' in LIB2_DIVMOD_FUNCS compilation flags so as to
> provide unwind tables for the affected func
On Thu, Sep 10, 2020 at 5:41 PM Eric Botcazou wrote:
>
> > I'd say there must be (wishful thinking) some expand_expr
> > modifier that guarantees this? Alternatively use
> >
> > reg = force_reg (mode, reg);
I did a try, seems like force_reg didn't handle PARALLE :(
> >
> > instead of assig
Optimized version of the v2 patch, get rid of assign_stack_temp.
diff --git a/gcc/expr.c b/gcc/expr.c
index 1a15f24b3979..5f744a6c1b8d 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -5168,7 +5168,16 @@ expand_assignment (tree to, tree from, bool nontemporal)
rtx reg, mem;
reg = expand_ex
Hi Nathan:
Tested variadic-sizeof4.C on x86, x86_64 with native compiler
Tested variadic-sizeof4.C on aarch64, arm-eabi, riscv32, riscv64,
mips, mips64 and nds32 with cross compiler.
And tested g++/dg.exp on arm-eabi with this patch, no new fail introduced.
On Mon, Mar 23, 2020 at 2:27 AM Jim
On Thu, Jul 9, 2020 at 4:03 AM Jim Wilson wrote:
>
> On Tue, Jul 7, 2020 at 2:52 AM Kito Cheng wrote:
> > gcc/ChangeLog:
> > * gcc/config/riscv/riscv.md (): New.
> > (TP_REGNUM): Ditto.
> > * doc/extend.texi (Target Builtins): Add RISC-V built-in section.
> > Docum
Committed with typo fix (on the title) and ChangeLog fix.
On Thu, Jul 9, 2020 at 2:48 PM Kito Cheng wrote:
>
> On Thu, Jul 9, 2020 at 4:03 AM Jim Wilson wrote:
> >
> > On Tue, Jul 7, 2020 at 2:52 AM Kito Cheng wrote:
> > > gcc/ChangeLog:
> > > * gcc/config/riscv/riscv.md (): New.
> > >
Committed, thanks.
On Thu, Jul 9, 2020 at 3:39 AM Jim Wilson wrote:
>
> On Tue, Jul 7, 2020 at 12:28 AM Kito Cheng wrote:
> > gcc/ChangeLog:
> > * config/riscv/riscv-sr.c
> > (riscv_remove_unneeded_save_restore_calls):
> > Abort if any arguments on stack.
> > gcc/testsuite/Chang
Hi Simon:
Thanks for your fix!
Hi Jim:
Yeah, I think I should check the dejagnu errors.
On Sat, Jul 11, 2020 at 12:46 PM Jim Wilson wrote:
>
> On Fri, Jul 10, 2020 at 6:53 AM Simon Cook wrote:
> > Some square brackets were missing escape characters, causing DejaGnu to
> > try and call a proc
Hi Cooper:
Could you add testcases like ppc[3-4]?
[3]
https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/powerpc/ssp-1.c
[4]
https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/powerpc/ssp-2.c
On Mon, Jul 20, 2020 at 10:04 AM cooper via Gcc-patches
wrote
Hi Jakub:
Thanks for your review, committed with formatting fixes.
Hi Richard:
Thanks, I'll commit that after gcc 10.2 release :)
On Wed, Jul 22, 2020 at 6:14 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Wed, Jul 22, 2020 at 04:53:00PM +0800, Kito Cheng wrote:
> > --- a/gcc/asan.c
> > +++ b/
GCC 10.2 released, committed to GCC 10 branch :)
On Thu, Jul 23, 2020 at 3:21 PM Kito Cheng wrote:
>
> Hi Jakub:
>
> Thanks for your review, committed with formatting fixes.
>
> Hi Richard:
>
> Thanks, I'll commit that after gcc 10.2 release :)
>
> On Wed, Jul 22, 2020 at 6:14 PM Jakub Jelinek vi
Add testcase later is OK to me.
On Tue, Jul 28, 2020 at 6:55 AM Jim Wilson wrote:
>
> On Sun, Jul 19, 2020 at 7:04 PM cooper wrote:
> > Ping
> >
> > On 2020/7/13 下午4:15, cooper wrote:
> > > gcc/
> > > * config/riscv/riscv-opts.h (stack_protector_guard): New enum.
> > > * config/riscv
Hi Cooper:
Thanks for your patch! committed to trunk.
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c931e8d5a96463427040b0d11f9c4352ac22b2b0
On Wed, Jul 29, 2020 at 8:34 PM Cooper Qu via Gcc-patches
wrote:
>
> Sorry for later replay, I will add testcases on a following patch if the
> patch is a
Hi Joshua, Jim:
> > +/* Implement TARGET_ASAN_SHADOW_OFFSET. */
> > +
> > +static unsigned HOST_WIDE_INT
> > +riscv_asan_shadow_offset (void)
> > +{
> > + return HOST_WIDE_INT_UC (0x1000);
> > +}
>
> Is there a reason why you used 0x1000?
>
> Looking at other targets, it appears the conv
Hi Richard:
> I do think that local variable layout probably doesn't belong in that IPA pass
> but elsewhere (way earlier). But my main complaint was that the diff
> doesn't show changes you made to the pass because it first and foremost
> shows moving all the code. That makes reviewing the chan
Committed, thanks :)
On Mon, Jun 1, 2020 at 4:10 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Mon, Jun 01, 2020 at 03:43:00PM +0800, Kito Cheng wrote:
> > ping
> >
> >
> > On Wed, May 20, 2020 at 3:01 PM Kito Cheng wrote:
> > >
> > > - Run gcc testsuite with qemu will print out ascii color co
Hi Gerald:
Thanks for notifying me, we'll update that page soon :)
On Tue, Dec 15, 2020 at 4:08 PM Gerald Pfeifer wrote:
>
> On Fri, 13 Nov 2020, Kito Cheng wrote:
> > - New option -misa-spec support: -misa-spec=[2.2|20190608|20191213] and
> >corresponding configuration option --with-isa-sp
Found some build issue on MacOS, will update v2 patches in next few days
On Mon, Jan 4, 2021 at 5:49 PM Kito Cheng wrote:
>
> This patch set introduce new set of architecture extension test macros
> which is accept on riscv-c-api-doc[1] recently.
>
> The motivation of this scheme is have an unify
Hi Philipp:
Could you add zihintpause to -march parser and guard that on the
pattern and builtin like zifencei[1-2]?
And could you sent a PR to
https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md to
mention __builtin_riscv_pause?
Thanks!
[1] march parser change:
https://github.c
My point is tracking info and consistent behavior/scheme with other
extensions, so personally I strongly prefer it should be guarded with
-march.
But maybe we could create an issue on riscv-c-api-doc[1] or
riscv-toolchain-conventions[2] to
get feedback from LLVM folks, since I think this behavior
Committed
On Fri, Jan 8, 2021 at 3:29 AM Jim Wilson wrote:
>
> On Wed, Jan 6, 2021 at 1:17 AM Kito Cheng wrote:
>
> > RISC-V will put those variable on srodata rather than rodata.
> > gcc/testsuite/ChangeLog:
> > * gcc.dg/array-quals-1.c: Allow srodata.
> >
>
> OK.
>
> Jim
Committed, thanks :)
On Fri, Jan 8, 2021 at 3:49 AM Jim Wilson wrote:
>
> On Thu, Jan 7, 2021 at 1:55 AM Kito Cheng wrote:
>
> > This patch set introduce new set of architecture extension test macros
> > which is accept on riscv-c-api-doc[1] recently.
> >
> > The motivation of this scheme is hav
It's OK for gcc 10? I just forgot to backport that...
On Fri, Nov 6, 2020 at 11:24 AM Kito Cheng wrote:
>
> Committed, thanks :)
>
> On Fri, Nov 6, 2020 at 6:21 AM Jeff Law wrote:
>
> >
> > On 10/16/20 3:01 AM, Martin Liška wrote:
> > > On 10/16/20 9:41 AM, Kito Cheng wrote:
> > >> I think it is
Hi Geng Qi:
Thanks for your patch, committed!
On Mon, Jan 18, 2021 at 3:01 PM Geng Qi via Gcc-patches
wrote:
>
> From: gengqi
>
> Think about this case:
> ./multilib-generator rv32imc-ilp32-rv32imac,rv32imacxthead-f
> Here are 2 problems:
> 1. A unexpected 'xtheadf' extension was made.
>
Committed.
On Thu, Jun 11, 2020 at 5:13 AM Jim Wilson wrote:
>
> On Wed, Jun 10, 2020 at 1:08 AM Kito Cheng wrote:
> > * config/riscv/riscv-protos.h (riscv_output_gpr_save): Remove.
> > * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Update
> > value.
> > * c
Committed with adding comments for those two functions.
On Thu, Jun 11, 2020 at 5:10 AM Jim Wilson wrote:
>
> On Wed, Jun 10, 2020 at 1:08 AM Kito Cheng wrote:
> > * config/riscv/riscv.c (gpr_save_reg_order): New.
> > (riscv_expand_prologue): Use riscv_gen_gpr_save_insn to gen
>
Committed, thanks :)
On Tue, Jun 16, 2020 at 6:07 AM Jim Wilson wrote:
>
> On Mon, Jun 15, 2020 at 7:41 AM Kito Cheng wrote:
> > gcc/ChangeLog:
> >
> > PR target/95683
> > * config/riscv/riscv.c (riscv_gpr_save_operation_p): Remove
> > assertion and turn it into a early e
Oh I missed the -mabi in testcase, v2 patch attached, same as V1 but
add -mabi flag to testcase.
On Fri, Jun 19, 2020 at 3:08 PM Kito Cheng wrote:
>
> - g++ will complain too few arguments for frflags builtin like bellow
> message:
>
> error: too few arguments to function 'unsigned int
Hi Jason:
Committed, thanks for your review :)
> You should also be able to remove
>
> > #define RISCV_ATYPE_VOID void_type_node
That's still used for builtin functions without return value :)
>> Current GCC implementation is RISC-V ISA 2.2, this patch set implement
>> v20190608 and v20191213, and also add option
>> -misa-spec=[2.2|20190608|20191213] to change the default ISA spec version.
>>
>> There is one major incompatible
>>
>> That option will effect the default version of each s
On Wed, Nov 18, 2020 at 5:29 AM Jim Wilson wrote:
>
> On Thu, Nov 12, 2020 at 11:28 PM Kito Cheng wrote:
>>
>> +#ifndef HAVE_AS_MARCH_ZIFENCE
>> + /* Skip since older binutils don't recognize zifencei,
>> + we mad a mistake that is binutils 2.35 support zicsr but not support
>> + zifence
>> - CSR related instructions and fence instructions has to be splitted from
>>baseline ISA, zicsr and zifencei are corresponding sub-extension.
>
>
> It is actually only fence.i that is split off. fence is still part of the
> base ISA. This is why it is called zifencei.
Oh...I didn't noti
On Sat, Nov 21, 2020 at 6:12 AM Jim Wilson wrote:
>
> On Fri, Nov 20, 2020 at 12:34 AM Kito Cheng wrote:
>
> > - Define MULTILIB_DEFAULTS can reduce the total number of multilib if
> >the default arch and ABI are listed in the multilib config.
> >
>
> It looks like a good idea, but it doesn'
Committed :)
On Sat, Nov 28, 2020 at 7:45 AM Jim Wilson wrote:
>
> On Thu, Nov 26, 2020 at 1:04 AM Kito Cheng wrote:
>
> > * gcc.c (print_multilib_info): Check default arguments not
> > appeared in multi-lib option list with '!'
> >
>
> OK.
>
> Jim
Committed to trunk :)
On Sat, Nov 28, 2020 at 7:49 AM Jim Wilson wrote:
>
> On Fri, Nov 20, 2020 at 10:38 PM Kito Cheng wrote:
>
> > On Sat, Nov 21, 2020 at 6:12 AM Jim Wilson wrote:
> > > On Fri, Nov 20, 2020 at 12:34 AM Kito Cheng
> > wrote:
> > >
> > > > - Define MULTILIB_DEFAULTS can redu
Committed, thanks :)
On Thu, Dec 3, 2020 at 8:51 AM Jim Wilson wrote:
>
> On Tue, Dec 1, 2020 at 12:13 AM Kito Cheng wrote:
>>
>> - We would like to canonicalize the arch string for --with-arch for
>>easier handling multilib, so split canonicalization part to a stand
>>along script to s
thias Klose wrote:
> > On 12/4/20 9:07 AM, Kito Cheng via Gcc-patches wrote:
> >> Committed, thanks :)
> >>
> >> On Thu, Dec 3, 2020 at 8:51 AM Jim Wilson wrote:
> >>>
> >>> On Tue, Dec 1, 2020 at 12:13 AM Kito Cheng wrote:
> >>&
Committed
On Tue, Dec 8, 2020 at 5:33 AM Jim Wilson wrote:
>
> On Sat, Dec 5, 2020 at 10:12 PM Kito Cheng wrote:
>
> > gcc/ChangeLog:
> >
> > * config.gcc (riscv*-*-*): Checking python, python3 or python2
> > is available, and skip doing with_arch canonicalize if no python
> >
Hi Simon:
V2 version is LGTM, thanks!
On Thu, Dec 10, 2020 at 4:31 AM Simon Cook wrote:
>
>
> On 09/12/2020 14:57, Matthias Klose wrote:
> >
> > that's again hard-coding 'python'.
> >
>
> I believe this way of invoking python should be better than just
> hardcoding python, instead using the int
Hi Simon:
Committed, thanks :)
On Thu, Dec 10, 2020 at 4:56 PM Simon Cook wrote:
>
> Hi Kito,
>
> Thanks for reviewing this. Since I don't have commit access, could you
> commit this for me.
>
> On 10/12/2020 02:32, Kito Cheng wrote:
> > Hi Simon:
> >
> > V2 version is LGTM, thanks!
> >
Thanks for reviewing that, committed to trunk :)
On Tue, Oct 13, 2020 at 5:38 PM Eric Botcazou wrote:
>
> > Do you mind having a review for that?
>
> Sorry for missing the v2 patch; yes, it looks good to me.
>
> --
> Eric Botcazou
>
>
Committed, thanks, other improvement changes will be sent in separate
patches in the next few days :)
On Thu, Oct 15, 2020 at 5:41 AM Jim Wilson wrote:
>
> On Tue, Oct 13, 2020 at 3:09 AM Kito Cheng wrote:
> > - The behavior of -mcpu basically equal to -march plus -mtune, but it
> >has lowe
Hi Martin:
> I can do it earlier if it helps for the integration and testing purpose?
I think it would be helpful! thanks!
On Fri, Oct 16, 2020 at 3:33 PM Martin Liška wrote:
>
> On 8/19/20 11:25 AM, Kito Cheng via Gcc-patches wrote:
> > Could you update that for RV32, and thi
OK for gcc-10 branch?
This patch was committed into trunk for 1 week and seems stable.
On Wed, Oct 14, 2020 at 11:56 AM Kito Cheng wrote:
>
> Thanks for reviewing that, committed to trunk :)
>
> On Tue, Oct 13, 2020 at 5:38 PM Eric Botcazou wrote:
> >
> > > Do you mind having a review for that?
Committed with comment fix, thanks :)
On Thu, Oct 22, 2020 at 10:37 AM Jim Wilson wrote:
>
> On Wed, Oct 21, 2020 at 7:36 PM Jim Wilson wrote:
>
> >
> >
> > On Fri, Oct 16, 2020 at 2:34 AM Kito Cheng wrote:
> >
> >> +# Example 2:
> >> +# rv32imafd-ilp32d--c*b
> >> +# means that, in addition to
I would like to see some benchmark results instead of just a simple
case, to make sure everything is alright, the add pattern is used
literally anywhere, my most worry is the clobber might bring some
negative impact like cause register pressure estimation get higher,
and then result worse code gen.
Alternative fix for those testcase has posted:
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605126.html
On Tue, Nov 1, 2022 at 11:36 AM Palmer Dabbelt wrote:
>
> On Mon, 31 Oct 2022 16:52:25 PDT (-0700), juzhe.zh...@rivai.ai wrote:
> > These cases actually doesn't care about -mabi, th
LGTM, thank you for catching that!!
On Wed, Nov 9, 2022 at 3:50 PM Philipp Tomsich wrote:
>
> A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a
> while now, due to the pipeline model for sifive-7-series not being
> selected despite -mtune=sifive-7-series. The root cause is tha
I am not sure if I am missing something, your testcase should rely on
movmisalignhi pattern, but you defined movmisalign with ANYF
mode iterator rather than movmisalign with HI, SI, DI?
And seems the testcase compile with `-march=rv64gc -mabi=lp64
-mtune=size -O2` w/o this patch already generated
Committed, thanks !
On Sun, Nov 6, 2022 at 1:57 AM wrote:
>
> From: Ju-Zhe Zhong
>
> This patch support RVV scalable register spilling.
> prologue && epilogue handling pick up prototype from Monk Chiang
> .
> Co-authored-by: Monk Chiang
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc
Hi Christoph:
> This patch implements expansions for the cmpstrsi and the cmpstrnsi
> builtins using Zbb instructions (if available).
> This allows to inline calls to strcmp() and strncmp().
>
> The expansion basically emits a peeled comparison sequence (i.e. a peeled
> comparison loop) which comp
Could you provide some testcase?
On Tue, Nov 15, 2022 at 12:29 AM jiawei wrote:
>
> Skip add insn generate if the adjust size equal to zero.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_expand_epilogue):
> New if control segement.
>
> ---
> gcc/co
LGTM, thanks :)
On Thu, Nov 17, 2022 at 5:17 AM Kevin Lee wrote:
>
> l insn condition has been modified based on the thread in
> https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605481.html. The
> lfloor-lecil-inexact checks call instead of scan-assembler-not
> "fcvt.l.s/d" due to https://
Wait, what's Xgnuzihintpausestate???
On Fri, Nov 18, 2022 at 12:30 PM Palmer Dabbelt wrote:
>
> gcc/ChangeLog:
>
> * doc/extend.texi (__builtin_riscv_pause): Imply
> Xgnuzihintpausestate.
> ---
> gcc/doc/extend.texi | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>
committed to trunk and gcc 13
On Tue, Apr 18, 2023 at 9:29 PM Jeff Law wrote:
>
>
>
> On 4/18/23 04:16, Kito Cheng via Gcc-patches wrote:
> > Document which version of RISC-V vector intrinsics has implemented in
> > GCC.
> >
> > gcc/ChangeLog:
> >
&g
Few more background about RVV:
RISC-V has provide different VLEN configuration by different ISA
extension like `zve32x`, `zve64x` and `v`
zve32x just guarantee the minimal VLEN is 32 bits,
zve64x guarantee the minimal VLEN is 64 bits,
and v guarantee the minimal VLEN is 128 bits,
Current status (
Hi Jeff, Ju-Zhe:
Let you know that I am running creduce with this testcase for reduce
the size of testcsae, it's really too huge...
On Wed, Apr 19, 2023 at 3:00 AM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 4/17/23 20:03, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > gcc/ChangeLog:
Hi Richard, Jeff:
It's it possible to backport to GCC 13? highway is one of our
important users for RISC-V vector stuff, and it has built in some
distro, so we believe this bug fix is important to backport.
Thanks
Hi Ju-Zhe:
Thanks for update
On Wed, Apr 19, 2023 at 7:25 AM wrote:
>
> From: J
Do you mind shared gcc configure and the option you tried?
On Wed, Apr 19, 2023 at 4:01 AM Palmer Dabbelt wrote:
>
> On Tue, 18 Apr 2023 08:44:24 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> >> Yep, if I drop the non-canonicial strings via
> >>
> >> diff --git a/gcc/config/riscv/multilib-gen
Could you please move the new function declarations and new code to
the patch where they are being used?
> +/* RVV vector register sizes. */
> +enum riscv_vector_bits_enum
> +{
> + RVV_SCALABLE,
> + RVV_NOT_IMPLEMENTED = RVV_SCALABLE,
> + RVV_64 = 64,
> + RVV_128 = 128,
> + RVV_256 = 256,
>
> +/* Implement TARGET_ESTIMATED_POLY_VALUE.
> + Look into the tuning structure for an estimate.
> + KIND specifies the type of requested estimate: min, max or likely.
> + For cores with a known RVV width all three estimates are the same.
> + For generic RVV tuning we want to distinguish th
> @@ -118,6 +120,41 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT
> minval,
> && IN_RANGE (INTVAL (elt), minval, maxval));
> }
>
> +/* Return the vlmul field for a specific machine mode. */
> +unsigned int
> +riscv_classify_vlmul_field (enum machine_mode mode)
This is not imp
> diff --git a/gcc/config/riscv/vector-iterators.md
> b/gcc/config/riscv/vector-iterators.md
> index 70ad85b661b..7fae87968d7 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -34,6 +34,8 @@
>UNSPEC_VMULHU
>UNSPEC_VMULHSU
>
> + UNSPEC_VA
And which -march -mabi you used will got issue?
On Wed, Apr 19, 2023 at 8:51 AM Palmer Dabbelt wrote:
>
> On Tue, 18 Apr 2023 17:47:31 PDT (-0700), Kito Cheng wrote:
> > Do you mind shared gcc configure and the option you tried?
>
> Just riscv-gnu-toolchain with "--enbale-multilib --enable-linux"
OK, thanks, I know what the problem is, I tried rv64 but didn't try
rv32, I have another fix in my mind, and will post another fix soon.
On Wed, Apr 19, 2023 at 9:29 AM Palmer Dabbelt wrote:
>
> On Tue, 18 Apr 2023 18:26:18 PDT (-0700), Kito Cheng wrote:
> > And which -march -mabi you used will g
Write a primary version for that, did you mind giving it a try?
The basic idea is to select multilib only by ABI, so that we don't
need to bother with endless multilib reuse cases...
On Wed, Apr 19, 2023 at 9:38 AM Kito Cheng wrote:
>
> OK, thanks, I know what the problem is, I tried rv64 but di
Hi Pan:
>rtx expand (function_expander &e) const override diff --git
> a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index
> 0ecca98f20c..6819363b9ff 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be
written into the commit log.
> gcc/ChangeLog:
>
>* config/riscv/riscv-v.cc (emit_pred_op):
>* config/riscv/riscv-vector-builtins-bases.cc:
>* config/riscv/vector.
Could you add more description? maybe like this:
RISC-V has provide different VLEN configuration by different ISA
extension like `zve32x`, `zve64x` and `v`
zve32x just guarantee the minimal VLEN is 32 bits,
zve64x guarantee the minimal VLEN is 64 bits,
and v guarantee the minimal VLEN is 128 bits
---
htdocs/gcc-13/changes.html | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index f6941534..5427f805 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -636,9 +63
> On Wed, 19 Apr 2023 06:53:51 PDT (-0700), kito.ch...@sifive.com wrote:
> > ---
> > htdocs/gcc-13/changes.html | 31 ++-
> > 1 file changed, 30 insertions(+), 1 deletion(-)
> >
> > diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> > index f6941534.
Committed to trunk, thanks!
On Wed, Apr 19, 2023 at 8:34 PM wrote:
>
> From: Juzhe-Zhong
>
> RISC-V has provide different VLEN configuration by different ISA
> extension like `zve32x`, `zve64x` and `v`
> zve32x just guarantee the minimal VLEN is 32 bits,
> zve64x guarantee the minimal VLEN is 64
Committed, thanks :)
On Wed, Apr 19, 2023 at 5:19 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch aligned the MODE_CLASS condition of the IOR to the AND. Then
> more MODE_CLASS besides SCALAR_INT can able to perform the optimization
> A | (~A) -> -1 similar to AND operator. For
> +/* Return the vectorization machine mode for RVV according to LMUL. */
> +machine_mode
> +preferred_simd_mode (scalar_mode mode)
> +{
> + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128
> + which is -march=rv64gcv. Since GCC loop vectorizer report ICE
> + when we enabl
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