> @@ -118,6 +120,41 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT
> minval,
> && IN_RANGE (INTVAL (elt), minval, maxval));
> }
>
> +/* Return the vlmul field for a specific machine mode. */
> +unsigned int
> +riscv_classify_vlmul_field (enum machine_mode mode)
This is not implemented right for the current type system.
> @@ -176,6 +213,64 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
> return ratio;
> }
>
> +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */
> +
> +machine_mode
> +riscv_vector_preferred_simd_mode (scalar_mode mode, unsigned vf)
`vf` is kind of misleading, it should be `LMUL` or something like that.
> +{
> + if (!TARGET_VECTOR)
> + return word_mode;
> +
> + switch (mode)
> + {
> + case E_QImode:
> + return vf == 1 ? VNx8QImode
> + : vf == 2 ? VNx16QImode
> + : vf == 4 ? VNx32QImode
> + : VNx64QImode;
I would prefer only to keep LMUL=1/ vf=1 case for this patch set,
so maybe drop the vf parameter for this moment and add back when
we implement later.
> +/* Return true if it is a RVV tuple mode. */
> +bool
> +riscv_tuple_mode_p (machine_mode mode ATTRIBUTE_UNUSED)
just drop this for now.
> +/* Return nf for a machine mode. */
> +int
> +riscv_classify_nf (machine_mode mode)
Drop this, add that when we implement tuple type.
> +
> +/* Return vlmul register size for a machine mode. */
> +int
> +riscv_vlmul_regsize (machine_mode mode)
UNITS_PER_V_REGget mode size and calculate with UNITS_PER_V_REG
like exact_div (GET_MODE_SIZE (mode), UNITS_PER_V_REG).to_constant ()
> +{
> + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
> + return 1;
> + switch (riscv_classify_vlmul_field (mode))
> + {
> + case VLMUL_FIELD_001:
> + return 2;
> + case VLMUL_FIELD_010:
> + return 4;
> + case VLMUL_FIELD_011:
> + return 8;
> + case VLMUL_FIELD_100:
> + gcc_unreachable ();
> + default:
> + return 1;
> + }
> +}
> +
> +/* Return true if it is a RVV mask mode. */
> +bool
> +riscv_vector_mask_mode_p (machine_mode mode)
> +{
> + return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode
> + || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode
> + || mode == VNx64BImode);
> +}
> +
> +/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV. */
> +
> +opt_machine_mode
> +riscv_vector_get_mask_mode (machine_mode mode)
> +{
> + machine_mode mask_mode;
> + int nf = 1;
> + if (riscv_tuple_mode_p (mode))
> + nf = riscv_classify_nf (mode);
drop nf stuffs
