OK for backport now, steps for backport:
- checkout to releases/gcc-13 branch
- ./contrib/git-backport.py <hash-in-trunk>
- Make sure everything is alright, build-able, no extra regression.
- push releases/gcc-13 branch!
On Mon, Sep 18, 2023 at 3:54 PM Lehua Ding <lehua.d...@rivai.ai> wrote:
>
> Hi Kito,
>
> Can this bugfix be backported to GCC 13 now? If so, how can I do it?
>
> On 2023/8/31 10:12, Lehua Ding wrote:
> > Committed to the trunk and backported to GCC 13 one week later.
> > Thanks Juzhe and Kito.
> >
> > On 2023/8/31 9:44, Kito Cheng via Gcc-patches wrote:
> >> OK for gcc 13 branch too, the general rule for backport is to wait one
> >> week on trunk to make sure the fix is stable.
> >>
> >>
> >> On Thu, Aug 31, 2023 at 8:08 AM juzhe.zh...@rivai.ai
> >> <juzhe.zh...@rivai.ai> wrote:
> >>>
> >>> Ok for trunk. But not sure whether it's ok for GCC-13.
> >>>
> >>>
> >>>
> >>> juzhe.zh...@rivai.ai
> >>>
> >>> From: Lehua Ding
> >>> Date: 2023-08-30 17:51
> >>> To: gcc-patches
> >>> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
> >>> Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
> >>> This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
> >>> vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
> >>>
> >>> PR target/111234
> >>>
> >>> gcc/ChangeLog:
> >>>
> >>> * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
> >>>
> >>> gcc/testsuite/ChangeLog:
> >>>
> >>> * gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
> >>>
> >>> ---
> >>> gcc/config/riscv/riscv-vsetvl.cc | 2 +-
> >>> .../gcc.target/riscv/rvv/vsetvl/pr111234.c | 19 +++++++++++++++++++
> >>> 2 files changed, 20 insertions(+), 1 deletion(-)
> >>> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>>
> >>> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> >>> b/gcc/config/riscv/riscv-vsetvl.cc
> >>> index 1386d9250ca..a81bb53a521 100644
> >>> --- a/gcc/config/riscv/riscv-vsetvl.cc
> >>> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> >>> @@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const
> >>> vector_insn_info &info,
> >>> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
> >>> else
> >>> {
> >>> - if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
> >>> + if (vsetvl_insn_p (rinsn))
> >>> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
> >>> else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
> >>> new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
> >>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>> new file mode 100644
> >>> index 00000000000..ee5eec4a257
> >>> --- /dev/null
> >>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>> @@ -0,0 +1,19 @@
> >>> +/* { dg-do compile } */
> >>> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> >>> +
> >>> +#include <riscv_vector.h>
> >>> +
> >>> +void
> >>> +f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
> >>> +{
> >>> + vint32m1_t va = *in;
> >>> + vbool32_t mask = *m;
> >>> + vint64m2_t vb
> >>> + = __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2
> >>> ());
> >>> + vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1,
> >>> __riscv_vsetvlmax_e64m2 ());
> >>> +
> >>> + if (b != 0)
> >>> + vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1,
> >>> __riscv_vsetvlmax_e64m2 ());
> >>> +
> >>> + *out = vc;
> >>> +}
> >>> --
> >>> 2.36.3
> >>>
> >
>
> --
> Best,
> Lehua
>
