Re: Re: [PATCH V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init

On Wed, May 17, 2023 at 11:36 AM juzhe.zh...@rivai.ai wrote: > > >> Does it means we assume inner_int_mode is DImode? (because sizeof > >> (uint64_t)) > >> or it should be something like `for (unsigned int i = 0; i < > >> (GET_MODE_SIZE(inner_int_mode ()) * 8 / npatterns ()); i++)` ? > No, sizeof

Re: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

RISC-V glibc will require corresponding muilti-lib has built there, otherwise will report something like: /usr/include/gnu/stubs.h:11:11: fatal error: gnu/stubs-ilp32d.h: No such file or directory But actually we only require those fixed length types to compile and scan assembly or dump, So we

Re: [PATCH] RISC-V: Support RVV VREINTERPRET from v{u}int*_t to vbool1_t

ok, and also ok for those small API test in testsuite. On Tue, May 16, 2023 at 9:10 AM Li, Pan2 via Gcc-patches wrote: > > Kindly ping for this PATCH, 😉. > > Pan > > From: Li, Pan2 > Sent: Monday, May 15, 2023 11:25 AM > To: juzhe.zh...@rivai.ai; gcc-patches > Cc: Kito.cheng ; Wang, Yanzhang >

Re: [PATCH] RISC-V: Add mode switching target hook to insert rounding mode config for fixed-point instructions

LGTM, it's really awesome, I know it's kind of blocking due to enum stuff, so feel free to commit this once it unblock :) On Wed, May 17, 2023 at 5:58 PM wrote: > > From: Juzhe-Zhong > > Hi, this patch support the new coming fixed-point intrinsics: > https://github.com/riscv-non-isa/rvv-intrinsi

Re: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

> > RISC-V glibc will require corresponding muilti-lib has built there, > > otherwise will report something like: > > > > /usr/include/gnu/stubs.h:11:11: fatal error: gnu/stubs-ilp32d.h: No > > such file or directory > > > > But actually we only require those fixed length types to compile and > >

Re: [PATCH] RISC-V: Introduce rounding mode operand into fixed-point intrinsics

LGTM, thanks! 钟居哲 於 2023年5月17日 週三，23:02寫道： > Ping this patch which is the prerequisite of this patch: > > https://patchwork.sourceware.org/project/gcc/patch/20230517095818.1285188-1-juzhe.zh...@rivai.ai/ > > which has been approved by kito. > > Is this patch also ok for trunk ? > > Thanks. >

Re: [RFC V2] RISC-V : Support rv64 ilp32

I am concern about we didn't define POINTERS_EXTEND_UNSIGNED here, and also concern about the code model stuffs, I know currently Guo-Ren's implementation is rely on some MMU trick, but I am not sure does it also applicable on embedded applications. > diff --git a/gcc/config/riscv/linux.h b/gcc/c

Re: [PATCH] RISC-V: testsuite: Remove empty *-run-template.h.

LGTM Robin Dapp via Gcc-patches 於 2023年5月19日 週五 19:10 寫道： > Hi, > > this obvious patch removes empty run template files and one redundant > stdio.h include. > > Regards > Robin > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Do not include > .

Re: [PATCH] RISC-V: Allow more loading of const vectors.

LGTM Robin Dapp via Gcc-patches 於 2023年5月19日 週五 19:07 寫道： > Hi, > > this fixes a rebase oversight regarding the loading > of vector constants. Added another test to properly > catch that in the future. > > Regards > Robin > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_const_insn

Re: [PATCH] RISC-V: Support RVV VREINTERPRET from v{u}int*_t to vbool[2-64]_t

Lgtm 於 2023年5月17日 週三，16:14寫道： > From: Pan Li > > This patch support the RVV VREINTERPRET from the int to the > vbool[2|4|8|16|32|64]_t. Aka: > > vbool[2|4|8|16|32|64]_t __riscv_vreinterpret_x_x(v{u}int[8|16|32|64]_t); > > These APIs help the users to convert vector LMUL=1 integer to > vbool[2-6

[PATCH] RISC-V: Add missing torture-init and torture-finish for rvv.exp

Hi Vineet: Could you help to test this patch, this could resolve that issue on our machine, but I would like to also work for other env. Thanks :) --- We got bunch of following error message for multi-lib run: ERROR: torture-init: torture_without_loops is not empty as expected ERROR: tcl error

Re: [PATCH] RISC-V: Reorganize the code of CONST_VECTOR handling in riscv.cc

LGTM On Mon, May 22, 2023 at 3:20 PM wrote: > > From: Juzhe-Zhong > > Since satisfies_constraint_vi (x) belongs to RVV region. > We make this condition inside riscv_v_ext_vector_mode_p to make codes > more reasonable. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_const_insns): Re

Re: [PATCH] RISC-V: Implement autovec abs, vneg, vnot.

So I expect you will also apply those refactor on Juzhe's new changes? If so I would like to have a separated NFC refactor patch if possible. e.g. Juzhe's vec_cmp/vcond -> NFC refactor patch -> abs, vneg, vnot On Mon, May 22, 2023 at 4:59 PM Robin Dapp wrote: > > As discussed with Juzhe off-list

Re: [PATCH] RISC-V: Add missing torture-init and torture-finish for rvv.exp

Ooops, seems still some issue around here, but I found something might related this issue: https://github.com/gcc-mirror/gcc/commit/d6654a4be3ba44c0d57be7c8a51d76d9721345e1 https://github.com/gcc-mirror/gcc/commit/23c49bb8d09bc3bfce9a08be637cf32ac014de56 On Mon, May 22, 2023 at 2:42 PM Kito Cheng

Re: [PATCH] RISC-V: Implement autovec abs, vneg, vnot.

> > So I expect you will also apply those refactor on Juzhe's new changes? > > If so I would like to have a separated NFC refactor patch if possible. > > What's NFC? :) Do you mean to just have the refactor part as a separate > patch? If yes, I agree. NFC: non-functional-change, that's a term us

Re: [PATCH] RISC-V: Fix typo of multiple_rgroup-2.h

ok On Mon, May 22, 2023 at 6:02 PM wrote: > > From: Juzhe-Zhong > > Just notice this following fail in the regression: > FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c (test for > excess errors) > FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c (test for > ex

Re: [PATCH] RISC-V: Add "m_" prefix for private member

LGTM On Mon, May 22, 2023 at 8:10 PM wrote: > > From: Juzhe-Zhong > > Since the current framework is hard to maintain and > hard to be used in the future possible auto-vectorization patterns. > > We will need to keep adding more helpers and arguments during the > auto-vectorization supporting. W

Re: Re: [PATCH] RISC-V: Refactor the framework of RVV auto-vectorization

> ARM uses rtx operands[] in many places and I personally prefer this way since > it will make codes much cleaner. > I dislike the way making the function argument with multiple operand ,like > this: > void func(rtx dest, rtx src1, rtx src2, ) > If we are doing this, we will need to add helper

Re: Re: [PATCH V2] RISC-V: Refactor the framework of RVV auto-vectorization

Lgtm, we can always improve later, I am not intend to block things too :) juzhe.zh...@rivai.ai 於 2023年5月23日 週二 17:46 寫道： > Oh， Thanks. > Let's wait for Kito's final approved. > > > > juzhe.zh...@rivai.ai > > From: Robin Dapp > Date: 2023-05-23 17:44 > To: juzhe.zhong; gcc-patches > CC: rdapp.gcc

Re: [PATCH] RISC-V: Fix incorrect code of touching inaccessible memory address

I am a little hesitant about that, since I feel the vl and normal op should be put in separately, otherwise the means of m_op_num is kind of unclear, we have comments there but I think it's not ideal since it is really context sensitive and hard to determine. And I suspect gcc_assert (ops[m_op_num

Re: [PATCH V2] RISC-V: Fix incorrect code of reaching inaccessible memory address

Lgtm, thanks 於 2023年5月24日 週三，10:39寫道： > From: Juzhe-Zhong > > To fix this issue, we seperate Vl operand and normal operands. > > gcc/ChangeLog: > > * config/riscv/autovec.md: Adjust for new interface. > * config/riscv/riscv-protos.h (emit_vlmax_insn): Add VL operand. > (e

Re: [PATCH V2] RISC-V: Add RVV comparison autovectorization

> +void > +expand_vec_cmp (rtx target, rtx_code code, rtx mask, rtx maskoff, rtx op0, > + rtx op1) > ... > + rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1); > + rtx ops[RVV_CMP_OP + 2] = {target, mask, maskoff, cmp, op0, op1}; > + emit_vlmax_cmp_insn (icode, RVV_CMP_OP + 2, o

Re: [PATCH] RISC-V: Support RVV VREINTERPRET from vbool*_t to vuint*m1_t

ok On Thu, May 18, 2023 at 2:32 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch support the RVV VREINTERPRET from the vbool*_t to the > vuint*m1_t. Aka: > > vuint*m1_t __riscv_vreinterpret_x_x(vbool*_t); > > These APIs help the users to convert vector the vbool*_t to the LMUL=1

Re: [PATCH v2] RISC-V: Support RVV VREINTERPRET from vbool*_t to vint*m1_t

LGTM On Thu, May 18, 2023 at 2:37 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch support the RVV VREINTERPRET from the vbool*_t to the > vint*m1_t. Aka: > > vint*m1_t __riscv_vreinterpret_x_x(vbool*_t); > > These APIs help the users to convert vector the vbool*_t to the LMUL=1

Re: [PATCH V5] RISC-V: Add RVV comparison autovectorization

LGTM On Wed, May 24, 2023 at 11:29 AM wrote: > > From: Juzhe-Zhong > > This patch enable RVV auto-vectorization including floating-point > unorder and order comparison. > > The testcases are leveraged from Richard. > So include Richard as co-author. > > And this patch is the prerequisite patch f

Re: [PATCH] RISC-V: Add RVV mask logic auto-vectorization

Just one comment: define_insn_and_split should be used in this scenario rather than define_insn_and_rewrite since you are not really rewriting. You can commit after updating to define_insn_and_split :) On Wed, May 24, 2023 at 3:04 PM wrote: > > From: Juzhe-Zhong > > This patch is adding mask lo

Re: [V2 COMMITTED] RISC-V: Add RVV mask logic auto-vectorization

LGTM, just one comment in git comment, no need v3, just commit with the fix is fine :) On Wed, May 24, 2023 at 3:28 PM wrote: > > From: Juzhe-Zhong > > This patch is adding mask logic auto-vectorization. > define the pattern as "define_insn_and_split" to allow don't forgot to update here ^

Re: Re: [V2 COMMITTED] RISC-V: Add RVV mask logic auto-vectorization

Oh, never mind, I mean you updated to use define_insn_and_split but comment still define_insn_and_split, but just ignore that if already committed On Wed, May 24, 2023 at 3:42 PM juzhe.zh...@rivai.ai wrote: > > > > > From: Juzhe-Zhong > > > > This patch is adding mask logic auto-vectorization. >

Re: [PATCH] RISC-V: Add FRM_ prefix to dynamic rounding mode enum

ok On Wed, May 24, 2023 at 7:20 PM wrote: > > From: Juzhe-Zhong > > An obvious fix to make all enum naming consistent. > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (enum frm_field_enum): Add FRM_ prefix. > > --- > gcc/config/riscv/riscv-protos.h | 2 +- > 1 file changed, 1 inser

Re: Re: RISC-V Bootstrap problems

Jojo has a patch to try to split those things that should help this, but seems not landed. https://patchwork.ozlabs.org/project/gcc/patch/20201104015315.81416-1-jiejie_r...@c-sky.com/ > How about LLVM? Can kito help with this issue? > LLVM has already supported full intrinsics for a long time an

Re: [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions

LGTM, thanks :) On Wed, May 24, 2023 at 7:26 PM wrote: > > From: Juzhe-Zhong > > According to RVV ISA: > The conversions use the dynamic rounding mode in frm, except for the rtz > variants, which round towards zero. > > So rtz conversion patterns should not have FRM dependency. > > We can't sup

Re: RISC-V Bootstrap problems

Yeah, JoJo still working on toolchain stuff, but just not active on upstream GCC cc. jojo On Thu, May 25, 2023 at 12:06 PM Jeff Law wrote: > > > > On 5/24/23 21:53, Kito Cheng wrote: > > Jojo has a patch to try to split those things that should help this, > > but seems not landed. > > > > https:

Re: [PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

> When testing a extension, it is often necessary for a certain program not to > need some kind of extension, such as the bitmanip extension, to evaluate the > performance or codesize of the extension. However, the current multilib rules > will report an error when it is not a superset of the MULTI

Re: [PATCH] RISC-V: Fix zero-scratch-regs-3.c fail

Lgtm with a minor comment 於 2023年5月26日 週五 07:18 寫道： > From: Juzhe-Zhong > > Fix ICE of zero-scratch-regs-3.c: > bug.c:7:1: internal compiler error: Segmentation fault > 7 | } > | ^ > 0x1647b23 crash_signal > ../../../riscv-gcc/gcc/toplev.cc:314 > 0x147053f maybe_legitimize_ope

Re: [PATCH] RISC-V: Optimize TARGET_XTHEADCONDMOV

I would defer this to vrull or t-head folks :) Die Li 於 2023年5月26日 週五 08:53 寫道： > This patch allows less instructions to be used when TARGET_XTHEADCONDMOV > is enabled. > > Provide an example from the existing testcases. > > Testcase: > int ConEmv_imm_imm_reg(int x, int y){ > if (x == 1000) re

Re: [PATCH] RISC-V: Fix -march option parsing when `p` extension exists.

Hi Xing: Thanks for your patch, but I would like to know did you have the copyright assignment for FSF? or your employee/company has signed that? On Thu, Jan 21, 2021 at 8:48 PM Xing GUO via Gcc-patches wrote: > > This patch fixes -march option parsing when `p` extension exists, > e.g., -march=r

Re: [PATCH 0/2] RISC-V big endian support

Hi Marcus: Let you know reviewing this patch is on my TODO list, and I definitely want this included in GCC 11, but I am working on other urgent work this week, so I might not be able to give any review comment or testing at this moment. Thanks for your awesome work for big-endian support! On Tu

Re: [PATCH] RISC-V: Fix -march option parsing when `p` extension exists.

Thanks! committed to master :) On Wed, Jan 27, 2021 at 1:58 PM Xing GUO via Gcc-patches wrote: > > Sorry, I forgot to remove the line '*explicit_version_p = true;' in my > previous patch. > > This is an updated patch. > > Thanks! > > --- > gcc/ChangeLog: > > * common/config/riscv/riscv-co

Re: [PATCH] RISC-V: Always define MULTILIB_DEFAULTS

Hi Sebastian: Thank for report this issue, I can reproduce that, I'll investigate what happened today :) Sebastian Huber 於 2021年1月26日 週二 14:13 寫道： > Hello Kito, > > On 20/11/2020 09:33, Kito Cheng wrote: > > - Define MULTILIB_DEFAULTS can reduce the total number of multilib if > > the def

Re: [PATCH 0/2] RISC-V big endian support

Hi Marcus: > * Implicitly pass default endianness as -mbig-endian / -mlittle-endian > to gas, since older binutils targeting little endian will not understand > -mlittle-endian. Instead assume gas has the same default as gcc. > If -mbig-endian or -mlittle-endian is explicitly given, it is p

Re: [PATCH 1/2] RISC-V: Support -mlittle-endian and -mbig-endian

Could you document -mbig-endian and -mlittle-endian in gcc/doc/invoke.texi? On Tue, Jan 26, 2021 at 2:16 AM Marcus Comstedt wrote: > > gcc/ > * config/riscv/elf.h (LINK_SPEC): Pass linker endianness flag. > * config/riscv/freebsd.h (LINK_SPEC): Likewise. > * config/riscv/l

Re: [PATCH 2/2] RISC-V: Add riscv{32, 64}be with big endian as default

> diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h > index 973efdaed7b..7e65e499031 100644 > --- a/gcc/config/riscv/elf.h > +++ b/gcc/config/riscv/elf.h > @@ -18,7 +18,7 @@ along with GCC; see the file COPYING3. If not see > . */ > > #define LINK_SPEC "

Re: [PATCH] RISC-V: Fix -march option parsing when `p` extension exists.

Pushed, thanks :) On Mon, Feb 1, 2021 at 4:58 PM Xing GUO wrote: > > Hi, > > I've reproduced the failure. It's because my gcc is configured as a > bare-metal toolchain and built with binutils that supports RISC-V > attribute. That is to say, my gcc emits RISC-V attributes by default. > Below is t

Re: [PATCH] PR target/98743: Fix ICE in convert_move for RISC-V

On Mon, Feb 1, 2021 at 6:10 PM Jakub Jelinek wrote: > > On Mon, Feb 01, 2021 at 05:57:28PM +0800, Kito Cheng wrote: > > > > - Check `TO` mode is not BLMmode before call store_expr, calling > > > > store_expr > > > >with BLKmode will cause ICE. > > > > > > How do you end up with a SUBREG_PROM

Re: [PATCH 2/2] RISC-V: Add riscv{32, 64}be with big endian as default

> > Could you extract the endian related LINK_SPEC change to > > ENDIAN_LINK_SPEC to riscv.h, so that we can prevent > > duplicate this several times. > > You mean a define which expands to > > "-melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" Yeah, but I'd like to include following 2 lines too: %{

Re: [PATCH] PR target/98878 - Incorrect multilib list for riscv*-rtems

Thanks Jim, committed with your revision of comment :) On Fri, Feb 5, 2021 at 11:28 AM Jim Wilson wrote: > > On Thu, Feb 4, 2021 at 2:02 AM Kito Cheng wrote: >> >> * gcc.c (print_multilib_info): Check all required argument is >> provided >> by default arg. > > > This looks OK to

Re: [PATCH 0/2] RISC-V big endian support

Hi Marcus: > I could also disable the -mlittle-endian and -mbig-endian options if > the binutils is too old, but it's questionable if getting a "I don't > understand -mbig-endian" from gcc is more useful than getting it from > gas. And it would be more work for the user to fix it since then they

Re: [PATCH v2 0/5] RISC-V big endian support

Hi Marcus: Thanks for the quick update, I am testing your V2 patch now, the result seems really great now, some of fail case seems like not cause by big-endian patch, I am reviewing and comparing the fail case with the little-endian build. > Should I make a PR against riscv-newlib on GitHub, or w

Re: [PATCH v2 0/5] RISC-V big endian support

Seems like only 3 fail are related to big-endian, you don't need to worry about other fails. FAIL: gcc.c-torture/execute/string-opt-5.c FAIL: gcc.target/riscv/shift-and-1.c scan-assembler-not andi FAIL: gcc.target/riscv/shift-and-2.c scan-assembler-not andi On Tue, Feb 23, 2021 at 10:38 AM Kito C

Re: add rv64im{,c,fc} multilibs

Hi Alexandre: We've added a new configure option to allow you to override that without changing source code. For example: --with-multilib-generator="rv32i-ilp32--c;rv32im-ilp32--c;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f-rv32imafdc-;rv64im-lp64--;rv64imc-lp64--;rv64imfc-lp64f--;rv64imac-

Re: [PATCH] config.sub, config.guess : Import upstream 2021-01-25.

Committed, thanks! On Tue, Feb 23, 2021 at 4:18 PM Richard Biener wrote: > > On Tue, 23 Feb 2021, Kito Cheng wrote: > > > Hi > > > > Does it update config.sub and config.guess, I know it's already > > stage 4, but the config.* stuff update should be harmless things, > > and we need this for RISC-

Re: [PATCH v2 0/5] RISC-V big endian support

Hi Marcus: I just spend some time on those two testcase, I think this those two testcase could just skip in big-endinan. > FAIL: gcc.target/riscv/shift-and-1.c scan-assembler-not andi > FAIL: gcc.target/riscv/shift-and-2.c scan-assembler-not andi However seems like rv32be has still has some stra

Re: [PATCH v3 6/6] RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md

Hi Jim: Could you take a look for this patch, I am not sure it's the right change or not for big-endian, On Thu, Feb 25, 2021 at 6:39 AM Marcus Comstedt wrote: > > These all intend the least significant subpart of the register. > Use the same endian-neutral "subreg_lowpart_operator" predicate th

Re: [PATCH] RISC-V: Implment __builtin_thread_pointer

Hi Matthias: Sure, backported to gcc 10 branch, let's wait 10.3 :) On Mon, Mar 1, 2021 at 4:17 PM Matthias Klose wrote: > > On 7/8/20 9:59 PM, Jim Wilson wrote: > > On Tue, Jul 7, 2020 at 2:52 AM Kito Cheng wrote: > >> gcc/ChangeLog: > >> * gcc/config/riscv/riscv.md (): New. > >>

Re: [PATCH] RISC-V: Allow unaligned accesses in cpymemsi expansion

Hi Christoph: Generally LGTM, only 1 minor comment. > @@ -3292,8 +3294,17 @@ riscv_expand_block_move (rtx dest, rtx src, rtx length) >unsigned HOST_WIDE_INT hwi_length = UINTVAL (length); >unsigned HOST_WIDE_INT factor, align; > > - align = MIN (MIN (MEM_ALIGN (src), MEM_ALIG

Re: [PATCH] RISC-V: Enable overlap-by-pieces in case of fast unaliged access

HI Christoph: Could you submit v3 patch which is v1 with overlap_op_by_pieces field, testcase from v2 and add a few more comments to describe the field? And add an -mtune=ultra-size to make it able to test without change other behavior? Hi Palmer: Are you OK with that? On Sat, Aug 14, 2021 at

Re: [PATCH] RISC-V: Enable overlap-by-pieces in case of fast unaliged access

> > Could you submit v3 patch which is v1 with overlap_op_by_pieces field, > > testcase from v2 and add a few more comments to describe the field? > > > > And add an -mtune=ultra-size to make it able to test without change > > other behavior? > > > > Hi Palmer: > > > > Are you OK with that? > > I'm

Re: RISC-V: fix a typo in riscv.h

Hi Yeting: Could you provide a test case for that? On Mon, Sep 14, 2020 at 3:15 PM Yeting Kuo via Gcc-patches wrote: > > Hi all, > > The patch fixes a typo that would make some errors in fast-unaligned-access > targets. > > RISC-V: fix a typo in riscv.h > > 2020-09-14 Yeting Kuo > >

Re: [PATCH] RISC-V: Define __riscv_cmodel_medany for PIC mode.

Thanks, committed with more comments in code :) On Tue, Sep 29, 2020 at 3:35 AM Jim Wilson wrote: > > On Thu, Sep 24, 2020 at 10:46 PM Kito Cheng wrote: > > > > - According the conclusion in RISC-V C API document, we decide to deprecat > >the __riscv_cmodel_pic marco > > > > - __riscv_cmod

Re: [PATCH] RISC-V: Derive ABI from -march if -mabi is not present.

Hi Andreas: Thanks for your review, writing the document is my weakness ...:P On Tue, Oct 6, 2020 at 3:34 PM Andreas Schwab wrote: > > On Okt 06 2020, Kito Cheng wrote: > > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > > index f623467b7637..c6ba738aa0b7 100644 > > --- a/gcc/doc/invo

Re: [PATCH] RISC-V: Derive ABI from -march if -mabi is not present.

Hi Maciej: Thanks for sharing your experience on MIPS, that sounds like just opposite derived directions to this scheme. > The MIPS port used to have `-mcpu=' as well, which used to be roughly > equivalent to modern `-mtune='; from your description I gather `-mcpu=' is > going to be roughly equi

Re: [PATCH] RISC-V missing __builtin_lceil and __builtin_lfloor

LGTM, thanks, I guess I just missed this before Palmer Dabbelt 於 2022年9月17日 週六 23:07 寫道： > On Mon, 15 Aug 2022 17:44:35 PDT (-0700), kev...@rivosinc.com wrote: > > Hello, > > Currently, __builtin_lceil and __builtin_lfloor doesn't generate an > > existing instruction fcvt, but rather calls ceil

Re: [PATCH] RISC-V modified add3 for large stack frame optimization [PR105733]

Could you provide some data including code size and performance? add is frequently used patten, so we should more careful when changing that. Kevin Lee 於 2022年9月19日 週一，18:07寫道： > Hello GCC, > Started from Jim Wilson's patch in > > https://github.com/riscv-admin/riscv-code-speed-optimization/blob

Re: [PATCH] RISC-V: Support poly move manipulation and selftests.

Committed. thanks! On Thu, Sep 15, 2022 at 4:29 PM wrote: > > From: zhongjuzhe > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Change "static void" to "void". > * config.gcc: Add riscv-selftests.o > * config/riscv/predicates.md: Allow const_poly_int. >

Re: [PATCH] RISC-V: Suppress riscv-selftests.cc warning.

Committed, but squashed changes to "RISC-V: Support poly move manipulation and selftests." instead of a standalone commit. On Sat, Sep 17, 2022 at 9:00 AM wrote: > > From: Ju-Zhe Zhong > > This patch is a fix patch for: > https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601643.html > > S

Re: [PATCH] RISC-V: Add RVV machine modes.

Committed, thanks! On Thu, Sep 15, 2022 at 7:40 PM wrote: > > From: zhongjuzhe > > gcc/ChangeLog: > > * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add RVV mask modes. > (ADJUST_NUNITS): Adjust nunits using riscv_vector_chunks. > (ADJUST_ALIGNMENT): Adjust alignment.

Re: [PATCH] RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand

Committed with ChangeLog and minor naming tweaking. > But I'm not sure if the current checking of local symbol can be simplified > a bit. Isn't the first line enough for GET_CODE == const case too ? SYMBOL_REF_P not work for CONST, SYMBOL_REF_P is just checking GET_CODE is SYMBOL_REF, and SYMBOL

Re: [PATCH] RISC-V: Add ABI-defined RVV types.

Committed with few minor style tweaks :) On Tue, Sep 27, 2022 at 5:27 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config.gcc: Add riscv-vector-builtins.o. > * config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV > builtin function. > * config/riscv

Re: [V2 PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc.

Committed, but I decided to take v1 and disable that by default to prevent breaking the existing code :) On Tue, Sep 13, 2022 at 5:37 PM jiawei wrote: > > From: Jiawei > > Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option, > it will add csr-check in .option section and pass

Re: [PATCH v3] RISC-V: remove deprecate pic code model macro

Committed, and added ChangeLog, remember to add that next time :) On Sat, Sep 24, 2022 at 2:08 AM Vineet Gupta wrote: > > On 9/2/22 14:05, Vineet Gupta wrote: > > Came across this deprecated symbol when looking around for > > -mexplicit-relocs handling in code > > > > Signed-off-by: Vineet Gupta

Re: [PATCH] RISC-V: Introduce RVV header to enable builtin types

Committed, thanks :) On Fri, Sep 30, 2022 at 2:59 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config.gcc: Add riscv_vector.h. > * config/riscv/riscv-builtins.cc: Add RVV builtin types support. > * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): New functio

Re: [PATCH] RISC-V: Default to tuning for the thead-c906

-1 for this, default enable fast unaligned access could cause many problems, and lots of RISC-V cores don't support HW unaligned access (Rocket-base RISC-V core, most SiFive core, and most Andes core IIRC), change this to default means package from RISC-V linux distro might contain unaligned access

Re: [PATCH] RISC-V: Add missing vsetvl instruction type.

Committed, thanks :) On Mon, Oct 10, 2022 at 9:44 PM wrote: > > From: Ju-Zhe Zhong > > When implementing built-in framework, I notice I missed > vsetvl instruction type, so add it in a single patch > preparing for the following patches. > > gcc/ChangeLog: > > * config/riscv/riscv.md: Add

Re: [PATCH] RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name".

Committed, thanks :) On Mon, Oct 10, 2022 at 9:58 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc (struct vector_type_info): > Move from config/riscv/riscv-vector-builtins.h. > (DEF_RVV_TYPE): Change USER_NAME to NAME. > (r

Re: [PATCH] RISC-V: Refine riscv-vector-builtins.o include files and makefile.

I would suggest we do not include those header files unless we really need that. On Tue, Oct 11, 2022 at 2:32 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc: Change include files same as > ARM SVE. > * config/riscv/t-riscv: Refine

Re: [PATCH 4/5 V1] RISC-V:Implement testcases for Crypto extension

Just one general review comment for this patch: - Add newline at end of this file to prevent "\ No newline at end of file" in the git commit log - I saw you've skip -g and -flto, I guess that because that cause fail since -g or -flto might add few more line to make the scan-assembler-times, I would

Re: [PATCH 4/5 V1] RISC-V:Implement testcases for Crypto extension

> > diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c > > b/gcc/testsuite/gcc.target/riscv/zbkb64.c > > new file mode 100644 > > index 000..2cd76a29750 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c > > @@ -0,0 +1,21 @@ > > +/* { dg-do compile } */ > > +/* { dg-opti

Re: [PATCH] RISC-V:Add support for ZMMUL extension

LGTM for GCC 13, I'll commit that once stage 1 is open again. On Mon, Feb 14, 2022 at 10:26 AM wrote: > > From: LiaoShihua > > ZMMUL extension is Multiply only extension for RISC-V.It implements the > multiplication subset of the M extension. > The encodings are identical to those o

Re: [RFC v2] RISCV: Combine Pass Clobber Ops

Hi Patrick: There is few direction in my mind: 1. Model the C extension right in riscv.md 2. Write peephole2 pattern. 3. Implement a RISC-V specific register renaming pass. 1. Model the C extension right in riscv.md Currently we rely the GNU as to compress the instruction to C extension, and ac

Re: [PATCH] riscv: Allow -Wno-psabi to turn off ABI warnings [PR91229]

Hi Jakub: LGTM, Thanks! On Tue, Mar 15, 2022 at 6:57 PM Jakub Jelinek via Gcc-patches wrote: > > Hi! > > While checking if all targets honor -Wno-psabi for ABI related warnings > or messages, I found that almost all do, except for riscv. > In the testsuite when we want to ignore ABI related mess

Re: [PATCH] RISC-V: Handle combine extension in canonical ordering.

Hi Shi-Hua: Thanks, generally it's LGTM, just a few coding style issues. I've fixed that and committed this time, but just let you know where you should update your coding style. And you could use git clang-format and use /contrib/clang-format as format file to save your time to indent that. ht

Re: [PATCH] RISC-V: Implement ZTSO extension.

Hi Shi-Hua: Thanks, this patch is LGTM, but I would defer that until stage 1, because the binutils part isn't merget yet. On Tue, Mar 15, 2022 at 5:10 PM wrote: > > From: LiaoShihua > > ZTSO is the extension of tatol store order model. > This extension adds no new instructions to th

Re: [PATCH 3/3] RISC-V:Cache Management Operation instructions testcases

I would suggest rename those __builtin_riscv_* to __builtin_riscv_cmo_*, that's less confusing, __builtin_riscv_zero just seems like it will return a zero value. On Fri, Mar 4, 2022 at 10:52 AM wrote: > > From: yulong-plct > > This commit adds testcases about CMO instructions. > 7 > 8 gcc/t

Re: [PATCH 3/3] RISC-V:Cache Management Operation instructions testcases

> You meant cbo_zero, right? > CMO was only the task-group name, but the extensions ended up having "cbo" > in their name… Yeah, named with an extension name makes more sense, thank you for pointing that out. Either __builtin_riscv_cbo_zero or __builtin_riscv_zicboz_cbo_zero is fine to me since I

Re: [PATCH] RISC-V: Implement ZTSO extension.

Hi Palmer: Cool, so I keep that on the GCC 13 queue :) On Tue, Mar 22, 2022 at 10:41 AM Palmer Dabbelt wrote: > > On Mon, 21 Mar 2022 19:39:24 PDT (-0700), kito.ch...@sifive.com wrote: > > Hi Palmer: > > > > I guess the problem is binutils isn't included and it's too close to the > > GCC release

Re: 回复：[PATCH] Asan changes for RISC-V.

Arm 32, x86 (32) and mips has support for Asan[1], so we can `reference` how they implement that, but I guess the problem is we need someone to do that. [1] https://github.com/llvm/llvm-project/blob/main/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake#L28 On Thu, Apr 21, 2022 at 7:54 AM Pal

Re: [PATCH] Asan changes for RISC-V.

Hi Joshua: > Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is > still unsupported for RISC-V. If I add '--enable-libsanitizer' in Makefile.in > to reconfigure, there are compiling errors. Is it because # libsanitizer not supported rv32, but it will break the rv64 multi-

Re: [PATCH] riscv: fix -Wformat-diag errors.

Thanks Martin! On Wed, Jan 19, 2022 at 12:23 AM Martin Liška wrote: > > Pushed as pre-approved by Jeff. The patch fixes -Wformat-diag warnings. > > Martin > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc (riscv_subset_list::add): > Wrap keywords with quotes and remove

Re: [PATCH] RISC-V: Fix use-after-free error in `parse_multiletter_ext'

LGTM, thanks :) On Wed, Jan 19, 2022 at 12:59 AM Maciej W. Rozycki wrote: > > Avoid undefined arithmetic involving a pointer to a heap allocation that > has been freed and move a problematic calculation ahead of the following > call to `free' in `riscv_subset_list::parse_multiletter_ext', removin

Re: [PATCH] RISC-V: Document the degree of position independence that medany affords

LGTM, thanks for adding those comments :) On Wed, Jan 19, 2022 at 1:21 AM Palmer Dabbelt wrote: > > The code generated by -mcmodel=medany is defined to be > position-independent, but is not guaranteed to function correctly when > linked into position-independent executables or libraries. See the

Re: [PATCH] RISC-V: Update testcases info with new implement info

Committed, thanks! On Wed, Jan 19, 2022 at 5:18 PM Martin Liška wrote: > > On 1/19/22 10:15, shi...@iscas.ac.cn wrote: > > |From: LiaoShihua After commit > > 591b6e00d1bfe12932ca31530d5859f95db8a35a " riscv: fix -Wformat-diag errors > > ", some strings in implement was changed. This patch upda

Re: [PATCH v2] doc: RISC-V: Document the `-misa-spec=' option

Thanks, LGTM :) On Sat, Feb 5, 2022 at 7:56 AM Maciej W. Rozycki wrote: > > We have recently updated the default for the `-misa-spec=' option, yet > we still have not documented it nor its `--with-isa-spec=' counterpart > in the GCC manuals. Fix that. > > gcc/ > * doc/install.tex

Re: [PATCH] RISC-V: Always pass -misa-spec to assembler [PR104219]

Committed to trunk :) On Fri, Feb 4, 2022 at 8:56 PM Martin Liška wrote: > > May I please PING this? > > Thanks, > Martin > > On 1/25/22 14:04, Kito Cheng wrote: > > Add -misa-spec to OPTION_DEFAULT_SPECS to make sure -misa-spec will > > always pass that into assembler, that prevent GCC and binut

Re: [PATCH] RISC-V: Add target machine headers as a dependency for riscv-sr.o

OK to trunk, thanks for fixing this issue, I hit that issue before but I didn't figure out what happened...since that issue will disappear when I clean build :p On Tue, Feb 1, 2022 at 5:52 AM Maciej W. Rozycki wrote: > > Make riscv-sr.o depend on target machine headers, removing spurious test > f

Re: [PATCH] RISC-V/testsuite: Run target testing over all the usual optimization levels

Hi Maciej: Thanks for doing this, OK to trunk. On Tue, Feb 1, 2022 at 7:04 AM Maciej W. Rozycki wrote: > > Use `gcc-dg-runtest' test driver rather than `dg-runtest' to run the > RISC-V testsuite as several targets already do. Adjust test options > across individual test cases accordingly where

Re: [PATCH] doc: invoke: RISC-V: Clean up the -mstrict-align wording

LGTM, thanks :) On Tue, Feb 8, 2022 at 12:30 PM Palmer Dabbelt wrote: > > The polarity of do/do not was reversed for this option when compored to > the rest of them. This seems to have been copied from PowerPC, when the > polarity of the arguments in the docs was reversed (presumably to match >

Re: [PATCH] doc: invoke: RISC-V: Clean up the -memit-attribute wording

Hi Palmer: Seems like...you update the wrong part? you are updating -mmcount-ra-address/-mno-mcount-ra-address rather than -memit-attribute/ -mno-emit-attribute ? On Tue, Feb 8, 2022 at 12:30 PM Palmer Dabbelt wrote: > > The previous wording makes it sound like "do not emit" is a > clarification

Re: [PATCH] RISC-V: Add target machine headers as a dependency for riscv-sr.o

Hi Maciej: OK for release branches, thanks! On Tue, Feb 8, 2022 at 8:24 PM Maciej W. Rozycki wrote: > > On Mon, 7 Feb 2022, Kito Cheng wrote: > > > OK to trunk, thanks for fixing this issue, I hit that issue before but > > I didn't figure out what happened...since that issue will disappear > > w

Re: [PATCH 5/5 V1] RISC-V:Implement architecture extension test macros for Crypto extension

I would suggest implementing that in riscv_subset_list::parse so that it also affect the ELF attribute emission. On Wed, Feb 23, 2022 at 5:44 PM wrote: > > From: LiaoShihua > > gcc/ChangeLog: > > * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):Add __riscv_zks, > __riscv_zk, __riscv_z

Re: [PATCH 3/5 V1] RISC-V:Implement intrinsics for Crypto extension

Those header files have license issues that should relicinced to GPL, and don't put rvk_asm_intrin.h rvk_emu_intrin.h, since they are not too meaningful when we have compiler support. General comment: - Use /* */ rather than //, that gives much more compatibility, that is illegal for c89. - Add a

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