Re: [PATCH V2] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension

LGTM, thanks :) On Thu, Jul 13, 2023 at 4:33 PM Lehua Ding wrote: > > Hi, > > This tiny patch add a check for extension starts with 'z' or 's' in `-march` > option. Currently this unknown extension will be passed to the assembler, > which > then reports an error. With this patch, the compiler wi

Re: [PATCH] RISC-V: Refactor RVV machine modes

Thansk, that's really awesome! One comment about mode iterator is the naming seems like still prefixed with VNX which inconsistent with new mode naming scheme. > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index cd5b19457f8..03e19259505 100644 > --- a/gcc/config/riscv

Re: [PATCH V3] RISC-V: Refactor RVV machine modes

LGTM, I must say the number of modifications is less than my expect :) And it's a really big move for RVV implementation! Juzhe-Zhong 於 2023年7月20日 週四 07:22 寫道： > Current machine modes layout is hard to maintain && read && understand. > > For a LMUL = 1 SI vector mode: > 1. VNx1SI mode when TA

Re: [PATCH] RISC-V: Support in-order floating-point reduction

Seems like there is a potential vsetvli optimization chance in the example? > After this patch: > foo: > lui a5,%hi(.LC0) > flw fa0,%lo(.LC0)(a5) > ble a1,zero,.L4 > .L3: > vsetvli a5,a1,e32,m1,ta,ma > vle32.v v1,0(a0) > sllia4,a5,2 >

Re: Re: [PATCH] RISC-V: Support in-order floating-point reduction

Seems like because you ` using namespace riscv_vector;` so the UNORDERED in expand_vec_cmp_float used reduction_type::UNORDERED Hmmm, maybe enum class? enum class reduction_type { UNORDERED, FOLD_LEFT, MASK_LEN_FOLD_LEFT, }; and need use like this reduction_type::UNORDERED On Thu, Jul 20,

Re: Re: [PATCH] RISC-V: Support in-order floating-point reduction

reduction_type = reduction_type::UNORDERED On Thu, Jul 20, 2023 at 4:16 PM juzhe.zh...@rivai.ai wrote: > > I have tried this: > enum class reduction_type > { > UNORDERED, > FOLD_LEFT, > MASK_LEN_FOLD_LEFT, > }; > > But fail to build. > > /gcc/build -I../../../riscv-gcc/gcc/../include

Re: [PATCH V2] RISC-V: Support in-order floating-point reduction

LGTM, but I would like make sure Robin is OK too On Thu, Jul 20, 2023 at 4:51 PM Juzhe-Zhong wrote: > > This patch is depending on: > https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624995.html > > Consider this following case: > float foo (float *__restrict a, int n) > { > float result = 1

Re: [PATCH v3] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

LGTM, I think long jump is another issue and making ra become a fixed register will escalate to an ABI issue, so that should not be a blocker for this patch. On Tue, Jul 18, 2023 at 4:10 PM yanzhang.wang--- via Gcc-patches wrote: > > From: Yanzhang Wang > > gcc/ChangeLog: > > * config/ri

Re: [PATCH 1/2] Fix PR 110066: crash with -pg -static on riscv

OK for trunk, thanks:) Andrew Pinski via Gcc-patches 於 2023年7月23日 週日 09:07 寫道： > The problem -fasynchronous-unwind-tables is on by default for riscv linux > We need turn it off for crt*.o because it would make __EH_FRAME_BEGIN__ > point > to .eh_frame data from crtbeginT.o instead of the user-de

Re: [PATCH v2] RISC-V: Fixbug for fsflags instruction error using immediate.

Jin Ma via Gcc-patches 於 2023年7月25日 週二 15:29 寫道： > The pattern mistakenly believes that fsflags can use immediate numbers, > but in fact it does not support it. Immediate numbers should use fsflagsi. > > For example: > __builtin_riscv_fsflags(4); > > The following error occurred. > /tmp/ccoWdWqT.

Re: [PATCH v7] RISC-V: Support CALL for RVV floating-point dynamic rounding

Hi Robin: Give few more context about the design: The call fesetround could be any function in practice, and we never know if that function might use dynamic rounding mode floating point operation or not, also we don't know if it will be called fesetround or not. So that's why we want to restore

Re: [gcc13 backport 12/12] riscv: fix error: control reaches end of non-void function

OK for backport :) On Wed, Jul 26, 2023 at 2:11 AM Patrick O'Neill wrote: > > From: Martin Liska > > Fixes: > gcc/config/riscv/sync.md:66:1: error: control reaches end of non-void > function [-Werror=return-type] > 66 | [(set (attr "length") (const_int 4))]) >| ^ > > PR target/109

Re: Re: [PATCH v3] RISC-V: Fixbug for fsflags instruction error using immediate.

So I guess you should change `fscsr` to `fscsr%i0` instead of dropping K from the constraint list? On Wed, Jul 26, 2023 at 11:42 AM juzhe.zh...@rivai.ai wrote: > > I don't understand: > (define_insn "riscv_fscsr" > - [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSCSR)] >

Re: [PATCH v4] RISC-V: Fixbug for fsflags instruction error using immediate.

On Wed, Jul 26, 2023 at 1:41 PM Jin Ma via Gcc-patches wrote: > > The pattern mistakenly believes that fsflags can use immediate numbers, > but in fact it does not support it. Immediate numbers should use fsflagsi. > > For example: > __builtin_riscv_fsflags(4); > > The following error occurred. >

Re: Re: [PATCH v4] RISC-V: Fixbug for fsflags instruction error using immediate.

Oh, yeah, my bad, there is no fscsri, gonna test and push :) On Wed, Jul 26, 2023 at 3:20 PM juzhe.zh...@rivai.ai wrote: > > I just checked SPEC: > > fscsr rd, rs csrrw rd, fcsr, rs > Swap FP control/status register > fscsr rs csrrw x0, fcsr, rs > Write FP control/status register > > It seems tha

Re: RISC-V: Replace unspec with bitreverse in riscv_brev8_ insn

My understanding is the semantic is slightly different, brev8 is only the bit reverse within each byte, but bitreverse means did bit reverse for the whole content of the mode, e.g. riscv_brev8_si will bit reserved within 32 bit. Using RV32 as example: UNSPEC_BREV8: rd[0...7] = rs[7...0] rd[8...15

Re: Re: [PATCH v4] RISC-V: Fixbug for fsflags instruction error using immediate.

commit, thanks :) On Wed, Jul 26, 2023 at 3:39 PM Kito Cheng wrote: > > Oh, yeah, my bad, there is no fscsri, gonna test and push :) > > On Wed, Jul 26, 2023 at 3:20 PM juzhe.zh...@rivai.ai > wrote: > > > > I just checked SPEC: > > > > fscsr rd, rs csrrw rd, fcsr, rs > > Swap FP control/status r

Re: [PATCH] RISC-V: Fix vector tuple intrinsic

OK, thanks On Wed, Jul 26, 2023 at 4:22 PM juzhe.zh...@rivai.ai wrote: > > LGTM from my side. > > It should be V3 though, never mind. > No need to send V3 again. > > Give kito a chance chime in for more comments. > > > juzhe.zh...@rivai.ai > > > From: Li Xu > Date

Re: [PATCH v7] RISC-V: Support CALL for RVV floating-point dynamic rounding

Sorry for late ack on the LLVM part, I can say they are did the same model/semantics, it done by our team member too, and I have regular meeting with that guy :P Robin Dapp via Gcc-patches 於 2023年7月26日 週三，21:47寫道： > > current llvm didn't do any pre optimization. They always > > backup+restore fo

Re: [PATCH v7] RISC-V: Support CALL for RVV floating-point dynamic rounding

CSR write could be expensive, it will flush whole pipeline in some RISC-V core implementation… Kito Cheng 於 2023年7月26日 週三，21:57寫道： > Sorry for late ack on the LLVM part, I can say they are did the same > model/semantics, it done by our team member too, and I have regular meeting > with that guy :

Re: Re: [PATCH v7] RISC-V: Support CALL for RVV floating-point dynamic rounding

I would say LCM/PRE is the key of this set of static rounding model intrinsic, otherwise I think it's will push people to using dynamic with fesetrouding mode or inline asm to set the rounding mode for performance issue - it's kind of opposite way of the design concept, we want to provide a reliabl

Re: [PATCH V2] RISC-V: Enable basic VLS modes support

Hi Juzhe-Zhong: Only > diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md > new file mode 100644 > index 000..c67ff386e50 > --- /dev/null > +++ b/gcc/config/riscv/autovec-vls.md > +(define_insn_and_split "mov" > + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem

Re: [PATCH V2] RISC-V: Enable basic VLS modes support

Ooops, I just click send too fast, I want to say "Only few minor comment on the md file" On Thu, Jul 27, 2023 at 2:52 PM Kito Cheng wrote: > > Hi Juzhe-Zhong: > > Only > > > diff --git a/gcc/config/riscv/autovec-vls.md > > b/gcc/config/riscv/autovec-vls.md > > new file mode 100644 > > index

Re: [PATCH V3] RISC-V: Enable basic VLS modes support

Last minor thing :) > +(define_insn_and_split "*mov" > + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr") > + (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))] > + "TARGET_VECTOR" Reject (set (mem) (mem)) by adding the check: TARGET_VECTOR && (registe

Re: Re: [PATCH V3] RISC-V: Enable basic VLS modes support

Hmmm, does it mean we'll have (set (mem) (mem)) after legitimize_move??? Or maybe try to use define_insn_and_split rather than define_split for the (set (mem) (mem)) On Thu, Jul 27, 2023 at 5:50 PM juzhe.zh...@rivai.ai wrote: > > Hi, kito. > I tried to reject mem->mem in this pattern: > (define

Re: [PATCH v1] RISC-V: Remove unnecessary vread_csr/vwrite_csr intrinsic.

Ok, thanks:) Pan Li via Gcc-patches 於 2023年7月27日 週四 18:45 寫道： > From: Pan Li > > According to below RVV doc, the related intrinsic is not longer needed. > > https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/249 > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/riscv

Re: [PATCH v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks.

LGTM, I just found this patch still on the list, I mostly tested with qemu, so I don't think that is a problem before, but I realize it's a problem when we run on a real board that does not support those extensions. On Sun, Jun 18, 2023 at 6:07 AM Jeff Law via Gcc-patches wrote: > > > > On 6/15/2

Re: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative

My first impression is those emit_insn (gen_rtx_SET()) seems necessary, but I got the point after I checked vector.md :P Committed to trunk, thanks :) On Thu, Jul 27, 2023 at 6:23 PM juzhe.zh...@rivai.ai wrote: > > Oh, YES. > > Thanks for fixing it. It makes sense since the ternary operations i

Re: [PATCH] RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u]

I didn't checked with rvv intrinsic spec, but I assume this is found during test with api test, so LGTM, thanks for fixing this:) juzhe.zh...@rivai.ai 於 2023年7月28日 週五 14:43 寫道： > Thanks for fixing it. > LGTM from my side. > > > > juzhe.zh...@rivai.ai > > From: Li Xu > Date: 2023-07-28 13:52 > To

Re: [PATCH v2] RISC-V: convert the mulh with 0 to mov 0 to the reg.

於 2023年7月28日 週五 19:50 寫道： > From: Yanzhang Wang > > This patch will optimize the below mulh example, > > vint32m1_t shortcut_for_riscv_vmulh_case_0(vint32m1_t v1, size_t vl) { > return __riscv_vmulh_vx_i32m1(v1, 0, vl); > } > > from mulh pattern > > vsetvli zero, a2, e32, m1, ta, ma > vmulh.

Re: [PATCH] RISC-V: Enable basic VLS auto-vectorization

Hi Juzhe: > * config/riscv/riscv.cc (riscv_estimated_poly_value): Fix incorrect > poly estimation. Is it a necessary change for the VLS autovectorizaion or could it be a separate change??

Re: [PATCH V2] RISC-V: Enable basic VLS auto-vectorization

LGTM, thanks :) On Mon, Jul 31, 2023 at 10:14 AM Juzhe-Zhong wrote: > > Consider this following case: > void > foo (int8_t *in, int8_t *out, int8_t x) > { > for (int i = 0; i < 16; i++) > in[i] = x; > } > > Compile option: --param=riscv-autovec-preference=scalable -fno-builtin > > Before th

Re: [PATCH v1] RISC-V: Bugfix for RVV floating-point rm suffix sequence

lgtm On Mon, Jul 31, 2023 at 10:56 AM wrote: > > From: Pan Li > > According to below RVV intrinsic doc, the RVV floating-point intrinsic name > with rounding mode should be: > > _rm_m > > instead of: > > _m_rm > > https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226 > > This patch fix thi

[PATCH] RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC

We always want get_mask_mode return a valid mode, it's something wrong if it failed, so I think we could just move the `.require ()` into get_mask_mode, instead of calling that every call-site. The only exception is riscv_get_mask_mode, it might put supported mode into get_mask_mode, so added a ch

Re: [PATCH] RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC

Pushed, thanks :) On Mon, Jul 31, 2023 at 2:59 PM juzhe.zh...@rivai.ai wrote: > > ok > > > > juzhe.zh...@rivai.ai > > From: Kito Cheng > Date: 2023-07-31 14:52 > To: gcc-patches; kito.cheng; juzhe.zhong; rdapp.gcc; pan2.li > CC: Kito Cheng > Subject: [PATCH] RISC-V: Return machine_mode rather tha

Re: [committed] RISC-V: Fix bug of get_mask_mode

Ooops, I guess my code base was too old, and forgot to check that after rebase, thanks for fix that! Juzhe-Zhong 於 2023年7月31日 週一，20:21寫道： > Fix bugs: > ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc: In function ‘void > riscv_vector::emit_vlmax_masked_fp_mu_insn(unsigned int, int, rtx_def**)’: >

Re: [PATCH] RISC-V: Support POPCOUNT auto-vectorization

On Mon, Jul 31, 2023 at 8:03 PM Juzhe-Zhong wrote: > > This patch is inspired by "lowerCTPOP" in LLVM. > Support popcount auto-vectorization by following LLVM approach. > https://godbolt.org/z/3K3GzvY7f > > Before this patch: > > :7:21: missed: couldn't vectorize loop > :8:14: missed: not vectoriz

Re: [committed] RISC-V: Fix bug of get_mask_mode

I saw you didn't push yet, so I pushed another patch to fix those unused variable issues. On Mon, Jul 31, 2023 at 9:12 PM Kito Cheng wrote: > > Ooops, I guess my code base was too old, and forgot to check that after > rebase, thanks for fix that! > > Juzhe-Zhong 於 2023年7月31日 週一，20:21寫道： >> >> Fi

Re: [PATCH] RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC

Hi Maciej: Sorry for disturbing, pushed a fix for that, and...added -Werror=unused-variable to my build script to prevent that happen again :( On Mon, Jul 31, 2023 at 7:08 PM Maciej W. Rozycki wrote: > > On Mon, 31 Jul 2023, Kito Cheng via Gcc-patches wrote: > > > Pushed, than

Re: [PATCH] RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC

On Mon, Jul 31, 2023 at 10:03 PM Maciej W. Rozycki wrote: > > On Mon, 31 Jul 2023, Kito Cheng wrote: > > > Sorry for disturbing, pushed a fix for that, and...added > > -Werror=unused-variable to my build script to prevent that happen > > again :( > > I just configure with `--enable-werror-always'

Re: [PATCH v8] RISC-V: Support CALL for RVV floating-point dynamic rounding

Hi Pan: Thanks for your effort on this, this is LGTM and OK for trunk. Hi Robin: Thanks for your review on this stuff, this set of intrinsic functions is complicated and might be controversial since the whole floating point rounding mode is…complicated, and people might have different tastes

Re: [PATCH v1] RISC-V: Support RVV VFWSUB rounding mode intrinsic API

LGTM, thanks:) Pan Li via Gcc-patches 於 2023年8月2日 週三 18:19 寫道： > From: Pan Li > > This patch would like to support the rounding mode API for the VFWSUB > for the below samples. > > * __riscv_vfwsub_vv_f64m2_rm > * __riscv_vfwsub_vv_f64m2_rm_m > * __riscv_vfwsub_vf_f64m2_rm > * _

Re: [PATCH 1/1 V3] RISC-V: Support Zmmul extension

On Mon, Jul 11, 2022 at 3:15 PM wrote: > > From: LiaoShihua > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: > * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): > * config/riscv/riscv-opts.h (MASK_ZMMUL): > (TARGET_ZMMUL): > * config/riscv/ri

Re: [PATCH 1/1 V4] RISC-V: Support Zmmul extension

> gcc\ChangeLog: It's minor but that should be gcc/ChangeLog rather than gcc\ChangeLog: > > gcc\testsuite\ChangeLog: Same here. > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -4999,10 +4999,14 @@ riscv_option_override (void) >/* The presence of the M extension impl

Re: [PATCH] RISC-V: Add RTX costs for `if_then_else' expressions

Hi Maciej: LGTM, thanks for modeling this in cost model! On Tue, Jul 19, 2022 at 12:48 AM Maciej W. Rozycki wrote: > > Fix a performance regression from commit 391500af1932 ("Do not ignore > costs of jump insns in combine."), a part of the m68k series for MODE_CC > conversion (

Re: [PATCH 1/1 V5] RISC-V: Support Zmmul extension

LGTM, will merge once binuils part merge. On Wed, Jul 13, 2022 at 10:14 AM wrote: > > From: LiaoShihua > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Add Zmmul. > * config/riscv/riscv-opts.h (MASK_ZMMUL): New. > (TARGET_ZMMUL): Ditto. > * config/ris

Re: [PATCH v3] RISC-V/testsuite: constraint some of tests to hard_float

> On 5/29/22 20:50, Kito Cheng via Gcc-patches wrote: > > Committed, thanks! > > Can this be backported to gcc-12 please. I want to say yes but 9ddd44b58649d1d ("RISC-V: Provide `fmin'/`fmax' RTL pattern") only existing in the trunk, and gcc.target/riscv/

Re: [PATCH v1 1/3] RISC-V: Split "(a & (1 << BIT_NO)) ? 0 : -1" to bexti + addi

Hi Philipp: This patch series is LGTM, but plz introduce new pseudo when can_create_pseudo_p like what we discussed in https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596305.html, you can commit with the change with a [committed] patch mail :) On Thu, Jun 16, 2022 at 5:32 PM Philipp Tomsich

Re: [PATCH 1/1 V5] RISC-V: Support Zmmul extension

On Fri, Jul 22, 2022 at 2:43 AM Palmer Dabbelt wrote: > > On Thu, 21 Jul 2022 02:03:35 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > > LGTM, will merge once binuils part merge. > > +Nelson, in case he's already planning on handling those. If not then > they're not in my inbox, so just poke me if

Re: [PATCH] RISC-V: Remove duplicate backslashes from `stack_protect_set_'

Hi Maciej: Ooops, thanks for fixing that, the change was gotten from kernel folks. I assume they have already used that for a while, but it's really weird no bug report from those guys... OK for trunk and backport for release branch. On Wed, Jul 27, 2022 at 1:00 AM Maciej W. Rozycki wrote: > >

Re: [PING][PATCH v2] RISC-V: Split unordered FP comparisons into individual RTL insns

Hi Maciej: I am convinced that is OK for now, I agree modeling fflags would be a rabbit hole, I tried to build a full GNU toolchain with my quick patch and saw many ICE during build libraries, that definitely should be a long-term optimization project. Although I'm thinking if we should default -

Re: [PATCH] RISC-V: Use the X iterator for eh_set_lr_{si,di}

LGTM, thanks! On Sun, Aug 7, 2022 at 3:42 AM Palmer Dabbelt wrote: > > These two patterns were independent, but exactly match the semantics of > X. Replace them with a single paramaterized pattern. Thanks to Andrew > for pointing this one out over IRC. > > gcc/ChangeLog > > * config/ris

Re: [PATCH] RISC-V: Fix the sge ..., x0, ... pattern

LGTM, that's apparently some kind of copy & paste error (from *slt pattern) when we add this pattern. On Sun, Aug 7, 2022 at 3:42 AM Palmer Dabbelt wrote: > > There's no operand 2 here, so referencing it doesn't make sense. I > couldn't find a way to trigger bad assembly output so I don't have a

Re: [PATCH] RISC-V/testsuite: Restrict remaining `fmin'/`fmax' tests to hard float

LGTM, thanks :) On Fri, Jul 29, 2022 at 3:52 AM Maciej W. Rozycki wrote: > > Complement commit 7915f6551343 ("RISC-V/testsuite: constraint some of > tests to hard_float") and also restrict the remaining `fmin'/`fmax' > tests to hard-float test configurations. > > gcc/testsuite/ >

Re: [PATCH] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU

LGTM, but with a nit, I don't get set.w but get an andi like below, so maybe we should also scan-assembler-not andi? feel free to commit that directly with that fix ```asm sleu: sgtua0,a0,a1# 9 [c=4 l=4] *sgtu_disi xoria0,a0,1 # 10[c=4 l=4] *xorsi3_internal/

Re: [PATCH v1] RISC-V: Remove redudant extern declaration in function base

LGTM 於 2023年8月3日 週四 10:11 寫道： > From: Pan Li > > This patch would like to remove the redudant declaration. > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-bases.h: Remove > redudant declaration. > --- > gcc/config/riscv/riscv-vector-builti

Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

I am working on that, it seems the cost of vsetvli instruction become 0 due to this change, then loop invariant motion won't hoist vsetvli longer. Jeff Law 於 2023年8月3日 週四 21:49 寫道： > > > On 8/3/23 03:27, juzhe.zh...@rivai.ai wrote: > > > https://github.com/gcc-mirror/gcc/commit/e15d0b6680d10d766

Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

> > I am working on that, it seems the cost of vsetvli instruction become 0 > > due to this change, then loop invariant motion won't hoist vsetvli longer. > I haven't looked yet (generating baseline rvv.exp data right now). But > before I went to bed last night I was worried that a change snuck >

Re: [PATCH v1] RISC-V: Fix one comment for binop_frm insn

lgtm On Thu, Aug 3, 2023 at 10:32 PM wrote: > > From: Pan Li > > The previous patch missed the vfsub comment for binop_frm, this > patch would like to fix this. > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-bases.cc: Add vfsub. > --- > gcc/config

Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

> >> That'll be the first thing to look at. THe costing change was supposed > >> only affect if-then-else constructs, not sets in general. > > > > > > If so, I think the most simple fix is adding more checks on the set > > cost - only check the SET_SRC is if-then-else? > No, the simple fix is to j

Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic

What about using similar way as vlmul? # NOTE: diff is based on your patch. [kitoc@hsinchu02 riscv]$ git diff diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 33f7cb1d670..3cb5c23cb09 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-pro

Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic

A build-able patch attached, again, it's based on your patch :) On Mon, Aug 7, 2023 at 11:46 AM Li, Pan2 via Gcc-patches wrote: > > I am not quite sure if I understand it correctly, but I bet below enums are > required by RISC-V mode switching, like FRM_MODE_DYN in entry, or > FRM_MODE_CALL/EXI

Re: [PATCH 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed

> + machine_mode m1_mode = TARGET_VECTOR_ELEN_64 > + ? (TARGET_MIN_VLEN >= 128 ? VNx2DImode : > VNx1DImode) > + : VNx1SImode; This should update since JuZhe has update the mode system :P > @@ -5907,7 +6057,7 @@ riscv_expand_epilogue (int style)

Re: [PATCH 1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns

Thanks for the high quality patch, it's generally LGTM, only a few minor comments :) > + /* The number and alignment of vector registers need for this scalable > vector > + argument. When the mode size is less than a full vector, we use 1 vector > + register to pass. Just call TARGET_HAR

Re: [PATCH] RISC-V: Support VLS shift vectorization

Lgtm Juzhe-Zhong 於 2023年8月8日 週二，09:37寫道： > After this patch, this following case will be well optimized: > #include "riscv_vector.h" > > #define DEF_OP_VV(PREFIX, NUM, TYPE, OP) > \ > void __attribute__ ((noinline, noclone)) > \ > PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restri

Re: [PATCH] RISC-V: Support neg VLS auto-vectorization

LGTM :) Juzhe-Zhong 於 2023年8月8日 週二 11:10 寫道： > #include "riscv_vector.h" > > #define DEF_OP_V(PREFIX, NUM, TYPE, OP) > \ > void __attribute__ ((noinline, noclone)) > \ > PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) > \ > { > \ > for (int i = 0; i < NUM; ++

Re: [PATCH V1] RISC-V: Fix a bug that causes an error insn.

OK for trunk and GCC 13 :) On Tue, Aug 8, 2023 at 2:46 PM juzhe.zh...@rivai.ai wrote: > > LGTM. Thanks for fixing it. > > @kito: Hi, kito. This is the bug also exists in GCC-13, can we backport to > GCC-13? > > > > juzhe.zh...@rivai.ai > > From: shiyulong > Date: 2023-08-08 12:12 > To: gcc-patch

Re: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic

> +/* Get the frm mode with given CONST_INT rtx, the default mode is > + FRM_DYN. */ > +enum floating_point_rounding_mode > +get_frm_mode (rtx operand) > +{ > + gcc_assert (CONST_INT_P (operand)); > + > + switch (INTVAL (operand)) > +{ > +case FRM_RNE: > + return FRM_RNE; > +c

Re: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic

Yeah, no further comment from me :) On Thu, Aug 10, 2023 at 10:16 AM Li, Pan2 wrote: > > Thanks kito. It makes sense, should not reach default, may I prepare v3(add > gcc_unreachable to default) if no more comments? > > Pan > > -Original Message- > From: Kito Cheng > Sent: Thursday, Aug

Re: [PATCH v3] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic

LGTM 於 2023年8月10日 週四 11:12 寫道： > From: Pan Li > > The frm_mode attr has some assumptions for each define insn as below. > > 1. The define insn has at least 9 operands. > 2. The operands[9] must be frm reg. > 3. The operands[9] must be const int. > > Actually, the frm operand can be operands[8],

Re: [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API

LGTM On Thu, Aug 10, 2023 at 4:20 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to support the rounding mode API for the > VFNMACC for the below samples. > > * __riscv_vfnmacc_vv_f32m1_rm > * __riscv_vfnmacc_vv_f32m1_rm_m > * __riscv_vfnmacc_vf_f32m1_rm > * __riscv_

Re: [PATCH V2] RISC-V: Allow CONST_VECTOR for VLS modes

LGTM Juzhe-Zhong 於 2023年8月11日 週五 17:56 寫道： > This patch enables COSNT_VECTOR for VLS modes. > > void foo1 (int * __restrict a) > { > for (int i = 0; i < 16; i++) > a[i] = 8; > } > > void foo2 (int * __restrict a) > { > for (int i = 0; i < 16; i++) > a[i] = i; > } > > Compile

Re: [PATCH v1] RISC-V: Support RVV VFREC7 rounding mode intrinsic API

> +template You don't need a template class here since it can only be UNSPEC_VFREC7. > +class vfrec7_frm : public function_base > +{ > +public: > + bool has_rounding_mode_operand_p () const override { return true; } > + > + rtx expand (function_expander &e) const override > + { > +return e

Re: [PATCH v2 0/3] RISC-V: Support ZC* extensions.

Pushed to the trunk, with slight updates like rename and update testcases :) On Wed, Jun 7, 2023 at 10:28 PM Kito Cheng via Gcc-patches wrote: > > Thanks Jiawei, v2 patch set are LGTM, but I would like to defer this until > binutils part has merged, I know you guys already implement t

Re: [PATCH v1] RISC-V: Support RVV VFREC7 rounding mode intrinsic API

Checked with doc and llvm implementation, LGTM

Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API

Just a random idea came to my mind, maybe we could introduce one more template argument to reduce those codes for rounding mode intrinsic stuff? example: diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 2074dac0f16..9cc60842a5b 1

Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API

Or using an enum value rather than bool? I am thinking we could also simplify/remove most other frm classes, some practical example: diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 2074dac0f16..ace63e963a5 100644 --- a/gcc/conf

Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API

I would prefer to introduce an enum template argument and refactor existing code later :) On Wed, Aug 16, 2023 at 11:40 AM Li, Pan2 via Gcc-patches wrote: > > That should work as well, but may require some changes to existing codes like > declaration, etc. > I am OK for both the enum or inherit,

Re: [PATCH v2] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API

LGTM 於 2023年8月16日 週三 13:17 寫道： > From: Pan Li > > This patch would like to support the rounding mode API for the > VFCVT.X.F.V as the below samples. > > * __riscv_vfcvt_x_f_v_i32m1_rm > * __riscv_vfcvt_x_f_v_i32m1_rm_m > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/ris

Re: [PATCH v2] RISC-V: Support RVV VFCVT.XU.F.V rounding mode intrinsic API

lgtm On Wed, Aug 16, 2023 at 2:21 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to support the rounding mode API for the > VFCVT.XU.F.V as the below samples. > > * __riscv_vfcvt_xu_f_v_u32m1_rm > * __riscv_vfcvt_xu_f_v_u32m1_rm_m > > Signed-off-by: Pan Li > > gcc/C

Re: [PATCH v2] RISC-V: Support RVV VFCVT.F.X.V and VFCVT.F.XU.V rounding mode intrinsic API

lgtm On Wed, Aug 16, 2023 at 2:51 PM wrote: > From: Pan Li > > This patch would like to support the rounding mode API for the > VFCVT.F.X.V and VFCVT.F.XU.V as the below samples. > > * __riscv_vfcvt_f_x_v_f32m1_rm > * __riscv_vfcvt_f_x_v_f32m1_rm_m > * __riscv_vfcvt_f_xu_v_f32m1_rm > * __riscv_

Re: [PATCH v2] RISC-V: Support RVV VFWCVT.X.F.V rounding mode intrinsic API

lgtm On Wed, Aug 16, 2023 at 3:32 PM wrote: > From: Pan Li > > This patch would like to support the rounding mode API for the > VFWCVT.X.F.V as the below samples. > > * __riscv_vfwcvt_x_f_v_i64m2_rm > * __riscv_vfwcvt_x_f_v_i64m2_rm_m > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > *

Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp

Hi Fei: Tried to use Jiawei's patch to test this patch and found some issue: > @@ -5430,13 +5632,15 @@ riscv_expand_prologue (void) >/* Save the registers. */ >if ((frame->mask | frame->fmask) != 0) > { > - HOST_WIDE_INT step1 = riscv_first_stack_step (frame, remaining_size);

Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp

Another fail case for CFI: $ riscv64-unknown-elf-gcc _mulhc3.i -march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -g -O2 -o _mulhc3.s typedef float a __attribute__((mode(HF))); b, c; f() { a a, d, e = a + d; if (g() && e) c = b; } 0x10e508a maybe_record_trace_start ../../../../r

Re: [PATCH v1] RISC-V: Fix one build error for template default arg

ok On Wed, Aug 16, 2023 at 5:44 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > In some build option combination, the default value may result in > below error. This patch would like to fix it by passing a explict > argument. > > riscv-vector-builtins-bases.cc:2495:24: error: invalid use o

Re: [PATCH v2] RISC-V: Support RVV VFWCVT.XU.F.V rounding mode intrinsic API

ok On Wed, Aug 16, 2023 at 4:10 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to support the rounding mode API for the > VFWCVT.X.F.V as the below samples. > > * __riscv_vfwcvt_xu_f_v_u64m2_rm > * __riscv_vfwcvt_xu_f_v_u64m2_rm_m > > Signed-off-by: Pan Li > > gcc/C

Re: [PATCH v1] RISC-V: Support RVV VFNCVT.XU.F.W rounding mode intrinsic API

LGTM On Thu, Aug 17, 2023 at 9:23 AM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to support the rounding mode API for the > VFNCVT.XU.F.W as the below samples. > > * __riscv_vfncvt_xu_f_w_u16mf2_rm > * __riscv_vfncvt_xu_f_w_u16mf2_rm_m > > Signed-off-by: Pan Li > >

Re: [PATCH v1] RISC-V: Support RVV VFNCVT.F.{X|XU|F}.W rounding mode intrinsic API

Lgtm Pan Li via Gcc-patches 於 2023年8月17日 週四，10:19寫道： > From: Pan Li > > This patch would like to support the rounding mode API for the > VFNCVT.F.{X|XU|F}.W as the below samples. > > * __riscv_vfncvt_f_x_w_f32m1_rm > * __riscv_vfncvt_f_x_w_f32m1_rm_m > * __riscv_vfncvt_f_xu_w_f32m1_rm > * __risc

Re: [PATCH v1] RISC-V: Support RVV VFREDUSUM.VS rounding mode intrinsic API

Lgtm Pan Li via Gcc-patches 於 2023年8月17日 週四，11:09寫道： > From: Pan Li > > This patch would like to support the rounding mode API for the > VFREDUSUM.VS as the below samples. > > * __riscv_vfredusum_vs_f32m1_f32m1_rm > * __riscv_vfredusum_vs_f32m1_f32m1_rm_m > > Signed-off-by: Pan Li > > gcc/Chang

Re: [PATCH] RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037]

LGTM, thanks :) On Thu, Aug 17, 2023 at 1:59 PM Juzhe-Zhong wrote: > > void foo(_Float16 y, int64_t *i64p) > { > vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1); > vx = __riscv_vadd_vv_i64m1 (vx, vx, 1); > vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1); > asm volatile ("# use %0 %1" : : "v

Re: [PATCH v1] RISC-V: Support RVV VFWREDOSUM.VS rounding mode intrinsic API

ok On Thu, Aug 17, 2023 at 3:26 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to support the rounding mode API for the > VFWREDOSUM.VS as the below samples > > * __riscv_vfwredosum_vs_f32m1_f64m1_rm > * __riscv_vfwredosum_vs_f32m1_f64m1_rm_m > > Signed-off-by: Pan L

Re: [PATCH v1] RISC-V: Support RVV VFREDOSUM.VS rounding mode intrinsic API

lgtm On Thu, Aug 17, 2023 at 2:23 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to support the rounding mode API for the > VFREDOSUM.VS as the below samples. > > * __riscv_vfredosum_vs_f32m1_f32m1_rm > * __riscv_vfredosum_vs_f32m1_f32m1_rm_m > > Signed-off-by: Pan L

Re: [PATCH v1] RISC-V: Refactor RVV class by frm_op_type template arg

Just one nit from me: plz add assertion to OP_TYPE_vx to make sure NO FRM_OP == HAS_FRM there On Mon, Aug 21, 2023 at 11:04 PM Jeff Law via Gcc-patches wrote: > > > > On 8/17/23 20:53, Pan Li via Gcc-patches wrote: > > From: Pan Li > > > > As suggested by kito, we will add new frm_opt_type templ

Re: [PATCH] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS

I think I could do some details review tomorrow on the plane, I am free from the meeting hell tomorrow :p Robin Dapp via Gcc-patches 於 2023年8月21日 週一 23:24 寫道： > Hi Juzhe, > > thanks, this is a reasonable approach and improves readability noticeably. > LGTM but I'd like to wait for other opinio

Re: [PATCH] RISC-V: Remove redundant vcond patterns

ok for trunk, thanks :) On Mon, Jun 26, 2023 at 4:44 PM Richard Biener via Gcc-patches wrote: > > On Mon, 26 Jun 2023, Juzhe-Zhong wrote: > > > Previously, Richi has suggested that vcond patterns are only needed when > > target > > support comparison + select consuming 1 instruction. > > > > Now

Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization

Could you re-title this patch into something like "Support const vector expansion with xxx pattern", On Mon, Jun 26, 2023 at 3:52 PM Robin Dapp via Gcc-patches wrote: > > Hi Juzhe, > > > Currently, we are able to generate step vector with base == 0: > > { 0, 0, 2, 2, 4, 4, ... } > > > > ASM: > >

Re: [PATCH v1] RISC-V: Remove duplicated extern function_base decl

Lgtm juzhe.zh...@rivai.ai 於 2023年6月26日 週一，17:40寫道： > LGTM > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-26 17:36 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; > kito.cheng > Subject: [PATCH v1] RISC-V: Remove duplicated extern function_base

Re: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

LLVM will try to find scratch register even after RA to resolve the long jump issue. so maybe we could consider similar approach? And I guess the most complicate part would be the scratch register is not found, and require spill/reload after RA. Jeff Law via Gcc-patches 於 2023年6月26日 週一，22:31寫道： >

Re: [PATCH] RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering

It seems because of canonical form of RTL, right? LGTM, but plz add some more comments about the reason into the commit log. On Wed, Jun 28, 2023 at 11:00 AM Juzhe-Zhong wrote: > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-bases.cc: Adapt expand. > * config/riscv/ve

Re: [PATCH V2] RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering

LGTM with a minor comment. > Currently, vfwadd.wv is the pattern with (set (reg) (float_extend:(reg)) > which makes it's minor so you can just go commit after the fix: this should be (set (plus (reg) (float_extend:(reg))) > combine pass faile to combine. > > change RTL format of vfwadd.wv -

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