LGTM
On Thu, Aug 10, 2023 at 4:20 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2...@intel.com>
>
> This patch would like to support the rounding mode API for the
> VFNMACC for the below samples.
>
> * __riscv_vfnmacc_vv_f32m1_rm
> * __riscv_vfnmacc_vv_f32m1_rm_m
> * __riscv_vfnmacc_vf_f32m1_rm
> * __riscv_vfnmacc_vf_f32m1_rm_m
>
> Signed-off-by: Pan Li <pan2...@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (class vfnmacc_frm): New class for vfnmacc.
> (vfnmacc_frm_obj): New declaration.
> (BASE): Ditto.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfnmacc_frm): New function definition.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-nmacc.c: New test.
> ---
> .../riscv/riscv-vector-builtins-bases.cc | 24 ++++++++++
> .../riscv/riscv-vector-builtins-bases.h | 1 +
> .../riscv/riscv-vector-builtins-functions.def | 2 +
> .../riscv/rvv/base/float-point-nmacc.c | 47 +++++++++++++++++++
> 4 files changed, 74 insertions(+)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 1695d77e8bd..1d4a5a18bf9 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -379,6 +379,28 @@ public:
> }
> };
>
> +/* Implements below instructions for frm
> + - vfnmacc
> +*/
> +class vfnmacc_frm : public function_base
> +{
> +public:
> + bool has_rounding_mode_operand_p () const override { return true; }
> +
> + bool has_merge_operand_p () const override { return false; }
> +
> + rtx expand (function_expander &e) const override
> + {
> + if (e.op_info->op == OP_TYPE_vf)
> + return e.use_ternop_insn (
> + true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
> + if (e.op_info->op == OP_TYPE_vv)
> + return e.use_ternop_insn (
> + true, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
> + gcc_unreachable ();
> + }
> +};
> +
> /* Implements vrsub. */
> class vrsub : public function_base
> {
> @@ -2144,6 +2166,7 @@ static CONSTEXPR const vfnmsac vfnmsac_obj;
> static CONSTEXPR const vfmadd vfmadd_obj;
> static CONSTEXPR const vfnmsub vfnmsub_obj;
> static CONSTEXPR const vfnmacc vfnmacc_obj;
> +static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
> static CONSTEXPR const vfmsac vfmsac_obj;
> static CONSTEXPR const vfnmadd vfnmadd_obj;
> static CONSTEXPR const vfmsub vfmsub_obj;
> @@ -2380,6 +2403,7 @@ BASE (vfnmsac)
> BASE (vfmadd)
> BASE (vfnmsub)
> BASE (vfnmacc)
> +BASE (vfnmacc_frm)
> BASE (vfmsac)
> BASE (vfnmadd)
> BASE (vfmsub)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
> b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index 67d18412b4c..247074d0868 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -165,6 +165,7 @@ extern const function_base *const vfnmsac;
> extern const function_base *const vfmadd;
> extern const function_base *const vfnmsub;
> extern const function_base *const vfnmacc;
> +extern const function_base *const vfnmacc_frm;
> extern const function_base *const vfmsac;
> extern const function_base *const vfnmadd;
> extern const function_base *const vfmsub;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 92ecf8a9065..7aae0665520 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -351,6 +351,8 @@ DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
>
> DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops)
> DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
> +DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
> +DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
>
> // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
> DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
> new file mode 100644
> index 00000000000..fca378b7a8f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
> @@ -0,0 +1,47 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef float float32_t;
> +
> +vfloat32m1_t
> +test_riscv_vfnmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t
> op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
> + size_t vl) {
> + return __riscv_vfnmacc_vf_f32m1_rm (vd, op1, op2, 2, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfnmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1 (vd, op1, op2, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1_m (mask, vd, op1, op2, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vfnmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
> +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
> --
> 2.34.1
>
