> + machine_mode m1_mode = TARGET_VECTOR_ELEN_64
> + ? (TARGET_MIN_VLEN >= 128 ? VNx2DImode :
> VNx1DImode)
> + : VNx1SImode;
This should update since JuZhe has update the mode system :P
> @@ -5907,7 +6057,7 @@ riscv_expand_epilogue (int style)
> Start off by assuming that no registers need to be restored. */
> struct riscv_frame_info *frame = &cfun->machine->frame;
> unsigned mask = frame->mask;
> - HOST_WIDE_INT step2 = 0;
> + poly_int64 step2 = 0;
I saw we check `step2.to_constant () > 0` later, does it mean step2 is
always a scalar rather than a poly number?
If so, I would suggest keeping HOST_WIDE_INT if possible.
> @@ -6058,10 +6218,10 @@ riscv_expand_epilogue (int style)
> riscv_emit_stack_tie ();
>
> /* Deallocate the final bit of the frame. */
> - if (step2 > 0)
> + if (step2.to_constant () > 0)
> {
> insn = emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
> - GEN_INT (step2)));
> + GEN_INT (step2.to_constant ())));
>
> rtx dwarf = NULL_RTX;
> rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
