Committed
On Fri, Jan 8, 2021 at 3:29 AM Jim Wilson wrote:
>
> On Wed, Jan 6, 2021 at 1:17 AM Kito Cheng wrote:
>
> > RISC-V will put those variable on srodata rather than rodata.
> > gcc/testsuite/ChangeLog:
> > * gcc.dg/array-quals-1.c: Allow srodata.
> >
>
> OK.
>
> Jim
Committed, thanks :)
On Fri, Jan 8, 2021 at 3:49 AM Jim Wilson wrote:
>
> On Thu, Jan 7, 2021 at 1:55 AM Kito Cheng wrote:
>
> > This patch set introduce new set of architecture extension test macros
> > which is accept on riscv-c-api-doc[1] recently.
> >
> >
It's OK for gcc 10? I just forgot to backport that...
On Fri, Nov 6, 2020 at 11:24 AM Kito Cheng wrote:
>
> Committed, thanks :)
>
> On Fri, Nov 6, 2020 at 6:21 AM Jeff Law wrote:
>
> >
> > On 10/16/20 3:01 AM, Martin Liška wrote:
> > > On 10/16/20 9:4
Hi Geng Qi:
Thanks for your patch, committed!
On Mon, Jan 18, 2021 at 3:01 PM Geng Qi via Gcc-patches
wrote:
>
> From: gengqi
>
> Think about this case:
> ./multilib-generator rv32imc-ilp32-rv32imac,rv32imacxthead-f
> Here are 2 problems:
> 1. A unexpected 'xtheadf' extension was made.
>
Committed.
On Thu, Jun 11, 2020 at 5:13 AM Jim Wilson wrote:
>
> On Wed, Jun 10, 2020 at 1:08 AM Kito Cheng wrote:
> > * config/riscv/riscv-protos.h (riscv_output_gpr_save): Remove.
> > * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Update
Committed with adding comments for those two functions.
On Thu, Jun 11, 2020 at 5:10 AM Jim Wilson wrote:
>
> On Wed, Jun 10, 2020 at 1:08 AM Kito Cheng wrote:
> > * config/riscv/riscv.c (gpr_save_reg_order): New.
> > (riscv_expand_prologue): Use riscv_gen_gp
Committed, thanks :)
On Tue, Jun 16, 2020 at 6:07 AM Jim Wilson wrote:
>
> On Mon, Jun 15, 2020 at 7:41 AM Kito Cheng wrote:
> > gcc/ChangeLog:
> >
> > PR target/95683
> > * config/riscv/riscv.c (riscv_gpr_save_operation_p): Remove
> >
Oh I missed the -mabi in testcase, v2 patch attached, same as V1 but
add -mabi flag to testcase.
On Fri, Jun 19, 2020 at 3:08 PM Kito Cheng wrote:
>
> - g++ will complain too few arguments for frflags builtin like bellow
> message:
>
> error: too few arguments to functio
Hi Jason:
Committed, thanks for your review :)
> You should also be able to remove
>
> > #define RISCV_ATYPE_VOID void_type_node
That's still used for builtin functions without return value :)
>> Current GCC implementation is RISC-V ISA 2.2, this patch set implement
>> v20190608 and v20191213, and also add option
>> -misa-spec=[2.2|20190608|20191213] to change the default ISA spec version.
>>
>> There is one major incompatible
>>
>> That option will effect the default version of each s
On Wed, Nov 18, 2020 at 5:29 AM Jim Wilson wrote:
>
> On Thu, Nov 12, 2020 at 11:28 PM Kito Cheng wrote:
>>
>> +#ifndef HAVE_AS_MARCH_ZIFENCE
>> + /* Skip since older binutils don't recognize zifencei,
>> + we mad a mistake that is binutils
>> - CSR related instructions and fence instructions has to be splitted from
>>baseline ISA, zicsr and zifencei are corresponding sub-extension.
>
>
> It is actually only fence.i that is split off. fence is still part of the
> base ISA. This is why it is called zifencei.
Oh...I didn't noti
On Sat, Nov 21, 2020 at 6:12 AM Jim Wilson wrote:
>
> On Fri, Nov 20, 2020 at 12:34 AM Kito Cheng wrote:
>
> > - Define MULTILIB_DEFAULTS can reduce the total number of multilib if
> >the default arch and ABI are listed in the multilib config.
> >
>
>
Committed :)
On Sat, Nov 28, 2020 at 7:45 AM Jim Wilson wrote:
>
> On Thu, Nov 26, 2020 at 1:04 AM Kito Cheng wrote:
>
> > * gcc.c (print_multilib_info): Check default arguments not
> > appeared in multi-lib option list with '!'
> >
>
> OK.
>
> Jim
Committed to trunk :)
On Sat, Nov 28, 2020 at 7:49 AM Jim Wilson wrote:
>
> On Fri, Nov 20, 2020 at 10:38 PM Kito Cheng wrote:
>
> > On Sat, Nov 21, 2020 at 6:12 AM Jim Wilson wrote:
> > > On Fri, Nov 20, 2020 at 12:34 AM Kito Cheng
> > wrote:
> > >
Committed, thanks :)
On Thu, Dec 3, 2020 at 8:51 AM Jim Wilson wrote:
>
> On Tue, Dec 1, 2020 at 12:13 AM Kito Cheng wrote:
>>
>> - We would like to canonicalize the arch string for --with-arch for
>>easier handling multilib, so split canonicalization part to a sta
thias Klose wrote:
> > On 12/4/20 9:07 AM, Kito Cheng via Gcc-patches wrote:
> >> Committed, thanks :)
> >>
> >> On Thu, Dec 3, 2020 at 8:51 AM Jim Wilson wrote:
> >>>
> >>> On Tue, Dec 1, 2020 at 12:13 AM Kito Cheng wrote:
> >>&
Committed
On Tue, Dec 8, 2020 at 5:33 AM Jim Wilson wrote:
>
> On Sat, Dec 5, 2020 at 10:12 PM Kito Cheng wrote:
>
> > gcc/ChangeLog:
> >
> > * config.gcc (riscv*-*-*): Checking python, python3 or python2
> > is available, and skip doing wi
Hi Simon:
V2 version is LGTM, thanks!
On Thu, Dec 10, 2020 at 4:31 AM Simon Cook wrote:
>
>
> On 09/12/2020 14:57, Matthias Klose wrote:
> >
> > that's again hard-coding 'python'.
> >
>
> I believe this way of invoking python should be better than just
> hardcoding python, instead using the int
Hi Simon:
Committed, thanks :)
On Thu, Dec 10, 2020 at 4:56 PM Simon Cook wrote:
>
> Hi Kito,
>
> Thanks for reviewing this. Since I don't have commit access, could you
> commit this for me.
>
> On 10/12/2020 02:32, Kito Cheng wrote:
> > Hi Simon:
> >
> > V2 version is LGTM, thanks!
> >
Thanks for reviewing that, committed to trunk :)
On Tue, Oct 13, 2020 at 5:38 PM Eric Botcazou wrote:
>
> > Do you mind having a review for that?
>
> Sorry for missing the v2 patch; yes, it looks good to me.
>
> --
> Eric Botcazou
>
>
Committed, thanks, other improvement changes will be sent in separate
patches in the next few days :)
On Thu, Oct 15, 2020 at 5:41 AM Jim Wilson wrote:
>
> On Tue, Oct 13, 2020 at 3:09 AM Kito Cheng wrote:
> > - The behavior of -mcpu basically equal to -march plus -mtune, but i
Hi Martin:
> I can do it earlier if it helps for the integration and testing purpose?
I think it would be helpful! thanks!
On Fri, Oct 16, 2020 at 3:33 PM Martin Liška wrote:
>
> On 8/19/20 11:25 AM, Kito Cheng via Gcc-patches wrote:
> > Could you update that for RV32, and thi
OK for gcc-10 branch?
This patch was committed into trunk for 1 week and seems stable.
On Wed, Oct 14, 2020 at 11:56 AM Kito Cheng wrote:
>
> Thanks for reviewing that, committed to trunk :)
>
> On Tue, Oct 13, 2020 at 5:38 PM Eric Botcazou wrote:
> >
> > > Do you mi
Committed with comment fix, thanks :)
On Thu, Oct 22, 2020 at 10:37 AM Jim Wilson wrote:
>
> On Wed, Oct 21, 2020 at 7:36 PM Jim Wilson wrote:
>
> >
> >
> > On Fri, Oct 16, 2020 at 2:34 AM Kito Cheng wrote:
> >
> >> +# Example 2:
> >> +# rv
I would like to see some benchmark results instead of just a simple
case, to make sure everything is alright, the add pattern is used
literally anywhere, my most worry is the clobber might bring some
negative impact like cause register pressure estimation get higher,
and then result worse code gen.
se V functions with the +arch attributes. That
> wouldn't require any compiler changes, but it's kind of clunky.
> * Add some sort of test suite logic (maybe in DejaGNU?) to check and see
> if the desired ABI is linkable before attempting to do so. That might
> b
LGTM, thank you for catching that!!
On Wed, Nov 9, 2022 at 3:50 PM Philipp Tomsich wrote:
>
> A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a
> while now, due to the pipeline model for sifive-7-series not being
> selected despite -mtune=sifive-7-series. The root cause is tha
I am not sure if I am missing something, your testcase should rely on
movmisalignhi pattern, but you defined movmisalign with ANYF
mode iterator rather than movmisalign with HI, SI, DI?
And seems the testcase compile with `-march=rv64gc -mabi=lp64
-mtune=size -O2` w/o this patch already generated
Committed, thanks !
On Sun, Nov 6, 2022 at 1:57 AM wrote:
>
> From: Ju-Zhe Zhong
>
> This patch support RVV scalable register spilling.
> prologue && epilogue handling pick up prototype from Monk Chiang
> .
> Co-authored-by: Monk Chiang
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc
Hi Christoph:
> This patch implements expansions for the cmpstrsi and the cmpstrnsi
> builtins using Zbb instructions (if available).
> This allows to inline calls to strcmp() and strncmp().
>
> The expansion basically emits a peeled comparison sequence (i.e. a peeled
> comparison loop) which comp
Could you provide some testcase?
On Tue, Nov 15, 2022 at 12:29 AM jiawei wrote:
>
> Skip add insn generate if the adjust size equal to zero.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_expand_epilogue):
> New if control segement.
>
> ---
> gcc/co
LGTM, thanks :)
On Thu, Nov 17, 2022 at 5:17 AM Kevin Lee wrote:
>
> l insn condition has been modified based on the thread in
> https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605481.html. The
> lfloor-lecil-inexact checks call instead of scan-assembler-not
> "fcvt.l.s/d" due to https://
Wait, what's Xgnuzihintpausestate???
On Fri, Nov 18, 2022 at 12:30 PM Palmer Dabbelt wrote:
>
> gcc/ChangeLog:
>
> * doc/extend.texi (__builtin_riscv_pause): Imply
> Xgnuzihintpausestate.
> ---
> gcc/doc/extend.texi | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>
committed to trunk and gcc 13
On Tue, Apr 18, 2023 at 9:29 PM Jeff Law wrote:
>
>
>
> On 4/18/23 04:16, Kito Cheng via Gcc-patches wrote:
> > Document which version of RISC-V vector intrinsics has implemented in
> > GCC.
> >
> > gcc/ChangeLog:
> >
&g
4 + 4x SImode where x is 0~n, so it
will hold at least four DI
So GET_MODE_NUNITS for a single vector register with DI mode will
become 2 (VNx2DImode) if it is really possible, which is a more
precise way to model the vector extension for RISC-V .
On Tue, Apr 18, 2023 at 10:28 PM Kito Cheng
Hi Jeff, Ju-Zhe:
Let you know that I am running creduce with this testcase for reduce
the size of testcsae, it's really too huge...
On Wed, Apr 19, 2023 at 3:00 AM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 4/17/23 20:03, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > gcc/ChangeLog:
Hi Richard, Jeff:
It's it possible to backport to GCC 13? highway is one of our
important users for RISC-V vector stuff, and it has built in some
distro, so we believe this bug fix is important to backport.
Thanks
Hi Ju-Zhe:
Thanks for update
On Wed, Apr 19, 2023 at 7:25 AM wrote:
>
> From: J
Do you mind shared gcc configure and the option you tried?
On Wed, Apr 19, 2023 at 4:01 AM Palmer Dabbelt wrote:
>
> On Tue, 18 Apr 2023 08:44:24 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> >> Yep, if I drop the non-canonicial strings via
> >>
> >> diff --git a/gcc/config/riscv/multilib-gen
Could you please move the new function declarations and new code to
the patch where they are being used?
> +/* RVV vector register sizes. */
> +enum riscv_vector_bits_enum
> +{
> + RVV_SCALABLE,
> + RVV_NOT_IMPLEMENTED = RVV_SCALABLE,
> + RVV_64 = 64,
> + RVV_128 = 128,
> + RVV_256 = 256,
>
> +/* Implement TARGET_ESTIMATED_POLY_VALUE.
> + Look into the tuning structure for an estimate.
> + KIND specifies the type of requested estimate: min, max or likely.
> + For cores with a known RVV width all three estimates are the same.
> + For generic RVV tuning we want to distinguish th
> @@ -118,6 +120,41 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT
> minval,
> && IN_RANGE (INTVAL (elt), minval, maxval));
> }
>
> +/* Return the vlmul field for a specific machine mode. */
> +unsigned int
> +riscv_classify_vlmul_field (enum machine_mode mode)
This is not imp
> diff --git a/gcc/config/riscv/vector-iterators.md
> b/gcc/config/riscv/vector-iterators.md
> index 70ad85b661b..7fae87968d7 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -34,6 +34,8 @@
>UNSPEC_VMULHU
>UNSPEC_VMULHSU
>
> + UNSPEC_VA
And which -march -mabi you used will got issue?
On Wed, Apr 19, 2023 at 8:51 AM Palmer Dabbelt wrote:
>
> On Tue, 18 Apr 2023 17:47:31 PDT (-0700), Kito Cheng wrote:
> > Do you mind shared gcc configure and the option you tried?
>
> Just riscv-gnu-toolchain with "--enbale-
OK, thanks, I know what the problem is, I tried rv64 but didn't try
rv32, I have another fix in my mind, and will post another fix soon.
On Wed, Apr 19, 2023 at 9:29 AM Palmer Dabbelt wrote:
>
> On Tue, 18 Apr 2023 18:26:18 PDT (-0700), Kito Cheng wrote:
> > And which -march -m
Write a primary version for that, did you mind giving it a try?
The basic idea is to select multilib only by ABI, so that we don't
need to bother with endless multilib reuse cases...
On Wed, Apr 19, 2023 at 9:38 AM Kito Cheng wrote:
>
> OK, thanks, I know what the problem is, I tri
Hi Pan:
>rtx expand (function_expander &e) const override diff --git
> a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index
> 0ecca98f20c..6819363b9ff 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be
written into the commit log.
> gcc/ChangeLog:
>
>* config/riscv/riscv-v.cc (emit_pred_op):
>* config/riscv/riscv-vector-builtins-bases.cc:
>* config/riscv/vector.
Could you add more description? maybe like this:
RISC-V has provide different VLEN configuration by different ISA
extension like `zve32x`, `zve64x` and `v`
zve32x just guarantee the minimal VLEN is 32 bits,
zve64x guarantee the minimal VLEN is 64 bits,
and v guarantee the minimal VLEN is 128 bits
---
htdocs/gcc-13/changes.html | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index f6941534..5427f805 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -636,9 +63
> On Wed, 19 Apr 2023 06:53:51 PDT (-0700), kito.ch...@sifive.com wrote:
> > ---
> > htdocs/gcc-13/changes.html | 31 ++-
> > 1 file changed, 30 insertions(+), 1 deletion(-)
> >
> > diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> > index f6941534.
Committed to trunk, thanks!
On Wed, Apr 19, 2023 at 8:34 PM wrote:
>
> From: Juzhe-Zhong
>
> RISC-V has provide different VLEN configuration by different ISA
> extension like `zve32x`, `zve64x` and `v`
> zve32x just guarantee the minimal VLEN is 32 bits,
> zve64x guarantee the minimal VLEN is 64
Committed, thanks :)
On Wed, Apr 19, 2023 at 5:19 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch aligned the MODE_CLASS condition of the IOR to the AND. Then
> more MODE_CLASS besides SCALAR_INT can able to perform the optimization
> A | (~A) -> -1 similar to AND operator. For
> +/* Return the vectorization machine mode for RVV according to LMUL. */
> +machine_mode
> +preferred_simd_mode (scalar_mode mode)
> +{
> + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128
> + which is -march=rv64gcv. Since GCC loop vectorizer report ICE
> + when we enabl
On Thu, Apr 20, 2023 at 10:56 AM juzhe.zh...@rivai.ai
wrote:
>
> >> The comment above might not sync with your implementation?
> Address comment.
>
> >> Actually, you've allowed TARGET_MIN_VLEN < 128 && riscv_autovec_lmul <
> >> RVV_M2
> Not sure I am on the same page with you. I return word_mode
OK, thanks :)
On Thu, Apr 20, 2023 at 12:35 PM Jeff Law wrote:
>
> This is primarily Raphael's work. All I did was adjust it to apply to
> the trunk and add the new types to generic.md's scheduling model.
>
>
> The basic idea here is to make sure we have the ability to schedule the
> bitmanip in
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
> new file mode 100644
> index 000..be6b4c641cb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_
> LGTM, do we missed the timeline to merge code size reduction extensions
> support in gcc13?
Yeah, GCC 13 is branching out, so we need to wait for GCC 14, I also
really want to have this in GCC 13 too, and I am a little concerned
that it is still not officially ratified yet for merge that.
>
>
On Thu, Apr 20, 2023 at 5:07 PM juzhe.zh...@rivai.ai
wrote:
>
> >> With --param=riscv-autovec-preference=fixed-vlmax, however, the output is
> >> reasonable. BTW please use --param instead of -param in the description to
> >> avoid confusion.
> >>Now the patches don't explicitly note that they on
---
htdocs/gcc-13/changes.html | 34 +-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index f6941534..4515a6af 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -636,7
Hi Robin:
Share with you more context that I've discussed with Ju-Zhe, and look
for comments from you :)
There is 3 different auto vectorization flavor:
- VLA
- VLS fixed-vlmax (Name TBD)
- (Traditional) VLS
I think I don't need to explain too much on VLA.
So let we focus on second and third:
V
Committed, thanks!
On Wed, Apr 19, 2023 at 6:42 PM wrote:
>
> From: Ju-Zhe Zhong
>
> Testcase coming from Kito.
>
> Co-authored-by: kito-cheng
> Co-authored-by: kito-cheng
>
> PR 109535
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v
GCC will complaint if target ABI isn't have corresponding multi-lib on
glibc toolchain, use stdint-gcc.h to suppress that.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/simplify_ior_optimization.c: Use stdint-gcc.h
rather than stdint.h
---
gcc/testsuite/gcc.target/riscv/simplify_io
In newer ISA spec, F will implied zicsr, add that into -march option to
prevent different test result on different default -misa-spec version.
gcc/testsuite/
* gcc.target/riscv/arch-19.c: Add -misa-spec.
---
gcc/testsuite/gcc.target/riscv/arch-19.c | 4 ++--
1 file changed, 2 insertions(
Committed to trunk, thanks :)
On Tue, Apr 18, 2023 at 9:50 PM Jeff Law wrote:
>
>
>
> On 3/13/23 02:19, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > Co-authored-by: kito-cheng
> > Co-authored-by: kito-cheng
> >
> > Consider this
---
gcc/common/config/riscv/riscv-common.cc | 118
gcc/config/riscv/linux.h| 13 ++-
2 files changed, 90 insertions(+), 41 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 309a52def75f..75b
Sorry, I didn't really commit this, it's send by accident since I give
wrong sha1
On Fri, Apr 21, 2023 at 2:47 PM Kito Cheng via Gcc-patches
wrote:
>
> ---
> gcc/common/config/riscv/riscv-common.cc | 118
> gcc/config/riscv/linux.h
From: Juzhe-Zhong
This patch is to enhance optimization for auto-vectorization.
Before this patch:
Loop:
vsetvl a5,a2...
vsetvl zero,a5...
vle
After this patch:
Loop:
vsetvl a5,a2
vle
gcc/ChangeLog:
PR target/109547
* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn
Committed with an extra testcase from PR109547
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616363.html
On Fri, Apr 7, 2023 at 9:34 AM wrote:
>
> From: Juzhe-Zhong
>
> This patch is to enhance optimization for auto-vectorization.
>
> Before this patch:
>
> Loop:
> vsetvl a5,a2...
> vset
Hi Robin:
OK, Feel free to commit that to trunk.
and don't forgot to mention this:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109582
On Fri, Apr 21, 2023 at 3:45 PM Robin Dapp via Gcc-patches
wrote:
>
> > ../../gcc/config/riscv/generic.md:28:1: unknown value `smin' for attribute
> > `type'
Thanks, committed to trunk.
On Fri, Apr 21, 2023 at 5:19 PM wrote:
>
> From: Juzhe-Zhong
>
> Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
>
> Consider the following testcase:
> void f (void * restrict in, void * restrict out, int l, int n, int m)
> {
> for (int i = 0; i < l;
ng for the PATCH v2. Just FYI there will be some underlying
> investigation based on this PATCH like VMSEQ.
>
> Pan
>
> -Original Message-
> From: Li, Pan2
> Sent: Wednesday, April 19, 2023 7:27 PM
> To: 'Kito Cheng' ; 'juzhe.zh...@rivai.ai'
--Original Message-
> From: Kito Cheng
> Sent: Friday, April 21, 2023 6:17 PM
> To: Li, Pan2
> Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng
> ; Wang, Yanzhang
> Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut
> optimization
>
> I got a bunch
You need use git+ssh protocol, I use this way to manage that:
git remote add upstream-write git+ssh://@gcc.gnu.org/git/gcc.git
git push upstream-write master
On Sat, Apr 22, 2023 at 12:00 AM Vineet Gupta wrote:
>
>
> On 4/21/23 02:30, Richard Sandiford wrote:
> > No approval is needed when addi
Committed, thanks :)
On Sun, Apr 23, 2023 at 7:18 PM wrote:
>
> From: Juzhe-Zhong
>
> V2 patch for:
> https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/
> which has been reviewed.
>
> This patch address Jeff's comment, refine ChangeLog to give more
Pushed
On Sun, Apr 23, 2023 at 7:34 PM wrote:
>
> From: Juzhe-Zhong
>
> Address Jeff's comment:
> https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/
> Add a function comment.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (pass_vsetvl
Committed, thanks :)
On Sun, Apr 23, 2023 at 8:19 PM wrote:
>
> From: Juzhe-Zhong
>
> This patch is the V2
> patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zh...@rivai.ai/
>
> Address comments from Jeff. Add comments for all_avail_in_compatible_p and
> r
I am not sure if we should accept this on gcc trunk without binutils support?
On Sat, Apr 22, 2023 at 3:58 AM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 2/10/23 15:41, Philipp Tomsich wrote:
> > This adds the xventanacondops extension to the option parsing and as a
> > default for the ventana-vt1
and merge it.
>
> Thanks,
> Philipp.
>
> On Tue, 25 Apr 2023 at 11:53, Kito Cheng wrote:
>
> > I am not sure if we should accept this on gcc trunk without binutils
> > support?
> >
> > On Sat, Apr 22, 2023 at 3:58 AM Jeff Law via Gcc-patches
> > wrot
tenance may be out of
> control if we will add many new define_insn_and_split for the shortcut.
> 2. The new added pattern may not friendly for the underlying
> auto-vectorization.
>
> Juzhe can help to correct me if any misleading.
>
> Pan
>
> -Original Message--
Hi ShiHua:
Thanks for your contribution to the zfbfmin extension :)
General comments:
- Add zfbfmin to riscv_ext_version_table
- Add test case to verify the -march is accepted.
- Add testcase to test argument passing.
- Add testcase for operations.
- Add testcase for compares.
> +(define_insn "*
y for the implementation. Thus, it is
> OK if we think option 2 is a better way for this.
>
> Kito and Juzhe, any idea for making the decision? Thanks in advance!
>
> Pan
>
> -Original Message-
> From: Kito Cheng
> Sent: Tuesday, April 25, 2023 9:08 PM
> To
Plz write description for every item in changelog, otherwise the gcc
git hook will reject this patch.
remote: *** The following commit was rejected by your
hooks.commit-extra-checker script (status: 1)
remote: *** commit: 2777f46a58af65be380a2f44bf5cdf93e2d11886
remote: *** ChangeLog format failed
Committed, thanks!
On Tue, Apr 25, 2023 at 10:29 PM wrote:
> From: Pan Li
>
> In most architecture the precision_size of vbool*_t types are caculated
> like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some archi
Committed to trunk
On Mon, Apr 24, 2023 at 11:06 AM juzhe.zh...@rivai.ai
wrote:
>
> Adding earlyclobber is to make dest operand do not overlap with source
> operand.
> For example:
> for gather load, vluxei.v v8,(a5),v8 is illegal according to RVV ISA.
> GCC is using same way as LLVM which is a
Committed to trunk
On Mon, Apr 24, 2023 at 11:09 AM juzhe.zh...@rivai.ai
wrote:
>
> I can push codes yet. Can you push them for me?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Jeff Law
> Date: 2023-04-22 04:42
> To: juzhe.zhong; gcc-patches
> CC: kito.cheng; palmer
> Subject: Re: [PATCH] RISC-V: Fix r
Committed
On Wed, Apr 26, 2023 at 12:48 PM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Refine vmadc/vmsbc RA constraint.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/narrow_constraint-13.c: New test.
> * gcc.target/riscv/
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_scalable_vector_type_p):
> (riscv_arg_has_vector):
> (riscv_pass_in_vector_p):
> (riscv_get_arg_info):
You need to write something for changelog...:P
LGTM, pushed to trunk
> This patch try to legitimise the const0_rtx (aka zero register)
> as the base register for the RVV load/store instructions.
>
> For example:
> vint32m1_t test_vle32_v_i32m1_shortcut (size_t vl)
> {
> return __riscv_vle32_v_i32m1 ((int32_t *)0, vl);
> }
The example is kin
`vr`, `vm` and `vd` constarint for vector register constarint, those 3
constarint has implemented on LLVM as well.
gcc/ChangeLog:
* doc/md.texi (RISC-V): Add vr, vm, vd constarint.
---
gcc/config/riscv/riscv-modes.def| 4
gcc/config/riscv/riscv-protos.h | 2 ++
gcc/config/
Damm, I mixed something up else..
On Thu, Apr 27, 2023 at 4:53 PM Kito Cheng via Gcc-patches
wrote:
>
> `vr`, `vm` and `vd` constarint for vector register constarint, those 3
> constarint has implemented on LLVM as well.
>
> gcc/ChangeLog:
>
> * doc/md.texi (RI
`vr`, `vm` and `vd` constarint for vector register constarint, those 3
constarint has implemented on LLVM as well.
gcc/ChangeLog:
* doc/md.texi (RISC-V): Add vr, vm, vd constarint.
---
V2 changes:
- Drop unrelated changes.
---
gcc/doc/md.texi | 9 +
1 file changed, 9 insertion
> +(define_split
> + [(set (match_operand: 0 "register_operand")
> + (if_then_else:
> + (unspec:
> + [(match_operand: 1 "vector_all_trues_mask_operand")
> +(match_operand 6 "vector_length_operand")
> +(match_operand 7 "const_int_operand")
>
> Could you try something like this? that should be more generic:
>
> (define_split
> [(set (match_operand:VB 0 "register_operand")
>(if_then_else:VB
> (unspec:VB
>[(match_operand:VB 1 "vector_all_trues_mask_operand")
> (match_operand 4 "vector_length_opera
Thanks, pushed :)
On Thu, Apr 27, 2023 at 11:32 AM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> The read-thread-pointer test may require the gcc configured
> with --enable-tls. If no, there x4 (aka tp) register will not
> be presented in the assembly code.
>
> This patch requires the tls f
> * gcc.target/riscv/vector-abi-3.c: New test.
> * gcc.target/riscv/vector-abi-4.c: New test.
> * gcc.target/riscv/vector-abi-5.c: New test.
>
> Signed-off-by: Yanzhang Wang
> Co-authored-by: Kito Cheng
> ---
> gcc/config/riscv/riscv.cc
ce is that it will act on combine pass which is more generic
> than the PATCH v1 (which acts on split2 pass).
>
> Pan
>
> -Original Message-
> From: Kito Cheng
> Sent: Thursday, April 27, 2023 11:00 PM
> To: Li, Pan2
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@ri
struction eliminated and require less
> vector registers.
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Add new define split to perform
> the simplification.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/integer_compare_insn_shortc
ok
On Fri, Apr 28, 2023 at 2:13 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> The current support of the bitfield-extraction instructions
> th.ext and th.extu (XTheadBb extension) only covers sign_extract
> and zero_extract. This patch add support for sign_extend and
> zero_extend
ok
On Fri, Apr 28, 2023 at 2:15 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> The current implementation triggers an assertion in
> dwarf2out_frame_debug_cfa_offset() under certain circumstances.
> The standard code uses REG_FRAME_RELATED_EXPR notes instead
> of REG_CFA_OFFSET not
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