[PATCH i386 AVX512] [50/n] Add cvtps2 insn patterns.

Hello, Patch in the bottom extends truncation insn patterns. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/s

Re: [PATCH i386 AVX512] [49/n] Add vpshuf[lh]w insn patterns.

> Bootstrapped. > AVX-512* tests on top of patch-set all pass > under simulator. > > Is it ok for trunk? Forgot to mention, that patch adds support for PSHUF[HL]W insns. -- Thanks, K

[PATCH i386 AVX512] [51/n] Add pd2dq and dq2pd converts.

Hello, Patch in the bottom adds support for pd2dq and dq2pd conversions. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/i386.c (avx512f_ufix_notruncv8dfv8si_mask_round): Rename to ... (ufix_notruncv8dfv8si

[PATCH i386 AVX512] [52/n] Add convert ps2pd and ps2dq.

Hello, Patch in the bottom adds support for ps2dq and ps2pd conversions. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_CVTINT2MASK. (define_insn "fix_t

[PATCH, bootstrap PR63235] Fix bootstrap.

Hello, Patch in the bottom fixes bootstrap (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63235) gcc/ * varpool.c (varpool_node::add): Pass decl attributes to lookup_attribute. Is it ok for trunk? -- Thanks, K diff --git a/gcc/varpool.c b/gcc/varpool.c index 8001c93..3761f14 1006

[PATCH i386 AVX512] [53/n] Update vec_set_0 pattern constraints.

Hello, Patch in the bottom extends to EVEX constraints of vec_set_0 insn pattern. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_insn "vec_set_0"): Add EVEX version. -- Thanks, K diff --git a/gcc/

[PATCH i386 AVX512] [54/n] Add mov[dlh]dup insns support.

Hello, patch in the bottom introduces support for vmov[dlh]dup insns. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_insn "avx_movshdup256"): Add masking. (define_insn "sse3_movshdup"): Ditt

[PATCH i386 AVX512] [55/n] Extend `perm' insn patterns.

Hello, Patch in the bottom extends `perm' insn patterns. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_expand "_perm"): Rename to ... (define_expand "_perm"): this. (define_expand "

Re: [PATCH i386 AVX512] [52.1/n] Add vec2mask and mask2vec insn patterns.

_cvtmask2"): Ditto. (define_expand "_cvtmask2"): Ditto. (define_insn "*_cvtmask2"): Ditto. -- Thanks, K commit 6cece2e60da5777b6223025365295a555a25f285 Author: Kirill Yukhin Date: Thu Sep 25 12:01:15 2014 +0400 AVX-512. 52.1. D2M and M2D patterns. diff --git a/gc

Re: [PATCH i386 AVX512] [52.1/n] Add vec2mask and mask2vec insn patterns.

On 25 Sep 13:42, Kirill Yukhin wrote: > Hello, > As suggested, this is splitted out part of [52/n] patch, > which introduces new vec2mask and mask2vec insn patterns. > > As suggested, I've got rid off use of UNSPEC_CVTINT2MASK > unspec. Unfortunatelly, only partially. >

[PATCH i386 AVX512] [56/n] Add plus/minus/abs/neg/andnot insn patterns.

Hello, Patch in the bottom extends plus/minus/abs/andnot patterns to support AVX-512. I've used questionable hack in the patterns. Instead of writing dozen similar patterns with masking I've simply substed them, prohibiting non-mask variant in the pattern condition. E.g.: (define_expand "3" [(set

[PATCH i386 AVX512] [57/n] Extend blend/cmp/brodcast insn patterns.

Hello, Patch in the bottom extends blend/cmp/brodcast insn patterns. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_insn "avx512f_blendm"): Delete. (define_insn "_blendm"): New. (def

[PATCH i386 AVX512] [58/n] Add vpmul[u]dq insn patterns.

Hello, Patch in the bottom adds support for vpmul[u]dq insn patterns. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_expand "vec_widen_umult_even_v8si"): Add masking. (define_insn "*vec_wide

[PATCH i386 AVX512] [59/n] Add vptest[n]m, ucmp, cmpeq insn patterns.

Hello, Patch in the bottom adds support for vptest[n]m, ucmp, cmpeq. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/i386.c (ix86_expand_args_builtin): Handle CODE_FOR_avx512vl_cmpv4di3_mask, CODE_FOR_avx51

[PATCH i386 AVX512] [60/n] Update 128bit ashrv insn pattern.

Hello, This tiny patch extends 128bit ashrv expander. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_mode_iterator VI128_128 [V16QI V8HI V2DI]): Delete. (define_expand "vashr3"): Add masking

[PATCH i386 AVX512] [61/n] Update FP logic insn patterns.

Hello, This patch extends andnot and any_logic insn patterns. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_insn "_andnot3"): Add masking, use VF_128_256 mode iterator and update assembler

[PATCH i386 AVX512] [62/n] Add vpmaddubsw,vdbpsadbw insn patterns.

Hello, This patch introduces patterns for vpmaddubsw and vdbpsadbw insn. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_DBPSADBW, UNSPEC_PMADDUBSW512. (define_in

Re: [PATCH i386 AVX512] [60/n] Update 128bit ashrv insn pattern.

Hello Uroš, On 29 Sep 09:54, Uros Bizjak wrote: > > +(define_expand "vashrv2di3" > > + [(set (match_operand:V2DI 0 "register_operand") > > + (ashiftrt:V2DI > > + (match_operand:V2DI 1 "register_operand") > > + (match_operand:V2DI 2 "nonimmediate_operand")))] > > + "TARGET_XO

Re: [PATCH i386 AVX512] [61/n] Update FP logic insn patterns.

Hello Uroš, On 29 Sep 10:00, Uros Bizjak wrote: > > + /* There is no vandnp[sd] in avx512f. Use vpandn[qd]. */ > > + if (!TARGET_AVX512DQ) > > All other patterns also have " &&" condition here. Is > the above condition correct? I think this is correct since in this pattern we use AVX-512 only

Re: [PATCH i386 AVX512] [62/n] Add vpmaddubsw,vdbpsadbw insn patterns.

Hello Uroš, On 29 Sep 10:08, Uros Bizjak wrote: > On Fri, Sep 26, 2014 at 4:09 PM, Kirill Yukhin > wrote: > > +(define_insn "avx512bw_pmaddubsw512" > > + [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") > > + (u

Re: [PATCH] DATA_ALIGNMENT vs. DATA_ABI_ALIGNMENT (PR target/56564)

Patch preapproved. Jakub Hi, Checked into trunk: http://gcc.gnu.org/ml/gcc-cvs/2013-06/msg00646.html Thanks, K

Re: Document Intel Silvermont support in invoke.texi

> Patch preapproved. Checked into 4.8 branch: http://gcc.gnu.org/ml/gcc-cvs/2013-06/msg00648.html Thanks, K

[PATCH, i386, PR57623] Introduce _bextr (single underscore) intrinsucs

Hi, As mentioned be Jakub, Intel Spec introduces single-underscored intrinsics for bextr insn which takes different arguments. Patch introduces intrinsics and tests. ChangeLog: 2013-06-20 Kirill Yukhin

Re: [PATCH, i386, PR57623] Introduce _bextr (single underscore) intrinsucs

the submitters that want to bend > the rules. Sorry. > As I said before, bogus tests and bootstrap was actually working. I sorry for the crap I've sent. I've rewrote intrinsics and tests. Bootstrap is passing, new tests are passing and they perform correct checks. ChangeLog entry: 20

Re: [Patch wwwdocs] gcc-4.9 changes: mention support of the Intel Silvermont microarchitecture

Hello, > > Looks good to me; just say "the new Intel...". Checked int www CVS. Thanks, K

Re: [PATCH, i386, PR57623] Introduce _bextr (single underscore) intrinsucs

On 6/27/2013 8:28 PM, Richard Henderson wrote: Hello, > The patch is ok with that fixed. > Thanks, checked into trunk: http://gcc.gnu.org/ml/gcc-cvs/2013-06/msg00941.html. Thanks, K

Re: [Patch wwwdocs] gcc-4.9 changes: mention support of the Intel Silvermont microarchitecture

On 7/2/2013 11:31 AM, Chung-Ju Wu wrote: > I think that would be better to merge the content into single > 'IA-32/x86-64' subsection. But I have no idea about the order of those > two items. Perhaps you or Sriraman can make the decision for the > change? :-) Hi, thanks for pointing! I think order o

[PATCH, i386, PR57623] Introduce synonyms for BMI intrinsics

Hello, As mentioned by Uros [1], we have few intrinsics which described in Intel Spec, but absent in bmiintin.h Attached patch resolves this. Bootstrap passing. Updated tests passing on BMI-featured HW. ChangeLog: 2013-07-02 Kirill Yukhin * config/i386/bmiintrin.h (_blsi_u32): New

Re: [PATCH, i386, PR57623] Introduce synonyms for BMI intrinsics

> I'd say yes to both. I'll prepare a patch for 4.8 then Thanks, K

Re: [PATCH, x86] Use vector moves in memmove expanding

Hello, > Yes, this patch is OK (I meant my previous mail as an approval). > There is a lot of things we can do about string operations, taking > incremental steps is good > plan. Changes were checked into trunk: http://gcc.gnu.org/ml/gcc-cvs/2013-07/msg00179.html Thanks, K

Re: [PATCH, i386, PR57623] Introduce synonyms for BMI intrinsics

On 7/3/2013 10:29 AM, Jakub Jelinek wrote: > On Wed, Jul 03, 2013 at 08:14:25AM +0200, Uros Bizjak wrote: >> On Tue, Jul 2, 2013 at 10:32 AM, Kirill Yukhin >> wrote: >> BTW: Do we want to backport this patch (and your previous) to 4.8 branch? > I'd say yes to both

Re: [PATCH, i386, PR57623] Introduce synonyms for BMI intrinsics

On 7/17/2013 7:42 PM, Jakub Jelinek wrote: > On Wed, Jul 17, 2013 at 07:39:00PM +0400, Kirill Yukhin wrote: >> Is it ok to install? > Yes. > Thanks! Change into 4_8 branch: http://gcc.gnu.org/ml/gcc-cvs/2013-07/msg00477.html K

[www] Mention avx512 and mpx branches

Hi, Patch adds mention of avx512 and mpx branches in svn.html. Ok to install? Index: htdocs/svn.html === RCS file: /cvs/gcc/wwwdocs/htdocs/svn.html,v retrieving revision 1.185 diff -p -r1.185 svn.html *** htdocs/svn.html 27 May 2

Re: [www] Mention avx512 and mpx branches

Thanks, checked in! On Wed, Jul 24, 2013 at 8:06 PM, Gerald Pfeifer wrote: > On Wed, 24 Jul 2013, Kirill Yukhin wrote: >> Patch adds mention of avx512 and mpx branches in svn.html. >> >> Ok to install? > > Yes, thanks! > > Gerald

Re: [testsuite, android] Disabling thread_local4.C and thread_local4g.C for Android.

Hello, > OK. > Checked into MT: http://gcc.gnu.org/ml/gcc-cvs/2013-07/msg00731.html -- Thanks, K

[PATCH i386 2/8] [AVX512] Add mask registers.

ey Lega Anna Tikhonova Ilya Tocar Andrey Turetskiy Ilya Verbin Kirill Yukhin Michael Zolotukhin * config/i386/constraints.md (k): New. (Yk): Ditto. * config/i386/i386.c (const regclass_map): Add new

Re: [PATCH i386 2/8] [AVX512] Add mask registers.

Hello! > You can't read from memory into a mask register in QImode. > This will fail if the memory was the last byte of a page, > and the following page is not mapped. > > I expected you to need the following patch, to help spill > and fill QImode values, but I havn't found a test case that > ac

Re: Fwd: [x86, PATCH] More effecient code for short unsigned conversion to float-point.

On 12 Aug 16:12, Yuri Rumyantsev wrote: Hello, part of the thread was accidentally removed from gcc-patches. I've comitted Yuri's patch into ML: http://gcc.gnu.org/ml/gcc-cvs/2013-08/msg00272.html As far as discussion was out of ML - feel free to object. Thanks, K > -- Forwarded messa

Re: [PATCH i386 2/8] [AVX512] Add mask registers.

Hello, Patch was rebased on top of trunk. It is applicable on top of [1/8] (which was rebased on new trunk today). Testing: 1. Bootstrap pass. 2. make check shows no regressions. 3. Spec 2000 & 2006 build show no regressions both with and without -mavx512f option. 4. Spec 2000 &

Re: [PATCH] Enable non-complex math builtins from C99 for Bionic

> This is OK, with function_gnu removed (nothing appears to use it), if no > OS port maintainers object to the changes for their OSes within the next > week. Hello, Week is over. Comitted to MT: http://gcc.gnu.org/ml/gcc-cvs/2013-08/msg00447.html -- Thanks, K

Re: [RFC PATCH] Implementing ifunc target hook

> > Otherwise OK. > > Thanks, Hi, chacked into trunk: http://gcc.gnu.org/ml/gcc-cvs/2013-03/msg00785.html Thanks, K

Re: [testsuite] Adding -fno-pic to certain tests

> Ok with that change. Checked into trunk: http://gcc.gnu.org/ml/gcc-cvs/2013-03/msg00786.html Thanks, K

[PATCH, i386, AVX2] Fix intrinsic name for _mm256_broadcastsi128_si256

Hello, According to recent Spec, we have intrinsic _mm256_broadcastsi128_si256, not _mm_broadcastsi128_si256. Attached patch makes avx2intrin.h consistent with Spec in that way. ChangeLog: 2013-03-27 Kirill Yukhin * gcc/config/i386/avx2intrin.h (_mm256_broadcastsi128_si256

Re: [PATCH, i386, AVX2] Fix intrinsic name for _mm256_broadcastsi128_si256

> OK. Thanks, Checked into trunk: http://gcc.gnu.org/ml/gcc-cvs/2013-03/msg00860.html and 4.8: http://gcc.gnu.org/ml/gcc-cvs/2013-03/msg00861.html K

Re: [RFC PATCH] Implementing ifunc target hook

Hi, >> is it ok? > > Yes. Checked into trunk: http://gcc.gnu.org/ml/gcc-cvs/2013-04/msg00066.html Thanks, K

Re: [testsuite, i386] Reimplementing array comparison in avx2-vpop-check.h

> OK with that change. Hi, Checked into trunk: http://gcc.gnu.org/ml/gcc-cvs/2013-04/msg00763.html Thanks, K

Re: [PATCH i386 5/8] [AVX-512] Extend vectorizer hooks.

Hello, On 19 May 09:58, H.J. Lu wrote: > On Mon, May 19, 2014 at 9:45 AM, Uros Bizjak wrote: > > On Mon, May 19, 2014 at 6:42 PM, H.J. Lu wrote: > > > Uros, > I am looking into libreoffice size and the data alignment seems to make > huge > difference. Data section has grown f

Re: [PATCH i386 5/8] [AVX-512] Extend vectorizer hooks.

Hello, On 20 May 08:24, H.J. Lu wrote: > ABI alignment should be sufficient for correctness. Bigger alignments > are supposed to give better performance. Can you try this patch on > HSW and SLM to see if it has any impact on performance? Here is perf. data of your patch. Only HSW so far HSW, 64

Re: Patch RFA: Move x86 _mm_pause out of pragma target("sse") scope

Hello Ian, Uroš, On 30 May 09:19, Uros Bizjak wrote: > Hello! > > > This error is because _mm_pause is defined in the scope of #pragma GCC > > target("sse"). But _mm_pause, which simply generates the pause > > instruction, does not require SSE support. The pause instruction has > > nothing reall

Re: Patch RFA: Move x86 _mm_pause out of pragma target("sse") scope

On 30 May 13:45, Jakub Jelinek wrote: > On Fri, May 30, 2014 at 03:41:22PM +0400, Kirill Yukhin wrote: > > That is definetely a bug and I see no compatibility issues in the fix. > > > > The only nit I see: maybe it'd be better to put this cpuid-less intrinsic > &

Re: [PATCH i386 11/8] [AVX512] [1/2] Rename vmov* intrinsics according to EAS.

Hello, On 15 Jan 20:53, Uros Bizjak wrote: > On Tue, Jan 14, 2014 at 7:13 AM, Kirill Yukhin > wrote: > > I have a doubts about changes to sse.md. > > I've splitted existing (SF-only) patterns into 2: DF and SF. > > As far as insn operands and final instructi

Re: [PATCH i386 11/8] [AVX512] [2/2] Add missing packed PF gathers/scatters.

Hello, This is non-trivial part of the patch. > On 15 Jan 20:53, Uros Bizjak wrote: > On Tue, Jan 14, 2014 at 7:13 AM, Kirill Yukhin > wrote: > Did you try to add DF/SF mode to the unspec? I am not familiar with > this insn, but shouldn't the mode of mem access be some

Re: [PATCH i386 11/8] [AVX512] [2/2] Add missing packed PF gathers/scatters.

Hello, On 23 Jan 14:22, Uros Bizjak wrote: > > (define_expand "avx512pf_scatterpfdf" > > [(unspec > > [(match_operand: 0 "register_or_constm1_operand") > > (mem:DF > >(match_par_dup 5 > > [(match_operand 2 "vsib_address_operand") > > (match_operand:VI4_256_8_

Re: How to generate AVX512 instructions now (just to look at them).

Hello, I think its time to remove `XPASS' from corresponding tests. On 03 Jan 22:11, Jakub Jelinek wrote: > Hi! > > On Fri, Jan 03, 2014 at 08:58:30PM +0100, Toon Moene wrote: > > I don't doubt that would work, what I'm interested in, is (cat verintlin.f): > > Well, you need gather loads for that

[PATCH, WWW] [AVX-512] Add news about AVX-512.

Hello, This patch adds news about AVX-512 to GCC main page and entry to 4.9's changes.html. Is it ok? PS: I am not native speaker, any corrections are welcome! -- Thanks, K Index: htdocs/index.html === RCS file: /cvs/gcc/wwwdocs/ht

[PATCH i386 13/8] [AVX-512] Fix argument order for perm and recp intrinsics.

Hello, I’ve noticed that _mm512_permutexvar_epi[64|32] intrinsics have wrong arguments order. As per [1] first argument is index. For vmpermps/vpermpd intrinsics are fine, but I’ve changed tests to call CALC with same arg order as intrinsic. here is the same problem (wrong argument order) with vrc

Re: [PATCH, WWW] [AVX-512] Add news about AVX-512.

nd basic autovectorization. + Code was contributed by Sergey Guriev, Alexander Ivchenko, + Maxim Kuznetsov, Sergey Lega, Anna Tikhonova, Ilya Tocar, + Andrey Turetskiy, Ilya Verbin, Kirill Yukhin and + Michael Zolotukhin of Intel, Corp. + + Altera Nios II support

Re: [PATCH i386 13/8] [AVX-512] Fix argument order for perm and recp intrinsics.

Hello Uroš, On 13 Feb 18:25, Uros Bizjak wrote: > On Thu, Feb 13, 2014 at 1:55 PM, Uros Bizjak wrote: > > >> > >> Please don't change srcp pattern, it should be defined similar to > >> vrcpss (aka sse_vmrcpv4sf). You need to switch operand order > >> elsewhere. > > > > No, you are correct. Operan

Re: [PATCH i386 13/8] [AVX-512] Fix argument order for perm and recp intrinsics.

Hello Uroš, On 17 Feb 13:41, Uros Bizjak wrote: > On Mon, Feb 17, 2014 at 1:26 PM, Kirill Yukhin > wrote: > > >> >> Please don't change srcp pattern, it should be defined similar to > >> >> vrcpss (aka sse_vmrcpv4sf). You need to switch operand order

[PATCH i386 14/8] [AVX-512] Fix exp2 and sqrt tests.

Hello, This is relatively obvious patch which eliminates comparision of inifinities for exp2 AVX-512 test and properly comparing floats for avx512f-sqrtps-2.c. Tests pass. Is it ok for trunk? gcc/testsuite/ * gcc.target/i386/avx512er-vexp2ps-2.c: Decrease exponent argument to avo

Re: [PATCH i386 14/8] [AVX-512] Fix exp2 and sqrt tests.

Hello Uroš, On 28 Feb 13:55, Uros Bizjak wrote: > On Fri, Feb 28, 2014 at 1:14 PM, Kirill Yukhin > wrote: > > Hello, > > This is relatively obvious patch which eliminates comparision > > of inifinities for exp2 AVX-512 test and properly comparing floats > > for avx

Re: [PATCH, i386] Fix emitting of prefetch instructions

Hello Uroš, On 04 Mar 01:13, Uros Bizjak wrote: > On Tue, Mar 4, 2014 at 12:31 AM, Uros Bizjak wrote: > > They are all: > > > > FAIL: gcc.target/i386/avx512pf-vscatterpf0dpd-1.c (test for excess errors) > > Excess errors: > > /ssd/uros/gcc-build/gcc/include/avx512pfintrin.h:108:3: error: the > > l

Re: [i386] Replace builtins with vector extensions

Hello Marc. On 04 Jul 21:11, Marc Glisse wrote: > On Thu, 3 Jul 2014, Kirill Yukhin wrote: > like combining 2 shuffles unless the result is the identity. And > expanding shuffles that can be done in a single instruction works > well. > > But I am happy not doing them yet. T

Re: [GOMP4, RFC] OpenMP4 offload support for Intel PHI targets.

Hello, We recently checked into gomp4-offload branch fix allowing bootstrap to pass as well as fix for disabling multilib for liboffloadmic (64-bit only). -- Thanks, K

Re: [GOMP4, RFC] OpenMP4 offload support for Intel PHI targets.

Hello, We've fixed build infrastructure to allow both host- and accel-compilers to live in the same directory. We've also got rid off some [necessary for build] environment variables. Unfortunately currently it’s impossible to run make check-target-libgomp from the build dir, since both accel- an

Re: [GOMP4, RFC] OpenMP4 offload support for Intel PHI targets.

Hello, > Unfortunately currently it’s impossible to run make check-target-libgomp > from the build dir, since both accel- and host-compilers need to be installed > into the same dir, otherwise host’s gcc will not find accel’s mkoffload. We found workaround to allow make check-target-libgomp. So, he

[AVX-512, new branch] Branch for AVX-512{VL,BW,DQ} was created.

Hello, I'd like to announce, that I've created a branch containing initial support of new Intel ISA extensions called AVX-512{VL,BW,DQ}. It was published here [1] Name is: avx512-vlbwdq. We'll start review for main trunk soon. [1] - https://software.intel.com/sites/default/files/managed/c6/a9/3

Re: [GOMP4, RFC] OpenMP4 offload support for Intel PHI targets.

Hello, We've slightly improved mkoffload. Branch was rebased. -- Thanks, K

Re: [GOMP4, RFC] OpenMP4 offload support for Intel PHI targets.

Hello, Branch was rebased on trunk. It contains fixes for several issues in the build system. Now 'configure' can be called using relative path. Also some options are now unnecessary, updated manual is posted on wiki: https://gcc.gnu.org/wiki/Offloading in "How to try offloading enabled GCC". -

[PATH wwwdocs] Mention avx-512vlbwdq branch in svn.html

Hello, Patch below introduces mention of avx-512vlbwdq SVN branch in htdocs/svn.html Same prefix for e-mail (w/ avx-512) put intentionally. Is it ok to install? -- Thanks, K === RCS file: /cvs/gcc/wwwdocs/htdocs/svn.html,v retrievi

[PATCH i386 AVX512] [1/n] Introduce `-mavx512dq' switch

Hello, With this patch we'd like to start merge process of avx-512vlbwdq branch into main trunk. This patch introduces new switch `-mavx512dq' Bootstrapped. Is it ok for trunk? * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512DQ_SET): Define. (OPTION_MASK_ISA_AV

Re: [i386] Replace builtins with vector extensions

Hello Marc, On 26 Jul 19:34, Marc Glisse wrote: > I did some AVX and AVX512F intrinsics, and it still passes the > testsuite (on my old pre-AVX x86_64-linux-gnu). I've performed testing of your patch using functional simulator of AVX*. And see no regressions as well. -- Thanks, K

[PATCH, i386, AVX, AVX-512] Extend ADDITION_REGISTER_NAMES to XMMs and YMMs.

): Add ymm and zmm register names. testsuite/ * gcc.target/i386/avx-additional-reg-names.c: New. * gcc.target/i386/avx512f-additional-reg-names.c: Ditto. -- Thanks, K commit c3884af93c105115bc1e4d02fa824d24420c5bbf Author: Kirill Yukhin Date: Mon Mar 17 14:56:06 2014 +0400

Re: [PATCH, i386, AVX, AVX-512] Extend ADDITION_REGISTER_NAMES to XMMs and YMMs.

On 17 Mar 17:52, Uros Bizjak wrote: > On Mon, Mar 17, 2014 at 4:12 PM, H.J. Lu wrote: > > >> Is it ok for trunk? > >> Do we need to backport it to 4.8? > It does, but the situation is the same as with %eax vs. %rax names. > So, I think the patch is OK for mainline, and similar patch involving > o

Re: [PATCH, i386, AVX, AVX-512] Extend ADDITION_REGISTER_NAMES to XMMs and YMMs.

On 17 Mar 10:16, H.J. Lu wrote: > BTW, in glibc, there are > > asm volatile ("vmovdqa64 %0, %%zmm0" : : "x" (zmm) : "xmm0" ); Maybe. But I belive that this is much more clear to have instead: asm volatile ("vmovdqa64 %0, %%zmm0" : : "x" (zmm) : "zmm0" ); -- Thanks, K

Re: [PATCH] x86: _mm512_set1_p[sd]

Hello Ulrich, On 19 Mar 22:41, Ulrich Drepper wrote: > Another set of functions missing are those to set all elements of a > 512-bit vector to the same float or double value. I think the patch > below uses the optimal code sequence for that. The patch requires the > previous patch introducing _mm

Re: [PATCH] x86: _mm*_undefined_* (for real)

Hello Ulrich, On 21 Mar 06:41, Ulrich Drepper wrote: > This is a tested version of the patch I sent before. I'm using the > >type var = var > > trick for the initialization so far even those this is not ideal as I > have shown in one of the emails before. If anyone could work on a real > s

[PATCH, x86, testsuite, AVX-512] Fix initialization in 4 tests for shuffles.

2a5c128e75b4f18189d62b0e159de73272c41cf9 Author: Kirill Yukhin Date: Thu Mar 27 13:04:15 2014 +0400 AVX-512. Fix initialization of AVX-512 shuffle tests. --- gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-2.c | 2 +- gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-2.c | 2 +- gcc/testsuite/gcc.target/i386

Re: [PATCH] x86: _mm*_undefined_* (for real)

Hello Ulrich, On 21 Mar 06:41, Ulrich Drepper wrote: > From personal experience I find it > very frustrating if a gcc release doesn't have the complete set of > intrinsics since then you have to provide your own implementations in > code which doesn't assume the latest compiler. I think I should m

Re: various _mm512_set* intrinsics

Hello guys, On 28 Mar 20:10, Uros Bizjak wrote: > Hello! > > > Here are more intrinsics that are missing. I know that gcc currently > > generates horrible code for most of them but I think it's more important > > to have the API in place, albeit non-optimal. Maybe this entices some > > one to ad

Re: [PATCH, i386, PR57623] Introduce synonyms for BMI intrinsics

Thanks! Sorry, missed that! K On Thu, Apr 17, 2014 at 2:13 PM, Jakub Jelinek wrote: > On Wed, Jul 03, 2013 at 08:14:25AM +0200, Uros Bizjak wrote: >> On Tue, Jul 2, 2013 at 10:32 AM, Kirill Yukhin >> wrote: >> > Bootstrap passing. Updated tests passing on BMI-featured

Re: [RFC, x86] Changes for AVX and AVX2 processors

Hi, this was checked in: http://gcc.gnu.org/ml/gcc-cvs/2013-01/msg00442.html Thanks, K On Fri, Jan 11, 2013 at 4:38 PM, Vladimir Yakovlev wrote: > Kirill, > > Could you commit patch? > > 2013-01-11 Vladimir Yakovlev > > * config/i386/i386-c.c (ix86_target_macros_internal): New case. >

Re: [GCC 4.8 wwwdocs] PATCH: Mention several user-visible changes for x86

Hi, Checked in Thanks, K On Mon, Feb 18, 2013 at 10:28 AM, Igor Zamyatin wrote: > Gerald, > > Thanks a lot for your remarks! > > Below is updated patch which will be checked in. > > > Thanks, > Igor > > On Mon, Feb 18, 2013 at 3:07 AM, Gerald Pfeifer wrote: >> On Fri, 15 Feb 2013, Igor Zamyatin

Re: [PATCH, x86, AVX2] FP reassociation enabling for AVX2 targets

> OK (it is a tuning patch). > Hi, Checked in: http://gcc.gnu.org/ml/gcc-cvs/2013-02/msg00540.html Thanks, K

Re: [PATCH, testsuite, i386] FMA3 testcases + typo fix in MD

Thanks! K On Sat, Oct 15, 2011 at 3:08 PM, Uros Bizjak wrote: > On Sat, Oct 15, 2011 at 10:32 AM, Uros Bizjak wrote: > --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fma_double_1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-prune-output ".*warning: 'sseregpar

Re: [PATCH, i386 tests] New tests to check vectorization for AVX2 insns.

Thanks for inputs, Jakub! I am attaching updated patch. Updated testsuite/ChangeLog entry: 2011-10-17 Kirill Yukhin * gcc.target/i386/avx2-vpop-check.h: New header. * gcc.target/i386/avx2-vpaddd-3.c: New test. * gcc.target/i386/avx2-vpaddw-3.c: Ditto

Re: [PATCH, i386 tests] New tests to check vectorization for AVX2 insns.

Thanks, guys, could anybody please commit that? K On Mon, Oct 17, 2011 at 6:33 PM, Jakub Jelinek wrote: > On Mon, Oct 17, 2011 at 06:27:04PM +0400, Kirill Yukhin wrote: >> Thanks for inputs, Jakub! >> >> I am attaching updated patch. >> >> Updated testsui

Re: [PATCH, i386 tests] New tests to check vectorization for AVX2 insns.

Thank you! K On Tue, Oct 18, 2011 at 7:42 PM, H.J. Lu wrote: > On Mon, Oct 17, 2011 at 7:49 AM, Kirill Yukhin > wrote: >> Thanks, guys, could anybody please commit that? >> > > I checked it in for you. > > > -- > H.J. >

[PATCH, i386, PR50766] Fix incorrect mem/reg operands order

Hi, Here is (almost obvous) patch, which fixes PR50766. ChangeLog entry: 2011-10-19 Kirill Yukhin * config/i386/i386.md (bmi_bextr_): Update register/ memory operand order. (bmi2_bzhi_3): Ditto. (bmi2_pdep_3): Ditto. (bmi2_pext_3): Ditto. Bootstrapped

Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order

Thank you guys, Updated patch is attached. Test fails wihout and passing with the fix. ChangeLog entry: 2011-10-20 Kirill Yukhin PR target/50766 * config/i386/i386.md (bmi_bextr_): Update register/ memory operand order. (bmi2_bzhi_3): Ditto

Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order

> > OK. > > Thanks, > Uros. Great, could anybody please commit that? K

Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order

Thanks! K On Fri, Oct 21, 2011 at 12:37 AM, H.J. Lu wrote: > On Thu, Oct 20, 2011 at 1:30 AM, Kirill Yukhin > wrote: >>> >>> OK. >>> >>> Thanks, >>> Uros. >> >> Great, >> could anybody please commit that? >> > > I checked it in for you. > > -- > H.J. >

[i386, PR50740] CPUID leaf 7 for BMI/BMI2/AVX2 feature detection not qualified with max_level and doesn't use subleaf

Hello, Here is the patch which checks CPUID correctly to get BMI/BMI2/AVX2 feature. ChangeLog entry is: 2011-10-21 H.J. Lu Kirill Yukhin * config/i386/driver-i386.c (host_detect_local_cpu): Do cpuid 7 only if max_level allows that. testsuite/ChangeLg entry is

Re: [i386, PR50740] CPUID leaf 7 for BMI/BMI2/AVX2 feature detection not qualified with max_level and doesn't use subleaf

Thanks, Updated testsuite/ChangeLog: 2011-10-21 H.J. Lu Kirill Yukhin * gcc.target/i386/avx2-check.h (main): Check CPUID level correctly. * gcc.target/i386/bmi2-check.h: Ditto. Could anybody please commit that? K On Fri, Oct 21, 2011 at 4:56 PM, Uros

Re: [i386, PR50740] CPUID leaf 7 for BMI/BMI2/AVX2 feature detection not qualified with max_level and doesn't use subleaf

Thanks! K On Fri, Oct 21, 2011 at 6:34 PM, Uros Bizjak wrote: > On Fri, Oct 21, 2011 at 3:58 PM, Kirill Yukhin > wrote: > >> Updated testsuite/ChangeLog: >> 2011-10-21  H.J. Lu   >>            Kirill Yukhin   >> >>        * gcc.target/i386

MAINTAINERS: add myself

Hi folks, I've just committed this: Index: ChangeLog === --- ChangeLog (revision 180428) +++ ChangeLog (revision 180429) @@ -1,3 +1,7 @@ +2011-10-25 Kirill Yukhin + + * MAINTAINERS (Write After Approval): Add m

Re: [RFC PATCH] Gather vectorization (PR tree-optimization/50789)

Hi Jacob, this looks really cool. I have a liitle question, since I do not understand vectorizer as good. Say, we have a snippet: int *p; int idx[N]; int arr[M]; for (...) { p[i%4] += arr[idx[I]]; } As far as I understand, we cannot do gather we, since p may point to somewere in arr, and, idx ma

Re: [PATCH] Intrinsics for ADCX

> Here is the patch with some obvious fixes. If there are no objections, > could anyone please check it in? Done: http://gcc.gnu.org/ml/gcc-cvs/2012-08/msg00203.html Thanks, K

Re: [PATCH] Intrinsics for ADCX

> > Ok. Checked in: http://gcc.gnu.org/ml/gcc-cvs/2012-08/msg00231.html Thanks, K

Re: [PATCH] RDSEED-builtin Description Fix

> OK for mainline. Thanks! http://gcc.gnu.org/ml/gcc-cvs/2012-08/msg00264.html K

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