On 25 Sep 13:42, Kirill Yukhin wrote:
> Hello,
> As suggested, this is splitted out part of [52/n] patch,
> which introduces new vec2mask and mask2vec insn patterns.
>
> As suggested, I've got rid off use of UNSPEC_CVTINT2MASK
> unspec. Unfortunatelly, only partially.
> I suppose, that vec2mask generic RTX will be too complex:
> get most significant bit of each vec elt & compare it
> with zero setting destination mask register accordingly.
> If this approach is preferrable: I ready to do that.
>
> Testing in progress.
> Is it ok for trunk if pass?
Patch updated (I didn't know that internal operand in define_expand
should appear last).
Testing pass.
--
Thanks, K
commit 88cb02d69d28b8a11162db57f092a2560dd5a867
Author: Kirill Yukhin <kirill.yuk...@intel.com>
Date: Thu Sep 25 12:01:15 2014 +0400
AVX-512. 52.1. D2M and M2D patterns.
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 690bed5..9566884 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -618,6 +618,15 @@
return op == CONST0_RTX (mode);
})
+;; Match -1.
+(define_predicate "constm1_operand"
+ (match_code "const_int,const_double,const_vector")
+{
+ if (mode == VOIDmode)
+ mode = GET_MODE (op);
+ return op == CONSTM1_RTX (mode);
+})
+
;; Match one or vector filled with ones.
(define_predicate "const1_operand"
(match_code "const_int,const_double,const_vector")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e7646d7..ffc831f 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -132,6 +132,7 @@
;; For AVX512BW support
UNSPEC_PSHUFHW
UNSPEC_PSHUFLW
+ UNSPEC_CVTINT2MASK
;; For AVX512DQ support
UNSPEC_REDUCE
@@ -4868,6 +4869,72 @@
(set_attr "prefix" "evex")
(set_attr "mode" "V8DF")])
+(define_insn "<avx512>_cvt<ssemodesuffix>2mask<mode>"
+ [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
+ (unspec:<avx512fmaskmode>
+ [(match_operand:VI12_AVX512VL 1 "register_operand" "v")]
+ UNSPEC_CVTINT2MASK))]
+ "TARGET_AVX512BW"
+ "vpmov<ssemodesuffix>2m\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "<avx512>_cvt<ssemodesuffix>2mask<mode>"
+ [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
+ (unspec:<avx512fmaskmode>
+ [(match_operand:VI48_AVX512VL 1 "register_operand" "v")]
+ UNSPEC_CVTINT2MASK))]
+ "TARGET_AVX512DQ"
+ "vpmov<ssemodesuffix>2m\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_expand "<avx512>_cvtmask2<ssemodesuffix><mode>"
+ [(set (match_operand:VI12_AVX512VL 0 "register_operand")
+ (vec_merge:VI12_AVX512VL
+ (match_dup 2)
+ (match_dup 3)
+ (match_operand:<avx512fmaskmode> 1 "register_operand")))]
+ "TARGET_AVX512BW"
+ {
+ operands[2] = CONSTM1_RTX (<MODE>mode);
+ operands[3] = CONST0_RTX (<MODE>mode);
+ })
+
+(define_insn "*<avx512>_cvtmask2<ssemodesuffix><mode>"
+ [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VI12_AVX512VL
+ (match_operand:VI12_AVX512VL 2 "constm1_operand")
+ (match_operand:VI12_AVX512VL 3 "const0_operand")
+ (match_operand:<avx512fmaskmode> 1 "register_operand" "Yk")))]
+ "TARGET_AVX512BW"
+ "vpmovm2<ssemodesuffix>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_expand "<avx512>_cvtmask2<ssemodesuffix><mode>"
+ [(set (match_operand:VI48_AVX512VL 0 "register_operand")
+ (vec_merge:VI48_AVX512VL
+ (match_dup 2)
+ (match_dup 3)
+ (match_operand:<avx512fmaskmode> 1 "register_operand")))]
+ "TARGET_AVX512DQ"
+ "{
+ operands[2] = CONSTM1_RTX (<MODE>mode);
+ operands[3] = CONST0_RTX (<MODE>mode);
+ }")
+
+(define_insn "*<avx512>_cvtmask2<ssemodesuffix><mode>"
+ [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VI48_AVX512VL
+ (match_operand:VI48_AVX512VL 2 "constm1_operand")
+ (match_operand:VI48_AVX512VL 3 "const0_operand")
+ (match_operand:<avx512fmaskmode> 1 "register_operand" "Yk")))]
+ "TARGET_AVX512DQ"
+ "vpmovm2<ssemodesuffix>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_insn "sse2_cvtps2pd<mask_name>"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(float_extend:V2DF
