On 02 Jul 12:45, Kirill Yukhin wrote:
> Hello,
Pls disregard this mail and use previous one. Sorry.
--
Thanks, K
Hello Tobias
On 02 Jul 14:11, Tobias Burnus wrote:
> Kirill Yukhin wrote:
> > This branch should be capable to perform offload to Intel targets (Xeon PHI)
>
> Which Xeon PHI does it support? Knights Corner, Knights Landing, both?
Currently liboffloadmic supports KNC. Future
On 02 Jul 15:06, Tobias Burnus wrote:
> Hmm, I had hoped that the work would include the forward porting of HJ's
> patches from
> https://software.intel.com/en-us/articles/intel-manycore-platform-software-stack-mpss
> to the current trunk. In my understanding, that's all what is needed, isn't
> i
Hello Marc,
On 28 Jun 12:42, Marc Glisse wrote:
> It would enable a number of optimizations, like constant
> propagation, FMA contraction, etc. It would also allow us to remove
> several builtins.
This should be main motivation for replacing built-ins.
But this approach IMHO should only be used for
Hello,
Thanks!
On 15 Apr 12:30, Ryan Mansfield wrote:
> OK for trunk and gcc-5-branch?
The patch is OK for trunk and gcc-5-branch (when it is open).
--
K
Hello Andreas,
On 19 Apr 21:56, Andreas Tobler wrote:
> Done so and tested on FreeBSD amd64-unknown-freebsd11.0 and CentOS7.1.
>
> Ok for trunk?
The patch is OK for trunk and for gcc-5 branch (when it is open).
Thanks for fixing this!
--
K
Hello,
On 23 Mar 19:02, Ilya Tocar wrote:
> Hi,
>
> I've renamed EXT_SSE_REG_P into EXT_REX_SSE_REG_P for consistency.
> Ok for stage1?
Patch is OK for stage1.
--
Thanks, K
> On 19 Mar 12:24, Ilya Tocar wrote:
> > Hi,
> >
> > There were some discussion about "x" constraints being too conservat
bdb50f43ed940261230953a647c6a7197bc60c97
Author: Kirill Yukhin
Date: Tue Apr 7 17:37:01 2015 +0300
Fix PR65676.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 02b5103..a02e004 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -35863,6 +35863,15 @@ safe_vector_operand (rtx x
AVX-512DQ
is disabled.
gcc/testsuite/
* gcc.target/i386/pr65671.c: New.
--
Thanks, K
commit cb8d5b1c3156d81ae81600217d0861be1aade0ec
Author: Kirill Yukhin
Date: Thu Apr 9 13:05:54 2015 +0300
Fix PR target/65671. Generate 32x4 extract even for DF in absence of
AVX-512DQ.
dif
On 09 Apr 16:41, Jakub Jelinek wrote:
> Please use
> PR target/65671
> * config/i386/sse.md (vec_extract_hi_): ...
> (both PR line and name of pattern missing).
Sure, thanks!
--
K
Hello Rainer,
On 08 Apr 15:27, Rainer Orth wrote:
> Ok for mainline?
Patch is ok, thanks!
--
K
On 13 Apr 21:16, Rainer Orth wrote:
> Kirill Yukhin writes:
>
> > Hello Rainer,
> > On 08 Apr 15:27, Rainer Orth wrote:
> >> Ok for mainline?
> >
> > Patch is ok, thanks!
>
> Thanks. How about the gcc-5 branch? It would be good to avoid those
&g
Ditto.
* config/i386/ia32intrin.h (__bsrq): Explicitly convert return value.
testsuite/
PR target/65744
* gcc.target/i386/pr65744.c: New.
--
Thanks, K
commit f69a7bdc20206ec864cb7d8b2556bdf5941d5131
Author: Kirill Yukhin
Date: Mon Apr 13 20:24:52 2015 +0300
Fix PR target/
Hello,
I am starting (hopefully small) serie of patches to support
new ABI dedicated for Intel's MicroController Units [1].
Support for new arch was introduced into Binutils in a few threads, e.g. [2].
This patchset includes:
- Support in GCC: new switch (-miamcu), macro etc.
- Changes to libr
Hello,
This patch introduces basic support into GCC.
Bootstrapped and regtested.
/
* configure.ac (ospace_frag): Enable for i?86*-*-elfiamcu
target.
* configure: Regenerate.
gcc/
* config.gcc: Support i[34567]86-*-elfiamcu target.
* config/i386/iamcu.h: New
Hello,
Patch in the bottom adds support of IA MCU psABI to libgcc
(enables soft-fp) and libdecnumber (enables it for IA MCU).
Bootstrapped and regtested on top of [1/3] patch.
config/
* dfp.m4 (enable_decimal_float): Also set to yes for
i?86*-*-elfiamcu target.
gcc/
* con
Hello,
This patch introduces tests for new psABI.
gcc/testsuite/
* gcc.target/i386/iamcu/abi-iamcu.exp: New file.
* gcc.target/i386/iamcu/args.h: Likewise.
* gcc.target/i386/iamcu/asm-support.S: Likewise.
* gcc.target/i386/iamcu/defines.h: Likewise.
* gcc.ta
Hello,
Patch in the bottom uses proper check of valid memory
in `misaligned_operand' predicate.
gcc/
* config/i386/predicates.md (misaligned_operand): Properly
check if operand is memory.
Bootstrapped and reg-tested.
Is it ok for trunk?
--
Thanks, K
diff --git a/gcc/config/i3
Hello Richard, Jan,
On 16 Oct 13:22, Jakub Jelinek wrote:
> On Thu, Oct 16, 2014 at 03:17:36PM +0400, Ilya Verbin wrote:
> The rest LGTM, but please run it through LTO review (Richard/Honza) too.
Ping?
--
Thanks, k
>
> Jakub
Hello Richard, Jan,
On 08 Oct 11:23, Jakub Jelinek wrote:
> On Tue, Sep 30, 2014 at 06:53:20PM +0400, Ilya Verbin wrote:
> > Bootstrapped and regtested on top of patch 2. Is it OK for trunk?
>
> LGTM, with the requested var/section renames.
> Would like if Honza and/or Richard had a look at the c
On 30 Oct 09:32, Uros Bizjak wrote:
> On Thu, Oct 30, 2014 at 8:50 AM, Jan Beulich wrote:
> > gcc/testsuite:
> > 2014-10-30 Jan Beulich
> >
> > * gcc.target/i386/i386.exp: Extend option set to test
> > vect-args.c with to include -mavx, -mavx2, and -mavx512f.
> > * gcc.t
Hello,
On 24 Oct 17:56, Yury Gribov wrote:
...
> +const struct test_data_t test_data[] = {
> + { STRTOL, "-0x8000", 0, -0x8000L, 0 },
...
> + switch (test_data[i].fun)
> + {
> + case STRTOL:
> + res = strtol (test_data[i].nptr, 0, test_data[i].base);
> + bre
Hello Richard,
On 05 Nov 13:50, Jakub Jelinek wrote:
> On Wed, Nov 05, 2014 at 03:46:55PM +0300, Ilya Verbin wrote:
> > +
> >node->register_symbol ();
>
> LGTM.
Are you ok with the patch?
>
> Jakub
--
Thanks, K
Hello Marc, Uroš,
On 10 Nov 21:33, Uros Bizjak wrote:
> On Sun, Nov 9, 2014 at 5:26 PM, Marc Glisse wrote:
> > Hello,
> >
> > < > and == for integer vectors of size 128. I was surprised not to find
> > _mm_cmplt_epi64 anywhere. Note that I can do the same for size 256, but not
> > 512, there is no
On 11 Nov 10:28, Marc Glisse wrote:
> On Tue, 11 Nov 2014, Kirill Yukhin wrote:
>
> >Hello Marc, Uroš,
> >On 10 Nov 21:33, Uros Bizjak wrote:
> >>On Sun, Nov 9, 2014 at 5:26 PM, Marc Glisse wrote:
> >>>Hello,
> >>>
> >>>< >
Hello Richard,
On 12 Nov 10:23, Richard Biener wrote:
> On Wed, 5 Nov 2014, Ilya Verbin wrote:
> Yes please.
>
> Please make sure that regular LTO bootstrap still works - LTO is
> only tested lightly in the testsuite.
Current main trunk fails to bootstrap w/ `bootstrap-lto':
git/gcc/configure --e
On 12 Nov 15:09, Richard Biener wrote:
> On Wed, 12 Nov 2014, Kirill Yukhin wrote:
>
> > Hello Richard,
> > On 12 Nov 10:23, Richard Biener wrote:
> > > On Wed, 5 Nov 2014, Ilya Verbin wrote:
> > > Yes please.
> > >
> > > Please mak
Hello Uroš,
On 05 Aug 14:22, Uros Bizjak wrote:
> Hello!
>
> Attached patch was inspired by assembly from PR 72805 testcase.
> Currently, the compiler generates:
>
> test:
> vpternlogd $0xFF, %zmm0, %zmm0, %zmm0
> vpxord %zmm1, %zmm1, %zmm1
> vpcmpd $1, %zmm1, %zmm0
d6fe7376e4ce845b4330b45514fded7b2d890573
Author: Kirill Yukhin
Date: Mon Aug 22 18:34:52 2016 +0300
AVX-512. Fix operands order in kunpack check.
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-klogic-2.c
b/gcc/testsuite/gcc.target/i386/avx512f-klogic-2.c
index feff955..ec09e4c 100644
--- a/gcc
Hello,
On 29.08.2016 14:58, Marc Glisse wrote:
Hello,
this patch gets rid of a few more builtins (well, I actually kept
them, since Ada users may still need them). I had to tweak the flags
for pr59539-2.c, otherwise the compiler thinks it is more efficient to
split the loads, reading 128 bits
Hi,
Remove identical conditions from AND
in return.
Will check-in after bootstrap/regtest on i386|x86_64 as obvious.
gcc/
* dwarf2out.c (dw_val_equal_p): Remove redundant condition in
return statement.
--
Thanks, K
commit 4c71ef36cda91edaef731e460a58fe09942b2d93
Author: Kirill Yukhin
On 02.09.2016 20:00, Jakub Jelinek wrote:
On Fri, Sep 02, 2016 at 07:52:45PM +0300, Kirill Yukhin wrote:
Hi,
Remove identical conditions from AND
in return.
Will check-in after bootstrap/regtest on i386|x86_64 as obvious.
gcc/
* dwarf2out.c (dw_val_equal_p): Remove redundant condition in
0d211
Author: Kirill Yukhin
Date: Fri Sep 2 23:14:05 2016 +0300
Compare first element of char* instead of pointer.
diff --git a/gcc/ubsan.c b/gcc/ubsan.c
index 5cbc98d..d3bd8e3 100644
--- a/gcc/ubsan.c
+++ b/gcc/ubsan.c
@@ -1469,7 +1469,7 @@ ubsan_use_new_style_p (location_
zero before dereferencing it.
--
Thanks, K
commit 9b822dfb4db14ce762a8d55cf76c677f3fae04bc
Author: Kirill Yukhin
Date: Fri Sep 2 23:40:55 2016 +0300
Access odr_type only if odr_type_ptr is not 0.
diff --git a/gcc/ipa-devirt.c b/gcc/ipa-devirt.c
index 2cf018b..cca912c 100644
--- a/gcc/ipa
On 02.09.2016 23:56, Jakub Jelinek wrote:
On Fri, Sep 02, 2016 at 11:53:01PM +0300, Kirill Yukhin wrote:
gcc/
* gcc/ipa-devirt.c (get_odr_type): Check odr_types_ptr for
zero before dereferencing it.
I've already tested/posted
http://gcc.gnu.org/ml/gcc-patches/2016-09/msg
On 02.09.2016 23:54, Jakub Jelinek wrote:
Sure, sorry.
gcc/
* ubsan.c (ubsan_use_new_style_p): Fix check for empty string.
--
Thanks, K
Hello Ilya.
On 23 May 19:11, Ilya Verbin wrote:
> Hi!
>
> This patch adds missed 512-bit rounding builtins for vectorization.
> Regtested on x86_64-linux and i686-linux. OK for trunk?
Patch is OK.
--
Thanks, K
Hi Jakub,
On 23 May 19:15, Jakub Jelinek wrote:
> Hi!
>
> The vbroadcastss and vpermilps insns are already in AVX512F & AVX512VL,
> so can be used with v instead of x, the splitter case where we for AVX
> emit vpermilps plus vpermf128 is more problematic, because the latter
> insn isn't available
On 23 May 19:17, Jakub Jelinek wrote:
> Hi!
>
> This pattern is used to improve __builtin_shuffle in some cases;
> VPALIGNR is AVX512BW & AVX512VL.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
OK.
--
Thanks, K
On 23 May 19:21, Jakub Jelinek wrote:
> Hi!
>
> These insns are available in AVX512VL, so we can just use v instead of x.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
OK.
--
Thanks, K
r operand.
testsuite/
* gcc.target/i386/prr71346.c: New test.
--
Thanks, K
commit 6c0021bea7a5be8d9a10ef3f2fb30c1228f53d48
Author: Kirill Yukhin
Date: Mon May 30 16:31:28 2016 +0300
AVX-512. Fix PR target/71346.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b348f2d..
Hello Jakub,
On 01 Jun 22:17, Jakub Jelinek wrote:
> Hi!
>
> This is the last pattern I'm aware of that didn't have any v/Yv constraints
> that ought to be changed (there perhaps are others which have v/Yv in some
> of the alternatives, but not in all the ones that could use it).
>
> The testcase
On 02 Jun 17:17, Ilya Verbin wrote:
> On Mon, May 23, 2016 at 19:11:53 +0300, Ilya Verbin wrote:
> > This patch adds missed 512-bit rounding builtins for vectorization.
> > Regtested on x86_64-linux and i686-linux. OK for trunk?
> >
> > gcc/
> > * config/i386/i386-builtin-types.def: Add V16SI
Hi Jakub,
On 23 May 19:26, Jakub Jelinek wrote:
> Hi!
>
> Not sure how to easily test these.
> In any case, for the vinsert* case, we don't have vinserti128 nor
> vinsertf128 in evex, so need to use vinsert[if]{64x4,32x4} or
> for DQ {64x2,32x8}. For the case with zero in the other half,
> we nee
Hello,
On 29 Jun 13:12, Yuri Rumyantsev wrote:
> Hi All,
>
> Here is a simple patch which generates on-operand vperm instructions
> introduced in knl.
> Using this patch we got +5% speed-up on one important benchmark.
>
> Bootstrapping and regression testing did not show any new failures.
> Is it
Hello Olga, Sebastian,
On 16 Oct 11:20, Peryt, Sebastian wrote:
> Hi,
>
> This patch written by Olga Makhotina adds missing intrinsics for
> REDUCE[SD,SS].
>
> 16.10.2017 Olga Makhotina
>
> gcc/
> * config/i386/avx512dqintrin.h (_mm_mask_reduce_sd,
> _mm_maskz_reduce_sd, _mm_mask_r
Hello Sergey,
On 06 Oct 14:20, Shalnov, Sergey wrote:
> Jakub,
> I completely agree with you. I fixed the patch.
> Currently, TARGET_PREFER256 will work on architectures with 512VL. It will
> not work otherwise.
>
> I will try to find better solution for this. I think I need to look into
> regis
Hello Jakub, Uroš,
On 04 Oct 13:41, Uros Bizjak wrote:
> On Wed, Oct 4, 2017 at 10:33 AM, Jakub Jelinek wrote:
> > Hi!
> >
> > Most AVX* instructions have the same insn name between VEX and EVEX
> > encoded insns and whether it is EVEX or VEX encoded is determined by
> > the operands by the assemb
Hello Jakub,
On 04 Oct 21:29, Jakub Jelinek wrote:
> Hi!
>
> EVEX encoded vector shifts by immediate allow memory operand as input.
> We handle this right for the sra patterns by having 3 distinct
> define_insns, one TARGET_AVX512VL with masking, where the non-masked
> insn names start with *, tha
Jelinek [mailto:ja...@redhat.com]
> > Sent: Friday, October 13, 2017 9:08 AM
> > To: Koval, Julia
> > Cc: GCC Patches ; Uros Bizjak
> > ; Kirill Yukhin
> > Subject: Re: [x86] GFNI enabling[1/4]
> >
> > On Fri, Oct 13, 2017 at 07:03:14AM +, Koval, Julia wro
Hello Jakub, Uroš, Jakub
On 04 Oct 21:35, Jakub Jelinek wrote:
> Hi!
>
> The following patch tweaks the TImode vector shifts similarly
> to the earlier vector shift patch, so that for shifts by immediate
> we can accept a memory input. Additionally, it removes the vec_shl_*
> expander, because th
cc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On
> Behalf Of Kirill Yukhin
> Sent: Wednesday, October 18, 2017 8:10 PM
> To: Shalnov, Sergey
> Cc: Jakub Jelinek ; 'gcc-patches@gcc.gnu.org'
> ; 'ubiz...@gmail.com' ;
> Senkevich, Andrew
Hello Jakub,
On 24 Oct 13:01, Jakub Jelinek wrote:
> http://gcc.gnu.org/ml/gcc-patches/2017-10/msg00525.html
> PR target/82460 - improve AVX512* vperm[ti]2*
> Kyrill, can you please review this one?
Your patch is OK for trunk.
--
Thanks, K
>
> Thanks
>
> Jakub
On 24 Oct 19:14, Uros Bizjak wrote:
> On Tue, Oct 24, 2017 at 4:46 PM, Jakub Jelinek wrote:
> > On Tue, Oct 24, 2017 at 05:44:44AM -0700, H.J. Lu wrote:
> >> > What I can see from config/atom.md:
> >> > ;; if palignr or psrldq
> >> > (define_insn_reservation "atom_sseishft_2" 1
> >> > (and (eq_
Hello Olga, Sebastian,
On 20 Oct 08:36, Peryt, Sebastian wrote:
> Hi,
>
> This patch written by Olga Makhotina adds listed below missing intrinsics:
> _mm512_[mask_]cmpeq_[pd|ps]_mask
> _mm512_[mask_]cmple_[pd|ps]_mask
> _mm512_[mask_]cmplt_[pd|ps]_mask
> _mm512_[mask_]cmpneq_[pd|ps]_mask
> _mm512
On 17 Oct 12:58, Koval, Julia wrote:
> Hi, this is the second patch of enabling GFNI ISASET. It adds GF2P8AFFINEINV
> instruction.
> The instruction is described here:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
Hello Julia!
On 30 Oct 19:02, Koval, Julia wrote:
> Hi,
> Fixed that.
Your patch is OK for trunk. I've comitted it w/ minor re-indentation in
gcc/ChangeLog entry.
--
Thanks, K
> > >
> > > Ok for trunk?
> > Few comments:
> > 1. Why copyright in config/i386/gfniintrin.h starts from 2014?
> >
> > 2.
%0, %1, %2}): Changed to ...
> v\t{%2,
> %1, %0|
> %0, %1, %2} ... this.
> (v\t{%2, %1,
> %0|
> %0, %1, %2}): Changed to
> ...
>
> v\t{%2, %1,
> %0|
> %0, %1, %2}
> ... this.
Max line length is 79 characters I suppos
bastian
>
> -----Original Message-
> From: Kirill Yukhin [mailto:kirill.yuk...@gmail.com]
> Sent: Wednesday, July 5, 2017 12:36 PM
> To: Peryt, Sebastian
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATHC][x86] Scalar mask and round RTL templates
>
> On 05 Jul 06:38,
Hello Julia,
On 21 Jun 08:41, Koval, Julia wrote:
> Hi,
> This patch removes old parallel code for avx512er. Parallel in this case
> can't be generated anymore, because all existing patterns were reworked to
> unspec in r249423 and r249009. Ok for trunk?
Your patch is OK for trunk. I've comitted
On 06 Jul 09:35, Peryt, Sebastian wrote:
> Hi,
>
> This patch adds missing intrinsics for VGETEXPSD, VGETEXPSS, VGETMANTSD,
> VGETMANTSS.
>
> 2017-07-06 Sebastian Peryt
>
> gcc/
> * config/i386/avx512fintrin.h (_mm_mask_getexp_round_ss,
> _mm_maskz_getexp_round_ss, _mm_mask
Hello Julia,
On 26 May 09:13, Koval, Julia wrote:
> Hi,
> This patch fixes these PR's. Ok for trunk?
>
> gcc/
> * config/i386/subst.md (round): Fix round pattern.
> * config/i386/i386.c (ix86_erase_embedded_rounding):
> Fix erasing rounding for the fixed pattern.
>
> Thanks,
> J
On 31 May 11:38, Kirill Yukhin wrote:
> Hello Julia,
> On 26 May 09:13, Koval, Julia wrote:
> > Hi,
> > This patch fixes these PR's. Ok for trunk?
> >
> > gcc/
> > * config/i386/subst.md (round): Fix round pattern.
> > * config/i386/i38
On 31 May 17:28, Uros Bizjak wrote:
> On Wed, May 31, 2017 at 12:33 PM, Senkevich, Andrew
> wrote:
> > Hi,
> >
> > attached patches are for renaming __builtin_ia32_kmov16 to
> > __builtin_ia32_kmovw in GCC 5.* and 6.* branches since it was renamed in
> > master.
> > Bootstrapped and regtested on
Hi,
In addition to Uroš's inputs:
> diff --git a/gcc/config/i386/avx512vpopcntdqintrin.h
> b/gcc/config/i386/avx512vpopcntdqintrin.h
> new file mode 100644
> index 000..28305f6
> --- /dev/null
> +++ b/gcc/config/i386/avx512vpopcntdqintrin.h
> @@ -0,0 +1,90 @@
> +/* Copyright (C) 2016 Free Softw
On 10 Jan 15:00, Andrew Senkevich wrote:
> 2017-01-10 13:31 GMT+03:00 Uros Bizjak :
> > On Tue, Jan 10, 2017 at 11:21 AM, Andrew Senkevich
> > wrote:
> >> 2017-01-10 13:04 GMT+03:00 Kirill Yukhin :
> >>> Hi,
> >>> In addition to Ur
Hi Anrey,
On 17 Jan 14:04, Andrew Senkevich wrote:
> 2017-01-17 1:55 GMT+03:00 Jakub Jelinek :
> > On Tue, Jan 17, 2017 at 01:30:11AM +0300, Andrew Senkevich wrote:
> >> here is one more part of intrinsics for k-mask registers shifts:
> >
> > The software developer manuals describe KSHIFT{L,R}* lik
Hi Julia,
On 17 Jan 12:57, Koval, Julia wrote:
> Hi,
> I added builtin changes to Jakub's patch from
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=76731 It fixes the issue, when
> gather/scatter intrinsics has wrong spec. Ok for trunk?
Patch is OK for main trunk
--
Thanks, K
>
> gcc/
> * con
Hi Andrew,
On 18 Jan 15:45, Andrew Senkevich wrote:
> 2017-01-17 16:51 GMT+03:00 Jakub Jelinek :
> > On Tue, Jan 17, 2017 at 04:03:08PM +0300, Andrew Senkevich wrote:
> >> > I've played a bit w/ SDE. And looks like operands are not early clobber:
> >> > TID0: INS 0x004003ee AVX5
On 19 Jan 19:42, Andrew Senkevich wrote:
> 2017-01-19 13:39 GMT+03:00 Kirill Yukhin :
> > Hi Andrew,
> > On 18 Jan 15:45, Andrew Senkevich wrote:
> >> 2017-01-17 16:51 GMT+03:00 Jakub Jelinek :
> >> > On Tue, Jan 17, 2017 at 04:03:08PM +0300, Andrew Senkevich
Hi,
On 20 Jan 14:46, Uros Bizjak wrote:
> On Fri, Jan 20, 2017 at 2:32 PM, Andrew Senkevich
> wrote:
>
> > here is intrinsics for ktest{b,w,d,q} and kortest{b,w,d,q}. Is it Ok?
> >
> > gcc/
> > * config/i386/avx512bwintrin.h: Add k-mask test, kortest intrinsics.
> > * config/i386/avx512dqi
On 20 Jan 23:03, Andrew Senkevich wrote:
> 2017-01-20 20:08 GMT+03:00 Kirill Yukhin :
> > Hi,
> > On 20 Jan 14:46, Uros Bizjak wrote:
> >> On Fri, Jan 20, 2017 at 2:32 PM, Andrew Senkevich
> >> wrote:
> >>
> >> > here is intrin
Hello Thomas,
On 26 Jan 10:14, Thomas Schwinge wrote:
> I see:
>
> {+FAIL: gcc.target/i386/avx512f-ktestw-2.c (test for excess errors)+}
> {+UNRESOLVED: gcc.target/i386/avx512f-ktestw-2.c compilation failed to
> produce executable+}
>
> ... because of:
>
> /tmp/ccjv3mX2.s: Assembler me
Hi,
On 26 Jan 12:49, Thomas Schwinge wrote:
> Hi!
>
> On Thu, 26 Jan 2017 02:44:56 -0800, Kirill Yukhin
> wrote:
> > On 26 Jan 10:14, Thomas Schwinge wrote:
> > > I see:
> > >
> > > {+FAIL: gcc.target/i386/avx512f-ktestw-2.c (test for excess erro
On 26 Jan 13:05, Jakub Jelinek wrote:
> On Thu, Jan 26, 2017 at 03:53:44AM -0800, Kirill Yukhin wrote:
> > Hi,
> > On 26 Jan 12:49, Thomas Schwinge wrote:
> > > Hi!
> > >
> > > On Thu, 26 Jan 2017 02:44:56 -0800, Kirill Yukhin
> > > wr
Hello,
Two tests are failing for me on 32b variant bacause of wrong constants.
Fixed. Tests now pass (under SDE).
gcc/testsuite/
* gcc.target/i386/avx512bw-kshiftlq-2.c: Use unsigned long long
constant.
* gcc.target/i386/avx512bw-kshiftrq-2.c: Ditto.
If no objections from
Hi Jakub,
On 30 Mar 00:36, Jakub Jelinek wrote:
> Hi!
>
> As the testcase shows, we ICE with -mavx512f -ffloat-store, because
> at -O0 during expansion the destination is MEM, and the corresponding dup
> operand is some pseudo. There are *_mask patterns that have just
> register_operand / =v for t
Hi Jakib,
On 07 Apr 16:52, Jakub Jelinek wrote:
> Hi!
>
> This patch is slightly larger, so I haven't included it in the patch I've
> sent a few minutes ago.
>
> I've looked at godbolt for what ICC generates for these and picked sequences
> that generate approx. as good code as that. For
> min_epi
K
commit 72e85f1b936d61edc93603862c810a8b4817b8a7
Author: Kirill Yukhin
Date: Thu Mar 17 18:05:22 2016 +0300
AVX-512. Use vpbroadcastq for broadcasting DF values to 128b regs.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3c521b3..b25c246 100644
--- a/gcc/config/i386/sse.md
+++ b/
ew test.
commit 954aa2747cc3387e5a61cbe0fd029ee7a938072e
Author: Kirill Yukhin
Date: Fri Mar 18 17:30:42 2016 +0300
AVX-512. Disable reg->xmm broadcast in AVX pattern when AVX-VL512 is on.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3c521b3..fc6d597 100644
--- a/gcc
On 21 Mar 11:37, Richard Biener wrote:
> On Mon, 21 Mar 2016, Kirill Yukhin wrote:
>
> > Hello,
> >
> > Attached patch blocks third alternative of broadcast pattern
> > when compiled w/ -mavx512vl.
> > Issue is that third alternative is subject for subseq
--
Thanks, K
commit 68c7dd92daad8d4365d0dcd3b1aa4c3ba2658660
Author: Kirill Yukhin
Date: Mon Mar 21 14:28:58 2016 +0300
AVX-512. Fix PR70325.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3d8dbc4..9df5055 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -32429,6 +32429,9 @@ def_builtin
Hi Jakub,
On 21 Mar 21:10, Jakub Jelinek wrote:
> vec_interleave_lowv4sf only supports =x, x, x alternative, not =v, v, v
> (which should be supportable for AVX512VL only anyway, but probably
> stage1 material), without AVX512VL and with ext sse reg input operand
> we have to either due to interlea
Hi Jakub!
On 21 Mar 21:16, Jakub Jelinek wrote:
> The ix86_expand_vecop_qihi function has been adjusted for AVX512* just
> by changing i < 32 to i < 64 (where both were sometimes wasteful), but
> for !full_interleave that is even wrong, swapping the second and third
> quarter is something that wor
Hi Uroš.
On 22 Mar 09:19, Uros Bizjak wrote:
> OK with a suitable comment describing the reason for special handling.
Thanks!
> BTW: Looking through the builtins, I noticed that some builtin
> descriptions contains duplicated flags (please see attached
> pseudo-patch). Looks like typos to me, but
Emit
vpcmpeqd if AVX2 is enabled.
[1] - https://gcc.gnu.org/ml/gcc-cvs/2011-09/msg00318.html
--
Thanks, K
commit e30c86b06968416e7401a113b866ae353311aa10
Author: Kirill Yukhin
Date: Wed Mar 23 14:08:07 2016 +0300
AVX2. Emit vpcmpeqd for const_m1 only if AVX2 is enabled.
diff --git a/gcc/config
On 23 Mar 04:36, H.J. Lu wrote:
> On Wed, Mar 23, 2016 at 4:28 AM, Kirill Yukhin
> wrote:
> > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > index 1639704..7f5db75 100644
> > --- a/gcc/config/i386/i386.c
> > +++ b/gcc/config/i386/i
On 23 Mar 12:41, Jakub Jelinek wrote:
> On Wed, Mar 23, 2016 at 02:28:03PM +0300, Kirill Yukhin wrote:
> > Hello,
> >
> > `vpcmpeqd' insn is only available in AVX2, however
> > [1] added check for AVX instead. Looks like a typo.
> >
> > Patch in
On 23 Mar 12:55, Jakub Jelinek wrote:
> On Wed, Mar 23, 2016 at 02:47:54PM +0300, Kirill Yukhin wrote:
> > > This code is only executed if standard_sse_constant_p returns 2, which
> > > is for 16-byte vectors and all ones for TARGET_SSE2, and for
> > > 32-byte vecto
>On 23 Mar 13:13, Jakub Jelinek wrote:
> On Wed, Mar 23, 2016 at 03:06:22PM +0300, Kirill Yukhin wrote:
> > On 23 Mar 12:55, Jakub Jelinek wrote:
> > > On Wed, Mar 23, 2016 at 02:47:54PM +0300, Kirill Yukhin wrote:
> > > > > This code is only executed if stan
On 23 Mar 13:28, Uros Bizjak wrote:
> On Wed, Mar 23, 2016 at 12:28 PM, Kirill Yukhin
> wrote:
> > Hello,
> >
> > `vpcmpeqd' insn is only available in AVX2, however
> > [1] added check for AVX instead. Looks like a typo.
> >
> > Patch in the bottom
rget/70406
* gcc.target/i386/pr70406.c: New test.
--
Thanks, K
commit 465529c1aad5a92a7c0b345bf0ab809590dba896
Author: Kirill Yukhin
Date: Fri Mar 25 14:44:18 2016 +0300
AVX-512. Align type of not epxression in the split.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i38
On 29 Mar 19:49, Jakub Jelinek wrote:
> On Tue, Mar 29, 2016 at 11:44:15AM -0600, Jeff Law wrote:
> > On 03/29/2016 11:05 AM, Jakub Jelinek wrote:
> > >Hi!
> > >
> > >The various blendm expanders look like:
> > >(define_insn "_blendm"
> > > [(set (match_operand:V48_AVX512VL 0 "register_operand" "
70453
* gcc.target/i386/pr70453.c: New test.
--
Thanks, K
commit 06a60a6aa22b24962b315de1f07cc75b074e47d2
Author: Kirill Yukhin
Date: Wed Mar 30 17:43:12 2016 +0300
AVX-512. Fix typo in mode attribute.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 44141ea..5f
Hi Ilya,
On 13 Apr 16:29, Ilya Enkovich wrote:
> Hi,
>
> Current kunpck[hi|si|di] patterns emit operands in a wrong order. This
> is compensated by a wrong operands order in vec_pack_trunc_[qi|hi|si]
> expands and therefore we get correct code for vectorized loops. Code
> using kunpck* intrinsics
fiers.
gcc/testsuite/
PR target/70662
* gcc.target/i386/pr70662.c: New test.
--
Thanks, K
commit 4923dda50a901bf38d386818fcc5347e3882cd99
Author: Kirill Yukhin
Date: Fri Apr 15 09:37:48 2016 +0300
AVX-512. Fix PR target/70662 - use proper operand modifiers.
diff --git
On 15 Apr 10:57, Kirill Yukhin wrote:
> Hello,
> Patch in the bottom fixes memory operand modifiers
> for Intel syntax on broadcast patter.
>
> Bootstrapped and regtested on 32,64b x86 target.
>
> I'll check it into main trunk and gcc-5 branch.
>
> gcc/
>
Hi,
On 15 Apr 06:43, H.J. Lu wrote:
> [hjl@gnu-6 gcc]$ /export/build/gnu/gcc-x32/build-x86_64-linux/gcc/xgcc
> -B/export/build/gnu/gcc-x32/build-x86_64-linux/gcc/ -mx32 -mtune=slm
> -fno-diagnostics-show-caret -fdiagnostics-color=never -Og
> -fschedule-insns -fno-tree-fre -mavx512vbmi
> --param
Hi,
On 18 Apr 21:13, Uros Bizjak wrote:
> On Mon, Apr 18, 2016 at 8:40 PM, H.J. Lu wrote:
> > On Sun, Jan 10, 2016 at 11:45 PM, Uros Bizjak wrote:
> >> On Sun, Jan 10, 2016 at 11:32 PM, H.J. Lu wrote:
> >>> Since *mov_internal and _(load|store)_mask patterns
> >>> can handle unaligned load and s
Hi Ilya,
On 19 Apr 19:09, Ilya Enkovich wrote:
> Hi,
>
> vec_unpacks_lo_[si,hi,di] patterns for scalar masks don't need to extend
> mask elements. It means a simple register copy is good enough.
>
> Currently vec_unpacks_lo_hi pattern uses kmovb instruction which requires
> AVX512DQ target. But
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