Hello,
On 23 Mar 19:02, Ilya Tocar wrote:
> Hi,
>
> I've renamed EXT_SSE_REG_P into EXT_REX_SSE_REG_P for consistency.
> Ok for stage1?
Patch is OK for stage1.
--
Thanks, K
> On 19 Mar 12:24, Ilya Tocar wrote:
> > Hi,
> >
> > There were some discussion about "x" constraints being too conservative
> > for some patterns in i386.md.
> > Patch below fixes it. This is probably stage1 material.
> >
> > ChangeLog:
> >
> > gcc/
> >
> 2015-03-23 Ilya Tocar <ilya.to...@intel.com>
>
> * config/i386/i386.h (EXT_REX_SSE_REG_P): New.
> * config/i386/i386.md (*cmpi<FPCMP:unord><MODEF:mode>_mixed): Use "v"
> constraint.
> (*cmpi<FPCMP:unord><MODEF:mode>_sse): Ditto.
> (*movxi_internal_avx512f): Ditto.
> (define_split): Check for xmm16+, when splitting scalar float_extend.
> (*extendsfdf2_mixed): Use "v" constraint.
> (*extendsfdf2_sse): Ditto.
> (define_split): Check for xmm16+, when splitting scalar float_truncate.
> (*truncdfsf_fast_sse): Use "v" constraint.
> (fix_trunc<MODEF:mode><SWI48:mode>_sse): Ditto.
> (*float<SWI48:mode><MODEF:mode>2_sse): Ditto.
> (define_peephole2): Check for xmm16+, when converting scalar
> float_truncate.
> (define_peephole2): Check for xmm16+, when converting scalar
> float_extend.
> (*fop_<mode>_comm_mixed): Use "v" constraint.
> (*fop_<mode>_comm_sse): Ditto.
> (*fop_<mode>_1_mixed): Ditto.
> (*sqrt<mode>2_sse): Ditto.
> (*ieee_s<ieee_maxmin><mode>3): Ditto.
>
>
> ---
> gcc/config/i386/i386.h | 2 ++
> gcc/config/i386/i386.md | 82
> +++++++++++++++++++++++++++----------------------
> 2 files changed, 47 insertions(+), 37 deletions(-)
>
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index 1e755d3..70a471b 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -1477,6 +1477,8 @@ enum reg_class
> #define REX_SSE_REGNO_P(N) \
> IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
>
> +#define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X)))
> +
> #define EXT_REX_SSE_REGNO_P(N) \
> IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
>
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index 1129b93..dc1cd20 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -1639,8 +1639,8 @@
> (define_insn "*cmpi<FPCMP:unord><MODEF:mode>_mixed"
> [(set (reg:FPCMP FLAGS_REG)
> (compare:FPCMP
> - (match_operand:MODEF 0 "register_operand" "f,x")
> - (match_operand:MODEF 1 "nonimmediate_operand" "f,xm")))]
> + (match_operand:MODEF 0 "register_operand" "f,v")
> + (match_operand:MODEF 1 "nonimmediate_operand" "f,vm")))]
> "TARGET_MIX_SSE_I387
> && SSE_FLOAT_MODE_P (<MODEF:MODE>mode)"
> "* return output_fp_compare (insn, operands, true,
> @@ -1666,8 +1666,8 @@
> (define_insn "*cmpi<FPCMP:unord><MODEF:mode>_sse"
> [(set (reg:FPCMP FLAGS_REG)
> (compare:FPCMP
> - (match_operand:MODEF 0 "register_operand" "x")
> - (match_operand:MODEF 1 "nonimmediate_operand" "xm")))]
> + (match_operand:MODEF 0 "register_operand" "v")
> + (match_operand:MODEF 1 "nonimmediate_operand" "vm")))]
> "TARGET_SSE_MATH
> && SSE_FLOAT_MODE_P (<MODEF:MODE>mode)"
> "* return output_fp_compare (insn, operands, true,
> @@ -1959,8 +1959,8 @@
> (set_attr "length_immediate" "1")])
>
> (define_insn "*movxi_internal_avx512f"
> - [(set (match_operand:XI 0 "nonimmediate_operand" "=x,x ,m")
> - (match_operand:XI 1 "vector_move_operand" "C ,xm,x"))]
> + [(set (match_operand:XI 0 "nonimmediate_operand" "=v,v ,m")
> + (match_operand:XI 1 "vector_move_operand" "C ,vm,v"))]
> "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
> {
> switch (which_alternative)
> @@ -4003,7 +4003,9 @@
> (match_operand:SF 1 "nonimmediate_operand")))]
> "TARGET_USE_VECTOR_FP_CONVERTS
> && optimize_insn_for_speed_p ()
> - && reload_completed && SSE_REG_P (operands[0])"
> + && reload_completed && SSE_REG_P (operands[0])
> + && (!EXT_REX_SSE_REG_P (operands[0])
> + || TARGET_AVX512VL)"
> [(set (match_dup 2)
> (float_extend:V2DF
> (vec_select:V2SF
> @@ -4048,9 +4050,9 @@
> "operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));")
>
> (define_insn "*extendsfdf2_mixed"
> - [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,x")
> + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,v")
> (float_extend:DF
> - (match_operand:SF 1 "nonimmediate_operand" "fm,f,xm")))]
> + (match_operand:SF 1 "nonimmediate_operand" "fm,f,vm")))]
> "TARGET_SSE2 && TARGET_MIX_SSE_I387"
> {
> switch (which_alternative)
> @@ -4071,8 +4073,8 @@
> (set_attr "mode" "SF,XF,DF")])
>
> (define_insn "*extendsfdf2_sse"
> - [(set (match_operand:DF 0 "nonimmediate_operand" "=x")
> - (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
> + [(set (match_operand:DF 0 "nonimmediate_operand" "=v")
> + (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "vm")))]
> "TARGET_SSE2 && TARGET_SSE_MATH"
> "%vcvtss2sd\t{%1, %d0|%d0, %1}"
> [(set_attr "type" "ssecvt")
> @@ -4155,7 +4157,9 @@
> (match_operand:DF 1 "nonimmediate_operand")))]
> "TARGET_USE_VECTOR_FP_CONVERTS
> && optimize_insn_for_speed_p ()
> - && reload_completed && SSE_REG_P (operands[0])"
> + && reload_completed && SSE_REG_P (operands[0])
> + && (!EXT_REX_SSE_REG_P (operands[0])
> + || TARGET_AVX512VL)"
> [(set (match_dup 2)
> (vec_concat:V4SF
> (float_truncate:V2SF
> @@ -4228,9 +4232,9 @@
> ;; Yes, this one doesn't depend on flag_unsafe_math_optimizations,
> ;; because nothing we do here is unsafe.
> (define_insn "*truncdfsf_fast_sse"
> - [(set (match_operand:SF 0 "nonimmediate_operand" "=x")
> + [(set (match_operand:SF 0 "nonimmediate_operand" "=v")
> (float_truncate:SF
> - (match_operand:DF 1 "nonimmediate_operand" "xm")))]
> + (match_operand:DF 1 "nonimmediate_operand" "vm")))]
> "TARGET_SSE2 && TARGET_SSE_MATH"
> "%vcvtsd2ss\t{%1, %d0|%d0, %1}"
> [(set_attr "type" "ssecvt")
> @@ -4544,7 +4548,7 @@
> ;; When SSE is available, it is always faster to use it!
> (define_insn "fix_trunc<MODEF:mode><SWI48:mode>_sse"
> [(set (match_operand:SWI48 0 "register_operand" "=r,r")
> - (fix:SWI48 (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
> + (fix:SWI48 (match_operand:MODEF 1 "nonimmediate_operand" "v,m")))]
> "SSE_FLOAT_MODE_P (<MODEF:MODE>mode)
> && (!TARGET_FISTTP || TARGET_SSE_MATH)"
> "%vcvtt<MODEF:ssemodesuffix>2si<SWI48:rex64suffix>\t{%1, %0|%0, %1}"
> @@ -4864,7 +4868,7 @@
> })
>
> (define_insn "*float<SWI48:mode><MODEF:mode>2_sse"
> - [(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
> + [(set (match_operand:MODEF 0 "register_operand" "=f,v,v")
> (float:MODEF
> (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
> "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
> @@ -4967,7 +4971,9 @@
> && optimize_function_for_speed_p (cfun)
> && SSE_REG_P (operands[0])
> && (!SSE_REG_P (operands[1])
> - || REGNO (operands[0]) != REGNO (operands[1]))"
> + || REGNO (operands[0]) != REGNO (operands[1]))
> + && (!EXT_REX_SSE_REG_P (operands[0])
> + || TARGET_AVX512VL)"
> [(set (match_dup 0)
> (vec_merge:V4SF
> (vec_duplicate:V4SF
> @@ -4994,7 +5000,9 @@
> && optimize_function_for_speed_p (cfun)
> && SSE_REG_P (operands[0])
> && (!SSE_REG_P (operands[1])
> - || REGNO (operands[0]) != REGNO (operands[1]))"
> + || REGNO (operands[0]) != REGNO (operands[1]))
> + && (!EXT_REX_SSE_REG_P (operands[0])
> + || TARGET_AVX512VL)"
> [(set (match_dup 0)
> (vec_merge:V2DF
> (float_extend:V2DF
> @@ -13617,10 +13625,10 @@
> ;; so use special patterns for add and mull.
>
> (define_insn "*fop_<mode>_comm_mixed"
> - [(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
> + [(set (match_operand:MODEF 0 "register_operand" "=f,x,v")
> (match_operator:MODEF 3 "binary_fp_operator"
> - [(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,x")
> - (match_operand:MODEF 2 "nonimmediate_operand" "fm,xm,xm")]))]
> + [(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,v")
> + (match_operand:MODEF 2 "nonimmediate_operand" "fm,xm,vm")]))]
> "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
> && COMMUTATIVE_ARITH_P (operands[3])
> && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> @@ -13634,7 +13642,7 @@
> (const_string "fmul")
> (const_string "fop"))))
> (set_attr "isa" "*,noavx,avx")
> - (set_attr "prefix" "orig,orig,vex")
> + (set_attr "prefix" "orig,orig,maybe_evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fop_<mode>_comm_sse"
> @@ -13651,7 +13659,7 @@
> (const_string "ssemul")
> (const_string "sseadd")))
> (set_attr "isa" "noavx,avx")
> - (set_attr "prefix" "orig,vex")
> + (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fop_<mode>_comm_i387"
> @@ -13670,10 +13678,10 @@
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fop_<mode>_1_mixed"
> - [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x")
> + [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,v")
> (match_operator:MODEF 3 "binary_fp_operator"
> - [(match_operand:MODEF 1 "nonimmediate_operand" "0,fm,0,x")
> - (match_operand:MODEF 2 "nonimmediate_operand" "fm,0,xm,xm")]))]
> + [(match_operand:MODEF 1 "nonimmediate_operand" "0,fm,0,v")
> + (match_operand:MODEF 2 "nonimmediate_operand" "fm,0,xm,vm")]))]
> "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
> && !COMMUTATIVE_ARITH_P (operands[3])
> && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> @@ -13694,7 +13702,7 @@
> ]
> (const_string "fop")))
> (set_attr "isa" "*,*,noavx,avx")
> - (set_attr "prefix" "orig,orig,orig,vex")
> + (set_attr "prefix" "orig,orig,orig,maybe_evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*rcpsf2_sse"
> @@ -13710,10 +13718,10 @@
> (set_attr "mode" "SF")])
>
> (define_insn "*fop_<mode>_1_sse"
> - [(set (match_operand:MODEF 0 "register_operand" "=x,x")
> + [(set (match_operand:MODEF 0 "register_operand" "=x,v")
> (match_operator:MODEF 3 "binary_fp_operator"
> - [(match_operand:MODEF 1 "register_operand" "0,x")
> - (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]))]
> + [(match_operand:MODEF 1 "register_operand" "0,v")
> + (match_operand:MODEF 2 "nonimmediate_operand" "xm,vm")]))]
> "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
> && !COMMUTATIVE_ARITH_P (operands[3])"
> "* return output_387_binary_op (insn, operands);"
> @@ -13725,7 +13733,7 @@
> ]
> (const_string "sseadd")))
> (set_attr "isa" "noavx,avx")
> - (set_attr "prefix" "orig,vex")
> + (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "<MODE>")])
>
> ;; This pattern is not fully shadowed by the pattern above.
> @@ -14029,9 +14037,9 @@
> })
>
> (define_insn "*sqrt<mode>2_sse"
> - [(set (match_operand:MODEF 0 "register_operand" "=x")
> + [(set (match_operand:MODEF 0 "register_operand" "=v")
> (sqrt:MODEF
> - (match_operand:MODEF 1 "nonimmediate_operand" "xm")))]
> + (match_operand:MODEF 1 "nonimmediate_operand" "vm")))]
> "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
> "%vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}"
> [(set_attr "type" "sse")
> @@ -16993,17 +17001,17 @@
> (UNSPEC_IEEE_MIN "min")])
>
> (define_insn "*ieee_s<ieee_maxmin><mode>3"
> - [(set (match_operand:MODEF 0 "register_operand" "=x,x")
> + [(set (match_operand:MODEF 0 "register_operand" "=x,v")
> (unspec:MODEF
> - [(match_operand:MODEF 1 "register_operand" "0,x")
> - (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]
> + [(match_operand:MODEF 1 "register_operand" "0,v")
> + (match_operand:MODEF 2 "nonimmediate_operand" "xm,vm")]
> IEEE_MAXMIN))]
> "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
> "@
> <ieee_maxmin><ssemodesuffix>\t{%2, %0|%0, %2}
> v<ieee_maxmin><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> - (set_attr "prefix" "orig,vex")
> + (set_attr "prefix" "orig,maybe_evex")
> (set_attr "type" "sseadd")
> (set_attr "mode" "<MODE>")])
>
> --
> 1.8.3.1
