From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vwsub_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vwsub_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: New test.
---
.../riscv/rvv/base/binop_vx_constraint-120.c | 16
1 file changed, 16 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/binop_v
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector.md: use "zero" reg.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-121.c: New test.
li a5,0
vdiv.vx v0,v1,a5 ===> vdiv.vx v0,v1,zero
---
gcc/config/riscv/vector.md| 5
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (simm5_p): Add vadc/vsbc support.
* config/riscv/riscv-v.cc (simm32_p): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (class vadc): New class.
(class vsbc): Ditto.
(BASE): Ditto.
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Fix indent.
---
gcc/config/riscv/vector-iterators.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 858415bd6
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector.md: Fix indent.
---
gcc/config/riscv/vector.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index aaac32efcce..7da95013156 100644
--- a/gcc/config/risc
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vmadc): New class.
(class vmsbc): Ditto.
(BASE): Define new class.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.de
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/constraints.md (Wbr): Remove unused constraint.
* config/riscv/predicates.md: Fix move operand predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class vnshift): New
class.
(class vncvt_x): Ditto.
(c
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vncvt_x-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_m-1.c: New test.
* gcc.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmv_v_v-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c: New test.
* gcc
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c: New te
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class sat_op): New class.
(class vnclip): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vaadd)
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssrl_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssrl_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssra_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssra_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsmul_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vasubu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vasub_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vaaddu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-122.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv-3.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssrl_vx-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_mu-1.C: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssrl_vv-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_mu-1.C: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssra_vx-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-1.C: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssra_vv-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_mu-1.C: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsmul_vv-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_mu-1.C: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vasubu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_mu-1.C: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vasub_vv-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_mu-1.C: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vaaddu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_mu-1.C: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vaadd_vv-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-1.C: New test.
*
From: Ju-Zhe Zhong
According to RVV ISA, vsmul are not supported for EEW=64 in Zve64*,
so add Full 'V' extension required into predicate of vsmul intrinsics.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (vsmul): Change
iterators.
---
gcc/config/riscv/riscv-vector
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/predicates.md (vector_mask_operand): Refine the codes.
(vector_all_trues_mask_operand): New predicate.
(vector_undef_operand): New predicate.
(ltge_operator): New predicate.
(comparison_except_ltge_operator)
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmsne_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmsne_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmsne_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmsne_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmslt_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmslt_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmslt_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmslt_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmsle_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmsle_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmsle_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmsle_vv_m-1.c: New test.
*
zation if there are any arguments put on stack. */
- if (crtl->args.size != 0)
+ if (known_ne (crtl->args.size, 0))
return;
/* Will point to the first instruction of the function body, after the
diff --git a/gcc/config/riscv/riscv-vector.cc b/gcc/config/riscv/riscv-vector.cc
new
r
@@ -0,0 +1,205 @@
+# Mode iterators and attributes parser for RISC-V 'V' Extension for GNU
compiler.
+# Copyright (C) 2022-2022 Free Software Foundation, Inc.
+# Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd.
+#
+# This file is part of GCC.
+#
+# GCC is f
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (make_type_sizeless): New
function.
(sizeless_type_p): New function.
(vector_builtin_mode): New function.
(vector_legal_vlmul): New function.
(add_vector_type_attribute): New function
fine TARGET_SUPPORTS_WIDE_INT 1
+#define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas ()
+
#endif /* ! GCC_RISCV_H */
diff --git a/gcc/config/riscv/riscv_vector.h b/gcc/config/riscv/riscv_vector.h
new file mode 100644
index 000..ef1820a07cb
--- /dev/null
+++ b/gcc/config/riscv/riscv_ve
r VI [
+ VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI VNx64QI VNx128QI
+ VNx2HI VNx4HI VNx8HI VNx16HI VNx32HI VNx64HI
+ VNx2SI VNx4SI VNx8SI VNx16SI VNx32SI
+ VNx2DI VNx4DI VNx8DI VNx16DI])
\ No newline at end of file
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
new file mod
MODE_P (GET_MODE (op)) && IN_RANGE (INTVAL
(op), -16, 15)"
+
+(define_predicate "reg_or_const_int_operand"
+ (ior (match_operand 0 "register_operand")
+ (match_code "const_wide_int, const_int")))
\ No newline at end of file
diff --git a/gcc/co
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_add_offset): Change
riscv_add_offset as global function.
* config/riscv/riscv-vector.cc (rvv_report_required): New function.
(expand_quotient): New function.
(rvv_expand_poly_move): New function
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-protos.h (rvv_expand_const_vector): New function.
(rvv_expand_const_mask): New function.
(rvv_const_vec_all_same_in_range_p): New function.
* config/riscv/riscv-vector.cc (classify_vtype_field): Move codes
loca
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv.cc (struct riscv_arg_info): Add calling convention
support.
(riscv_get_arg_info): Add calling convention support.
(riscv_function_arg_advance): Add calling convention support.
(riscv_pass_by_reference): Add cal
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.cc
(vset::assemble_name): New function.
(vset::get_argument_types): New function.
(vset::expand): New function.
(vget::assemble_name): New function.
(vget::get_argument_types):
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-vector.cc (rvv_adjust_frame): Adjust frame
manipulation for RVV scalable vector.
* config/riscv/riscv-vector.h (rvv_adjust_frame): Adjust frame
manipulation for RVV scalable vector.
* config/riscv/riscv.cc (riscv_comp
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.cc
(loadstore::assemble_name): New function.
(loadstore::get_argument_types): New function.
(vle::call_properties): New function.
(vle::get_return_type): New function.
(vle::ca
From: zhongjuzhe
This patch adds implementation which missed in the V1 patch.
*** BLURB HERE ***
zhongjuzhe (1):
Add unit-stride load store intrinsics
.../riscv/riscv-vector-builtins-functions.cc | 80 +++
.../riscv/riscv-vector-builtins-functions.def | 7 ++
.../riscv/ris
From: zhongjuzhe
This patch is supplemental patch for [PATCH 14/21] which is missed in v1.
gcc/ChangeLog:
* config/riscv/constraints.md (vi): New constraint.
(vj): New constraint.
(vk): New constraint.
(vc): New constraint.
(Wn5): New constraint.
From: zhongjuzhe
This patche add the testcases that are missed in v1.
*** BLURB HERE ***
zhongjuzhe (34):
RISC-V: Add vlex_1.c
RISC-V: Add vlex_2.c
RISC-V: Add vlex_1.C
RISC-V: Add mask load store testcases
RISC-V: Add vlexff_1.c
RISC-V: Add vlexff_2.c
RISC-V: Add vloxeix_1.c
RI
From: zhongjuzhe
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrinsic/vlex_2.c: New test.
---
.../gcc.target/riscv/rvv/intrinsic/vlex_2.c | 1251 +
1 file changed, 1251 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlex_2.
From: zhongjuzhe
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrinsic/mask_load_store.c: New test.
* gcc.target/riscv/rvv/intrinsic/mask_load_store_31.c: New test.
* gcc.target/riscv/rvv/intrinsic/mask_load_store_32.c: New test.
---
.../riscv/rvv/intrinsic/mask_loa
From: zhongjuzhe
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrinsic/vlexff_2.c: New test.
---
.../gcc.target/riscv/rvv/intrinsic/vlexff_2.c | 1251 +
1 file changed, 1251 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlexff_2.c
d
From: zhongjuzhe
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrinsic/vlsex_2.c: New test.
---
.../gcc.target/riscv/rvv/intrinsic/vlsex_2.c | 1251 +
1 file changed, 1251 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_
From: zhongjuzhe
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrinsic/vsex.c: New test.
---
.../gcc.target/riscv/rvv/intrinsic/vsex.c | 4776 +
1 file changed, 4776 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsex.c
diff --gi
From: zhongjuzhe
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/vloxeix_4.C: New test.
---
.../g++.target/riscv/rvv/vloxeix_4.C | 2503 +
1 file changed, 2503 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vloxeix_4.C
diff --git a/gcc/te
From: zhongjuzhe
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/vsex.C: New test.
---
gcc/testsuite/g++.target/riscv/rvv/vsex.C | 1704 +
1 file changed, 1704 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vsex.C
diff --git a/gcc/testsuite/g+
From: zhongjuzhe
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/vluxeix_4.C: New test.
---
.../g++.target/riscv/rvv/vluxeix_4.C | 2503 +
1 file changed, 2503 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vluxeix_4.C
diff --git a/gcc/te
From: zhongjuzhe
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/vssex.C: New test.
---
gcc/testsuite/g++.target/riscv/rvv/vssex.C | 1704
1 file changed, 1704 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vssex.C
diff --git a/gcc/testsuite/
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/constraints.md (Wdm): New constraint.
* config/riscv/predicates.md (direct_broadcast_operand): New predicate.
* config/riscv/riscv-protos.h (RVV_VLMAX): New macro.
(emit_pred_op): Refine function.
* config/r
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (enum vlmul_type): New enum.
(get_vlmul): New function.
(get_ratio): Ditto.
* config/riscv/riscv-v.cc (struct mode_vtype_group): New struct.
(ENTRY): Adapt for attributes.
(enum vlmul_
From: Ju-Zhe Zhong
Since mask instruction doesn't need policy, so remove it to make it look
reasonable.
gcc/ChangeLog:
* config/riscv/vector.md: Remove TA && MA operands.
---
gcc/config/riscv/vector.md | 2 --
1 file changed, 2 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/g
From: Ju-Zhe Zhong
Sorry for resend this patch, I found I miss commit a file.
1. vector.md: remove tail && mask policy operand for mask mode operations since
we don't need them according to RVV ISA.
2. riscv-v.cc: adapt emit_pred_op for mask mode predicated mov since all RVV
modes
includin
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector.md: Fix bug of vmsbc
---
gcc/config/riscv/vector.md | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index a76e8286fe5..c100407d9fa 100644
--- a
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector.md: Fix bug of vmsbc
---
gcc/config/riscv/vector.md | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index a76e8286fe5..c100407d9fa 100644
--- a
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (eliminate_insn): Fix bugs.
(insert_vsetvl): Ditto.
(pass_vsetvl::emit_local_forward_vsetvls): Ditto.
* config/riscv/riscv-vsetvl.h (enum vsetvl_type): Ditto.
* config/riscv/vector.md: Ditto.
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Define as global.
(emit_vlmax_op): Ditto.
* config/riscv/riscv-v.cc (get_sew): New function.
(emit_vlmax_vsetvl): Adapt function.
(emit_pred_op): Ditto.
(emit_vlma
From: Ju-Zhe Zhong
This patch fix PR109228
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109228
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vlenb): Add
__riscv_vlenb support.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
From: Ju-Zhe Zhong
Current expansion of vmsge will make RA produce redundant vmv1r.v.
testcase:
void f1 (void * in, void *out, int32_t x)
{
vbool32_t mask = *(vbool32_t*)in;
asm volatile ("":::"memory");
vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
vint32m1_t v2 = __riscv_vle32_
From: Juzhe-Zhong
This patch fixes the issue of incorrect reigster order of RVV.
The new register order is coming from kito original RVV GCC implementation.
Consider this case:
void f (void *base,void *base2,void *out,size_t vl, int n)
{
vuint64m8_t bindex = __riscv_vle64_v_u64m8 (base
From: Juzhe-Zhong
Co-authored-by: kito-cheng
Co-authored-by: kito-cheng
This patch fixes the issue of incorrect reigster order of RVV.
The new register order is coming from kito original RVV GCC implementation.
Consider this case:
void f (void *base,void *base2,void *out,size_t vl, int n
From: Juzhe-Zhong
PR 108270
Fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
for (int j = 0; j < m; j++){
for (int k = 0;
From: Juzhe-Zhong
void f (int8_t* base1,int8_t* base2,int8_t* out,int n)
{
vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
for (int i = 0; i < n; i++){
v = __riscv_vor_vx_i8mf4 (v, 101, 32);
v = __riscv_vle8_v_i8mf4_tu (v, base2,
From: Juzhe-Zhong
void f (int8_t* base1,int8_t* base2,int8_t* out,int n)
{
vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
for (int i = 0; i < n; i++){
v = __riscv_vor_vx_i8mf4 (v, 101, 32);
v = __riscv_vle8_v_i8mf4_tu (v, base2,
From: Juzhe-Zhong
Co-authored-by: kito-cheng
Co-authored-by: kito-cheng
This path fix ICE of ternary intrinsic:
bug.C:144:2: error: unable to find a register to spill
144 | }
| ^
bug.C:144:2: error: this is the insn:
(insn 462 972 919 24 (set (reg/v:VNx8DI 546 [orig:192 var_10
From: Juzhe-Zhong
bug.C:144:2: error: unrecognizable insn:
144 | }
| ^
(insn 684 683 685 26 (set (reg:SI 513)
(and:SI (const_int 4 [0x4])
(const_int 1 [0x1]))) "bug.C":115:47 -1
(nil))
andi a4,a4,1 ===> sgtu a4,a4,zero
vsetlvi tuvs
From: Juzhe-Zhong
Co-authored-by: kito-cheng
Co-authored-by: kito-cheng
This path fix ICE of ternary intrinsic:
bug.C:144:2: error: unable to find a register to spill
144 | }
| ^
bug.C:144:2: error: this is the insn:
(insn 462 972 919 24 (set (reg/v:VNx8DI 546 [orig:192 var_10
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_insns): Adapt PASS.
* config/riscv/vector-iterators.md: New unspec.
* config/riscv/vector.md: Optimize fault only first load pattern.
gcc/testsuite/ChangeLog:
* gcc.target
From: Juzhe-Zhong
Currently, we only support chunk = 32 bit for zve32*
and chunk = 64 for zve64*.
According to RVV ISA chapter 18.3 V: Vector Extension for Application Processors
We should also support chunk = 128 bit for Full 'V' extension.
Also, currently, LMUL = 1 for INT64 is
From: Ju-Zhe Zhong
It's quite obvious that the order of vrsub SEW64 is wrong.
gcc/ChangeLog:
* config/riscv/vector.md: Fix incorrect operand order.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/bug-23.C: New test.
---
gcc/config/riscv/vector.md|
From: Juzhe-Zhong
This patch fix bug:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109399
PR 109399
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(pass_vsetvl::compute_local_backward_infos): Update user vsetvl in local demand
fusion.
gcc/testsuite/ChangeLog
From: Juzhe-Zhong
This patch is to add WHILE_LEN pattern.
It's inspired by RVV ISA simple "vvaddint32.s" example:
https://github.com/riscv/riscv-v-spec/blob/master/example/vvaddint32.s
More details are in "vect_set_loop_controls_by_while_len" implementation
and
From: Juzhe-Zhong
PATCH 1: Add WHILE_LEN pattern in Loop Vectorizer to support decrement IV for
RVV.
PATCH 2: Enable basic auto-vectorization for RVV in RISC-V port.
PATCH 3: Add testcases for basic RVV auto-vectorization of WHILE_LEN pattern
includeing single rgroup test and multiple
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add
compile option for RVV auto-vectorization.
(enum riscv_autovec_lmul_enum): Ditto.
* config/riscv/riscv-protos.h (get_vector_mode): Remove unused global
function
From: Juzhe-Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp: Add testing for RVV auto-vectorization.
* gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: New test.
* gcc.target/riscv
From: Juzhe-Zhong
This patch should be merged before this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614935.html
According to RVV ISA, the EEW = 64 is enable only when -march=*zve64*
Current condition is incorrect, since -march=*zve32*_zvl64b will enable EEW =
64 which
is
From: Juzhe-Zhong
The next patch to enable basic RVV auto-vectorization of
VLA auto-vectorization (RVV_SCALABLE) and fixed-length VLS auto-vectorization
(RVV_FIXED_VLMAX).
We will support RVV_FIXED_VLMIN in the future.
gcc/ChangeLog:
* config/riscv/riscv-opts.h (enum
From: Juzhe-Zhong
Enable basic auto-vectorization support of WHILE_LEN/LEN_LOAD/LEN_STORE.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode): New function.
(expand_while_len): Ditto.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto
From: Juzhe-Zhong
This patch is to enhance optimization for auto-vectorization.
Before this patch:
Loop:
vsetvl a5,a2...
vsetvl zero,a5...
vle
After this patch:
Loop:
vsetvl a5,a2
vle
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): New
function
From: Juzhe-Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp: Add auto-vectorization testing.
* gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase.
* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: New test.
* gcc.target/riscv/rvv
From: Juzhe-Zhong
This patch is to add WHILE_LEN pattern.
It's inspired by RVV ISA simple "vvaddint32.s" example:
https://github.com/riscv/riscv-v-spec/blob/master/example/vvaddint32.s
More details are in "vect_set_loop_controls_by_while_len" implementation
and
From: Juzhe-Zhong
For EEW = 64 RVV operation, we use TARGET_MIN_VLEN > 32 to predicate such
operations.
This is incorrect. Since -march=rv*zve32*_zvl64b will make TARGET_MIN_VLEN = 64
which is
not allowing EEW = 64 operations according to RVV ISA.
Instead, we should use "TARGET_VECTOR
From: Juzhe-Zhong
Since VNx1SI mode is nunits = [1,1] which will create ICE in
Loop vectorizer of GCC. We disabled it. The current condition
allows VNx4SI which LMUL = 4. We should be able to enable VNx2SI too.
This patch is to enable auto-vectorization for VNx2SImode.
gcc/ChangeLog
From: Juzhe-Zhong
According RVV ISA:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-type-register-vtype
We have LMUL: 1/8, 1/4, 1/2, 1, 2, 4, 8
Also, for segment instructions, we have tuple type for NF = 2 ~ 8.
For example, for LMUL = 1/2, SEW = 32, we have vint32mf2_t,
we
From: Ju-Zhe Zhong
Fix supporting data type according to RVV ISA.
For vint64m*_t, we should only allow them in zve64* instead of zve32*_zvl64b
(>=64b).
Ideally, we should make error message more friendly like Clang.
https://godbolt.org/z/f9GMv4dMo to report the RVV type require extenstion name.
From: Ju-Zhe Zhong
Fix supporting data type according to RVV ISA.
For vint64m*_t, we should only allow them in zve64* instead of zve32*_zvl64b
(>=64b).
Ideally, we should make error message more friendly like Clang.
https://godbolt.org/z/f9GMv4dMo to report the RVV type require extenstion name.
From: Juzhe-Zhong
Since multiple conflicts with previous patch.
Rebase to the trunk and resend it.
gcc/ChangeLog:
* config/riscv/riscv-modes.def (FLOAT_MODE): Add chunk 128 modes.
(VECTOR_BOOL_MODE): Ditto.
(ADJUST_NUNITS): Ditto.
(ADJUST_ALIGNMENT): Ditto
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-modes.def (FLOAT_MODE): Add chunk 128 support.
(VECTOR_BOOL_MODE): Ditto.
(ADJUST_NUNITS): Ditto.
(ADJUST_ALIGNMENT): Ditto.
(ADJUST_BYTESIZE): Ditto.
(ADJUST_PRECISION): Ditto
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function.
(pass_vsetvl::cleanup_insns): Fix bug.
---
gcc/config/riscv/riscv-vsetvl.cc | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/gcc/config/r
1001 - 1100 of 1101 matches
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