From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vaadd_vv-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C: New test.
---
.../g++.target/riscv/rvv/base/vaadd_vv-1.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vaadd_vv-2.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vaadd_vv-3.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vaadd_vv_mu-1.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vaadd_vv_mu-2.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vaadd_vv_mu-3.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vaadd_vv_tu-1.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vaadd_vv_tu-2.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vaadd_vv_tu-3.C | 160 +++++++++
.../riscv/rvv/base/vaadd_vv_tum-1.C | 160 +++++++++
.../riscv/rvv/base/vaadd_vv_tum-2.C | 160 +++++++++
.../riscv/rvv/base/vaadd_vv_tum-3.C | 160 +++++++++
.../riscv/rvv/base/vaadd_vv_tumu-1.C | 160 +++++++++
.../riscv/rvv/base/vaadd_vv_tumu-2.C | 160 +++++++++
.../riscv/rvv/base/vaadd_vv_tumu-3.C | 160 +++++++++
15 files changed, 2862 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C
new file mode 100644
index 00000000000..c75b9398e6b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vaadd(vbool64_t mask,vint8mf8_t op1,vint8mf8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vbool32_t mask,vint8mf4_t op1,vint8mf4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vbool16_t mask,vint8mf2_t op1,vint8mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vbool64_t mask,vint16mf4_t op1,vint16mf4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vbool32_t mask,vint16mf2_t op1,vint16mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd(vbool16_t mask,vint16m1_t op1,vint16m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd(vbool8_t mask,vint16m2_t op1,vint16m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd(vbool4_t mask,vint16m4_t op1,vint16m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd(vbool2_t mask,vint16m8_t op1,vint16m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vbool64_t mask,vint32mf2_t op1,vint32mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd(vbool32_t mask,vint32m1_t op1,vint32m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd(vbool16_t mask,vint32m2_t op1,vint32m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd(vbool8_t mask,vint32m4_t op1,vint32m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd(vbool4_t mask,vint32m8_t op1,vint32m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd(vbool64_t mask,vint64m1_t op1,vint64m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd(vbool32_t mask,vint64m2_t op1,vint64m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd(vbool16_t mask,vint64m4_t op1,vint64m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd(vbool8_t mask,vint64m8_t op1,vint64m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-2.C
new file mode 100644
index 00000000000..e78f7c1daa6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vaadd(vbool64_t mask,vint8mf8_t op1,vint8mf8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vbool32_t mask,vint8mf4_t op1,vint8mf4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vbool16_t mask,vint8mf2_t op1,vint8mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vbool64_t mask,vint16mf4_t op1,vint16mf4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vbool32_t mask,vint16mf2_t op1,vint16mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd(vbool16_t mask,vint16m1_t op1,vint16m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd(vbool8_t mask,vint16m2_t op1,vint16m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd(vbool4_t mask,vint16m4_t op1,vint16m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd(vbool2_t mask,vint16m8_t op1,vint16m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vbool64_t mask,vint32mf2_t op1,vint32mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd(vbool32_t mask,vint32m1_t op1,vint32m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd(vbool16_t mask,vint32m2_t op1,vint32m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd(vbool8_t mask,vint32m4_t op1,vint32m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd(vbool4_t mask,vint32m8_t op1,vint32m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd(vbool64_t mask,vint64m1_t op1,vint64m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd(vbool32_t mask,vint64m2_t op1,vint64m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd(vbool16_t mask,vint64m4_t op1,vint64m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd(vbool8_t mask,vint64m8_t op1,vint64m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-3.C
new file mode 100644
index 00000000000..6b83c1f028a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vaadd(vbool64_t mask,vint8mf8_t op1,vint8mf8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vbool32_t mask,vint8mf4_t op1,vint8mf4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vbool16_t mask,vint8mf2_t op1,vint8mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t
vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vbool64_t mask,vint16mf4_t op1,vint16mf4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vbool32_t mask,vint16mf2_t op1,vint16mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd(vbool16_t mask,vint16m1_t op1,vint16m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd(vbool8_t mask,vint16m2_t op1,vint16m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd(vbool4_t mask,vint16m4_t op1,vint16m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd(vbool2_t mask,vint16m8_t op1,vint16m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vbool64_t mask,vint32mf2_t op1,vint32mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd(vbool32_t mask,vint32m1_t op1,vint32m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd(vbool16_t mask,vint32m2_t op1,vint32m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd(vbool8_t mask,vint32m4_t op1,vint32m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd(vbool4_t mask,vint32m8_t op1,vint32m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd(vbool64_t mask,vint64m1_t op1,vint64m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd(vbool32_t mask,vint64m2_t op1,vint64m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd(vbool16_t mask,vint64m4_t op1,vint64m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd(vbool8_t mask,vint64m8_t op1,vint64m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-1.C
new file mode 100644
index 00000000000..9c010d8952a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t
op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t
op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t
op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-2.C
new file mode 100644
index 00000000000..bd26d023fb0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t
op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t
op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t
op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-3.C
new file mode 100644
index 00000000000..6e940305349
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t
op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t
op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t
op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-1.C
new file mode 100644
index 00000000000..139489edbb3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tu(vint16mf4_t merge,vint16mf4_t
op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tu(vint16mf2_t merge,vint16mf2_t
op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tu(vint32mf2_t merge,vint32mf2_t
op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-2.C
new file mode 100644
index 00000000000..8a35625fcad
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tu(vint16mf4_t merge,vint16mf4_t
op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tu(vint16mf2_t merge,vint16mf2_t
op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tu(vint32mf2_t merge,vint32mf2_t
op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-3.C
new file mode 100644
index 00000000000..aab36ce2bfc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tu(vint16mf4_t merge,vint16mf4_t
op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tu(vint16mf2_t merge,vint16mf2_t
op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tu(vint32mf2_t merge,vint32mf2_t
op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t
op2,size_t vl)
+{
+ return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-1.C
new file mode 100644
index 00000000000..e7aa8505c42
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tum(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tum(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tum(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-2.C
new file mode 100644
index 00000000000..146e552e4db
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tum(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tum(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tum(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-3.C
new file mode 100644
index 00000000000..0b9b02052a6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tum(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tum(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tum(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C
new file mode 100644
index 00000000000..1805fbe3605
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tumu(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tumu(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tumu(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C
new file mode 100644
index 00000000000..4bdac037d26
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tumu(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tumu(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tumu(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C
new file mode 100644
index 00000000000..0f6709e0ff4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t
op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t
op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t
op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t
op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t
op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t
op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t
op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tumu(vbool64_t mask,vint16mf4_t
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tumu(vbool32_t mask,vint16mf2_t
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t
op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t
op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t
op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t
op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tumu(vbool64_t mask,vint32mf2_t
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t
op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t
op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t
op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t
op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t
op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t
op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t
op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t
op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
--
2.36.3
