---
2015-07-03 James Greenhalgh
* doc/invoke.texi (moverride): Move to correct section.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 844d7edaecf2bc6642324ad8513f7c2add0ee486..1dfce1143027cef86d8fbf59580035e6d25f1189 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
On Mon, Jul 06, 2015 at 09:20:39AM +0100, Szabolcs Nagy wrote:
> fnmul was modeled as (-a)*b instead of -(a*b), which is wrong with
> -frounding-math, so the correct pattern is added too and the other
> one is only used if !flag_rounding_math.
>
> This affects a glibc math test, similar fix will b
On Tue, Jul 07, 2015 at 01:52:29PM +0100, Jiong Wang wrote:
>
> A second patch to improve rtl loop iv on AArch64.
>
> We should define this to tell gcc the pattern hidden by these GOT unspec
> is safe from trap, so gcc could make more positive decision when
> handling them, for example in RTL loo
trunk?
Thanks,
James
---
2015-01-15 James Greenhalgh
* config/arm/cortex-a57.md: New.
* config/aarch64/aarch64.md: Include it.
* config/aarch64/aarch64-cores.def (cortex-a57): Tune for it.
* config/aarch64/aarch64-tune.md: Regenerate.
diff --git a/gcc/config/
On Fri, Jan 16, 2015 at 10:20:40AM +, Marcus Shawcroft wrote:
> On 15 January 2015 at 09:50, James Greenhalgh
> wrote:
>
> > 2015-01-15 James Greenhalgh
> >
> > * config/arm/cortex-a57.md: New.
> > * config/aarch64/aarch64.md: Include
see if this fixes his bug!
Cheers,
James
---
gcc/testsuite/
2015-01-16 James Greenhalgh
* g++.dg/abi/mangle-abi-crypto.C: Add crypto options, rather
than Neon options.
diff --git a/gcc/testsuite/g++.dg/abi/mangle-arm-crypto.C b/gcc/testsuite/g++.dg/abi/mangle-arm-crypto.C
inde
On Mon, Jan 12, 2015 at 05:30:46PM +, Andrew Pinski wrote:
> On Mon, Jan 12, 2015 at 7:52 AM, Kyrill Tkachov
> wrote:
> > Hi all,
> >
> > As raised in https://gcc.gnu.org/ml/gcc-patches/2014-12/msg01237.html and
> > discussed in that thread, using __builtin_sqrt for vsqrt_f64 may end up in a
On Fri, Jan 16, 2015 at 11:14:42AM +, Ramana Radhakrishnan wrote:
>
>
> On 16/01/15 10:20, Marcus Shawcroft wrote:
> > On 15 January 2015 at 09:50, James Greenhalgh
> > wrote:
> >
> >> 2015-01-15 James Greenhalgh
> >>
> >> *
On Fri, Jan 16, 2015 at 03:34:30PM +, Ramana Radhakrishnan wrote:
> On Fri, Jan 16, 2015 at 3:06 PM, James Greenhalgh
> wrote:
> > On Fri, Jan 16, 2015 at 10:20:40AM +, Marcus Shawcroft wrote:
> >> On 15 January 2015 at 09:50, James Greenhalgh
> >> wrote:
On Mon, Jan 19, 2015 at 08:57:31PM +, Gerald Pfeifer wrote:
> On Monday 2015-01-19 17:52, James Greenhalgh wrote:
> > OK after the Cortex-A57 scheduling description goes in to the ARM port?
>
> Yes, thanks, except that once will be sufficient. ;-) (The current
> patch feat
On Wed, Jan 21, 2015 at 05:39:12PM +, Alex Velenko wrote:
> Hi,
> Is the following patch ok?
> regards,
> Alex
Hi Alex,
Some comments on your submission inline below.
> This patch fixes aarch64/atomic-op-consume.c test to expect safe assembly to
> be
> generated when __ATOMIC_CONSUME semant
*Ping*
Cheers,
James
On Mon, Jan 19, 2015 at 05:44:27PM +, James Greenhalgh wrote:
>
> On Fri, Jan 16, 2015 at 11:14:42AM +, Ramana Radhakrishnan wrote:
> >
> >
> > On 16/01/15 10:20, Marcus Shawcroft wrote:
> > > On 15 January 2015 at 09:5
ug, impacting
a corner case of Neon intrinsics, I think it is low risk.
With that in mind, OK for trunk?
Thanks,
James
---
gcc/
2015-01-28 James Greenhalgh
* config/aarch64/aarch64-simd.md (aarch64_abs): New.
* config/aarch64/aarch64-simd-builtins.def (abs): Split by
On Wed, Jan 28, 2015 at 12:32:45PM +, Alan Lawrence wrote:
> Ok for stage 4?
This is a regression from 4.9, so once we iron out some nits, it should
be.
> gcc/ChangeLog:
>
> * config/aarch64/aarch64.md (*xor_one_cmpl3): Use FP_REGNUM_P
> as split condition.
And a testcase, pleas
On Wed, Jan 28, 2015 at 05:51:27PM +, Marcus Shawcroft wrote:
> On 28 January 2015 at 17:41, Mike Stump wrote:
> > On Jan 27, 2015, at 8:24 AM, Alex Velenko wrote:
> >> This patch fixes aarch64/atomic-op-consume.c test to expect safe "LDAXR"
> >> instruction to be generated when __ATOMIC_CONS
-none-linux-gnu with no issues.
I can't see anyone objecting to this and would normally commit it
as obvious, but as we are in Stage 4, I'll ask for permission.
So OK for trunk/Stage 1?
Thanks,
James
---
2015-02-04 James Greenhalgh
* config/aarch64/aarch64.c (NAMED_PARAM):
On Wed, Feb 04, 2015 at 12:18:29PM +, Kyrill Tkachov wrote:
> Hi all,
>
> This patch makes use of std::swap in every peephole2 of
> aarch64-ldp-stp.md instead of manually swapping rtxen.
> No functional change, just a cleanup.
> Bootstrapped and tested on aarch64.
>
> I'm proposing this for
On Wed, Feb 04, 2015 at 01:23:06PM +, Ramana Radhakrishnan wrote:
> On Wed, Feb 4, 2015 at 10:36 AM, Matthew Wahab wrote:
> > Hello,
> >
> > The Cortex-A72 is an ARMv8 core with the same architectural features as the
> > Cortex-A57. This patch adds support for the command line option
> > -mcpu
On Wed, Feb 04, 2015 at 12:57:11PM +, Marcus Shawcroft wrote:
> On 4 February 2015 at 10:35, Matthew Wahab wrote:
> > Hello,
> >
> > The Cortex-A72 is an ARMv8 core with the same architectural features as the
> > Cortex-A57. This patch adds support for the command line option
> > -mcpu=cortex-
tor. Now the test passes on aarch64. I also
tried hacking out the vector comparison folding code and confirmed that
this caused the test to start failing, so it still works.
I've committed this under the obvious rule as revision 220440.
Cheers,
James
---
2014-02-05 James Greenhalgh
element of the vector.
The test now passes on AArch64. I also hacked out the vector comparison
folding code and confirmed that this test started failing.
I've committed this under the obvious rule as revision 220440.
Cheers,
James
---
2014-02-05 James Greenhalgh
* gcc.dg/tree-ss
On Fri, Feb 06, 2015 at 09:44:20AM +, Tobias Burnus wrote:
> I think it is useful to know that one can build libcc1.so - also as
> advertisement. Thus, I propose to include something like the quip in
> the attachment.
>
> GDB uses it in version 7.9, which is not yet released but already
> bran
GROUP_P set.
Thanks,
James
---
2015-02-06 James Greenhalgh
* haifa-sched.c (recompute_todo_spec): After applying a
replacement and cancelling a dependency, also clear the
SCHED_GROUP_P flag.
diff --git a/gcc/haifa-sched.c b/gcc/haifa-sched.c
index 75d2421..730a8db 100
On Wed, Jan 28, 2015 at 02:04:04PM +, James Greenhalgh wrote:
> On Wed, Jan 28, 2015 at 12:32:45PM +, Alan Lawrence wrote:
> > Ok for stage 4?
>
> This is a regression from 4.9, so once we iron out some nits, it should
> be.
>
> > gcc/ChangeLog:
> >
&g
James
---
2015-02-10 James Greenhalgh
* gfortran.dg/pr45636.f90: XFAIL for aarch64* targets.
diff --git a/gcc/testsuite/gfortran.dg/pr45636.f90 b/gcc/testsuite/gfortran.dg/pr45636.f90
index c80dda4..e3d8ca6 100644
--- a/gcc/testsuite/gfortran.dg/pr45636.f90
+++ b/gcc/testsuite/gfortr
On Mon, Feb 09, 2015 at 11:16:56PM +, Jeff Law wrote:
> On 02/06/15 05:24, James Greenhalgh wrote:
> >
> > ---
> > 2015-02-06 James Greenhalgh
> >
> > * haifa-sched.c (recompute_todo_spec): After applying a
> > replacement and
On Wed, Feb 11, 2015 at 10:15:42AM +, Marcus Shawcroft wrote:
> On 10 February 2015 at 16:06, James Greenhalgh
> wrote:
> >
> > Hi,
> >
> > As is already done for mips and hppa, we should XFAIL this test on
> > AArch64 as we don't currently use the s
ssues, and had a look in
firefox to ensure the changes were sane.
I've applied this patch under the obvious rule as revision r220738.
Thanks,
James
---
2015-02-16 James Greenhalgh
* doc/install.texi (Specific): Reorder targets list to put
aarch64 in alphabetical order.
with the testcase added, but I appreciate your argument
that the testcase is more than a wee bit fragile. In which case, this
is OK as is, but you'll need Marcus or Richard to approve it.
Cheers,
James
> James Greenhalgh wrote:
> > On Wed, Jan 28, 2015 at 02:04:04PM +, James Greenhal
-none-linux-gnu.
Marcus, Richard, do you want this churn now or in Stage 1?
Cheers,
James
---
2015-02-17 James Greenhalgh
* config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Use
emit_set_insn to emit simple sets.
(aarch64_expand_mov_immed
p from the maintainers of those ports
where it can be given.
The target-independent patches I've bootstrapped and tested on
x86_64/ARM/AArch64 with no issues.
OK for trunk?
Thanks,
James
---
James Greenhalgh (6):
[Patch 1/6] Hookize MOVE_BY_PIECES_P, remove most uses of MOVE_RATIO
[Patch 2/6
OK?
Thanks,
James
---
gcc/
2014-10-28 James Greenhalgh
* target.def (move_by_pieces_profitable_p): New.
* doc/tm.texi.in (MOVE_BY_PIECES_P): Reduce documentation to a stub
describing that this macro is deprecated.
(TARGET_MOVE_BY_PIECES_PROFITABLE_P): Add hook
-10-29 James Greenhalgh
* config/s390/s390.c (s390_move_by_pieces_profitable_p): New.
(TARGET_MOVE_BY_PIECES_PROFITABLE_P): Likewise.
* config/s390/s390.h (MOVE_BY_PIECES_P): Remove.
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 1b10805..f531e12
untested.
If one of the arc maintainers could give it a spin that would be
helpful.
OK?
Thanks,
James
---
2014-10-28 James Greenhalgh
* config/arc/arc.c (TARGET_MOVE_BY_PIECES_PROFITABLE_P): New.
(arc_move_by_pieces_profitable_p): Likewise.
* confir/arc/arc.h
/
2014-10-28 James Greenhalgh
* config/sh/sh.c (TARGET_MOVE_BY_PIECES_PROFITABLE_P): New.
(sh_move_by_pieces_profitable_p): Likewise.
* config/sh/sh.h (MOVE_BY_PIECES_P): Remove.
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 1662b55..0b907b9 100644
--- a/gcc
-
gcc/
2014-10-28 James Greenhalgh
* config/mips/mips.h (MOVE_BY_PIECES_P): Remove.
* config/mips/mips.c (TARGET_MOVE_BY_PIECES_PROFITABLE_P): New.
(mips_move_by_pieces_p): Rename to...
(mips_move_by_pieces_profitable_p): ...this, use new hook
parameters
Hi,
This final patch gets rid of MOVE_BY_PIECES_P.
Bootstrapped on x86_64, ARM and AArch64.
Thanks,
James
---
gcc/
2014-10-28 James Greenhalgh
* doc/tm.texi.in (MOVE_BY_PIECES_P): Remove.
* doc/tm.texi: Regenerate.
* system.h: Poison MOVE_BY_PIECES_P
On Wed, Oct 01, 2014 at 05:38:12PM +0100, James Greenhalgh wrote:
> On Fri, Sep 26, 2014 at 10:11:13AM +0100, Richard Biener wrote:
> > On Thu, Sep 25, 2014 at 4:57 PM, James Greenhalgh
> > wrote:
> > Given the special value to note the default for the new --params is
&
On Wed, Oct 29, 2014 at 11:42:06AM +, Matthew Fortune wrote:
> Hi James,
>
> I think you have a bug in the following hunk where you pass
> STORE_MAX_PIECES in place of the optimise for speed flag. I guess you
> would need an extra argument to pass a different *_MAX_PIECES value
> in.
Yup, goo
Hi,
This patch prepares for removing all the *BY_PIECES_P macros by
introducing a new target hook TARGET_USE_BY_PIECES_INFRASTRUCTURE_P.
Tested on ARM/AArch64/x86_64 with no issues.
Ok for trunk?
Thanks,
James
---
gcc/
2014-10-31 James Greenhalgh
* target.def
On Wed, Oct 29, 2014 at 03:31:54PM +, James Greenhalgh wrote:
> On Wed, Oct 29, 2014 at 11:42:06AM +, Matthew Fortune wrote:
> > Hi James,
> >
> > I think you have a bug in the following hunk where you pass
> > STORE_MAX_PIECES in place of the optimise
this patch. If one of the s390
maintainers wants to pick it up and test it, that would be much
appreciated.
Ok?
James
---
2014-10-31 James Greenhalgh
* config/s390/s390.c (s390_use_by_pieces_infrastructure_p): New.
(TARGET_USE_BY_PIECES_INFRASTRUCTURE_P): Likewise.
* c
otherwise,
I have no reasonable way to test this patch. If one of the sh
maintainers wants to pick it up and test it, that would be much
appreciated.
Thanks,
James
---
gcc/
2014-10-31 James Greenhalgh
* config/sh/sh.c (TARGET_USE_BY_PIECES_INFRASTRUCTURE_P): New
operations.
I tried building a compiler but no amount of fiddling with target
strings got me to a sensible result, so this patch is completely
untested.
If one of the arc maintainers could give it a spin that would be
helpful.
OK?
Thanks,
James
---
2014-10-31 James Greenhalgh
* config
bootstrap run
with no issues.
OK?
Cheers,
James
---
gcc/
2014-10-31 James Greenhalgh
* config/aarch64/aarch64.c
(aarch64_use_by_pieces_infrastructre_p): New.
(TARGET_USE_BY_PIECES_INFRASTRUCTURE): Likewise.
* config/aarch64/aarch64.h (STORE_BY_PIECES_P
piler and there were no fires, I don't have access
to any MIPS hardware, so if one of the MIPS maintainers wanted to pick
this up and test it, that would be very much appreciated.
OK?
Thanks,
James
---
gcc/
2014-10-31 James Greenhalgh
* config/mips/mips.h (MOVE_BY_PIECES_
Hi,
This final patch gets rid of all the *_BY_PIECES_P macros.
Bootstrapped on x86_64, ARM and AArch64.
Thanks,
James
---
gcc/
2014-10-31 James Greenhalgh
* doc/tm.texi.in (MOVE_BY_PIECES_P): Remove.
(CLEAR_BY_PIECES_P): Likewise.
(SET_BY_PIECES_P): Likewise
On Tue, Nov 04, 2014 at 12:07:56PM +, Joern Rennecke wrote:
> On 31 October 2014 15:10, James Greenhalgh wrote:
>
> > While I am there, arc defines a macro CAN_MOVE_BY_PIECES, which is
> > unused, so clean that up too.
>
> That's not a clean-up. This pertain
On Wed, Nov 05, 2014 at 09:50:52PM +, Marc Glisse wrote:
> On Wed, 5 Nov 2014, Tejas Belagod wrote:
>
> >>> 2014-10-01 Tejas Belagod
> >>>
> >>> * config/aarch64/aarch64-builtins.c
> >>> (aarch64_build_scalar_type): Remove.
> >>> (aarch64_scalar_builtin_types, aar
On Fri, Oct 31, 2014 at 10:46:12AM +, Richard Biener wrote:
> On Wed, Oct 29, 2014 at 3:39 PM, James Greenhalgh wrote:
> >> I suppose I could port any target with a definition of MOVE_RATIO to
> >> override the default parameter value in their option overriding code,
>
to pick it up.
This patch fixes both of these issues and adds testcases to ensure we are
picking up the combine opportunity.
I've bootstrapped and tested this on aarch64-none-linux-gnu and
cross-tested it for aarch64-none-elf.
OK?
Cheers,
James
---
gcc/
2014-11-11 James Greenhalgh
Hi,
I was taking a look at fixing the issues in the ARM back-end exposed
by Marc Glisse's patch in [1], and hoped to fix them by adapting the
patch recently commited by Tejas ([2]).
As I looked, I realised that the ARM target and the AArch64 target
now differ drastically in how their Advanced SIM
8 of the series.
Bootstrapped on arm-none-gnueabihf with no issues.
OK?
Thanks,
James
---
gcc/
2014-11-12 James Greenhalgh
* gcc/config/arm/arm-builtins.c (arm_type_qualifiers): New.
(neon_itype): Add new types corresponding to the types used in
q
isolation with no
issues.
OK?
Thanks,
James
---
2014-11-12 James Greenhalgh
* config/arm/t-arm (arm.o): Include arm-protos.h in the recipe.
* config/arm/arm.c (FL_CO_PROC): Move to arm-protos.h.
(FL_ARCH3M): Likewise.
(FL_MODE26): Likewise.
(FL_MODE32)
Hi,
These macros can always be defined as a base case of VAR1 and a "recursive"
case of VAR. At the moment, the body of VAR1 is duplicated to each
macro.
This patch makes that change.
Regression tested on arm-none-linux-gnueabihf with no issues.
OK?
Thanks,
James
---
gcc/
2014-11
eries,
and bootstrapped on arm-none-linux-gnueabihf for good luck.
OK?
Thanks,
James
---
gcc/testsuite/
2014-11-12 James Greenhalgh
* g++.dg/abi/mangle-arm-crypto.C: New.
* g++.dg/abi/mangle-neon.C (f19): New.
(f20): Likewise.
diff --git a/gcc/testsuite/g++.dg/abi/
abihf with no issues.
OK?
Thanks,
James
---
gcc/
2014-11-12 James Greenhalgh
* config/arm/arm-builtins.c (arm_scalar_builtin_types): New.
(enum arm_simd_type): Likewise.
(struct arm_simd_type_info): Likewise
(arm_mangle_builtin_scalar_type)
back-ends (and after that the builtin
definitions, and some of arm_neon.h, etc.), but I haven't done that here
as the immediate benefit is minimal.
Bootstrapped and regression tested with no issues.
OK?
Thanks,
James
---
gcc/
2014-11-12 James Greenhalgh
* config/arm/arm-built
On Thu, May 30, 2019 at 03:25:19PM +0100, Sylvia Taylor wrote:
> Greetings,
>
> This patch adds support to combine:
>
> 1) ushr and add into usra, example:
>
> ushr v0.16b, v0.16b, 2
> add v0.16b, v0.16b, v2.16b
> ---
> usra v2.16b, v0.16b, 2
>
> 2) sshr and add into ssra, example:
>
> ssh
On Fri, May 10, 2019 at 10:32:22AM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch fixes the failing gcc.dg/vect/slp-reduc-sad-2.c testcase on
> aarch64
> by implementing a vec_init optab that can handle two half-width vectors
> producing a full-width one
> by concatenating them.
>
> In t
On Thu, May 23, 2019 at 04:54:30AM +0100, Andrew Pinski wrote:
> aarch64_asan_shadow_offset is using the wrong
> offset for ILP32. Change it to be a decent one.
>
> OK? Bootstrapped and tested on aarch64-linux-gnu
> with no regressions,
OK.
Thanks,
James
>
> Thanks,
> Andrew Pinski
>
> Chan
On Mon, May 13, 2019 at 12:18:25PM +0100, Kyrill Tkachov wrote:
> Hi Richard,
>
> On 5/9/19 9:06 AM, Richard Sandiford wrote:
> > Kyrill Tkachov writes:
> >> +;; Helper expander for aarch64_abd_3 to save the callers
> >> +;; the hassle of constructing the other arm of the MINUS.
> >> +(define_exp
On Wed, May 29, 2019 at 11:00:46AM +0100, Richard Sandiford wrote:
> Szabolcs Nagy writes:
> > v2:
> > - use aarch64_simd_decl_p to check for aarch64_vector_pcs.
> > - emit the .variant_pcs directive even for local functions.
> > - don't require .variant_pcs asm support in compile only tests.
> >
On Wed, May 29, 2019 at 03:48:29PM +0100, Srinath Parvathaneni wrote:
> Hi All,
>
> This patch implements the __yield(), __wfe(), __wfi(), __sev() and
> __sevl() ACLE (hint) intrinsics for AArch64 as yield, wfe, wfi, sev and
> sevl (hint) instructions respectively.
>
> The instructions are docu
On Tue, Jun 04, 2019 at 03:58:07PM +0100, Szabolcs Nagy wrote:
> Commit r271869 broke visibility declarations in asm for extern symbols,
> because
> the new ASM_OUTPUT_EXTERNAL hook failed to call the default hook for elf.
OK.
In future, you can consider a patch like this to fall under the "obvi
On Thu, Nov 29, 2018 at 10:56:46AM -0600, Sudakshina Das wrote:
> Hi
>
> On 02/11/18 18:37, Sudakshina Das wrote:
> > Hi
> >
> > This patch is part of a series that enables ARMv8.5-A in GCC and
> > adds Branch Target Identification Mechanism.
> > (https://developer.arm.com/products/architecture/c
On Wed, Dec 12, 2018 at 09:42:05AM -0600, Olivier Hainque wrote:
> Ping for one of the changes last proposed here:
>
> https://gcc.gnu.org/ml/gcc-patches/2018-11/msg00761.html
>
> Submitted separately as an attempt to facilitate the review
> process.
>
> This one proposes the possibility for ta
On Fri, Dec 14, 2018 at 10:09:03AM -0600, Sudakshina Das wrote:
> I have updated the patch according to our discussions offline.
> The md pattern is now split into 4 patterns and i have added a new
> test for the setjmp case along with some comments where missing.
This is OK for trunk.
Thanks,
On Thu, Dec 20, 2018 at 10:38:42AM -0600, Sam Tebbs wrote:
> On 11/22/18 4:54 PM, Sam Tebbs wrote:
>
> Hi all,
>
> Attached is an updated patch with branch_protec_type renamed to
> branch_protect_type, some unneeded ATTRIBUTE_USED removed and an added
> use of ARRAY_SIZE.
>
> Below is the u
On Fri, Dec 21, 2018 at 09:00:10AM -0600, Sam Tebbs wrote:
> On 11/9/18 11:04 AM, Sam Tebbs wrote:
> Attached is an improved patch with "hint" removed from the test scans,
> pauth_hint_num_a and pauth_hint_num_b merged into pauth_hint_num and the
> "gcc_assert (cfun->machine->frame.laid_out)"
On Wed, Aug 07, 2019 at 08:23:48PM +0100, Richard Sandiford wrote:
> The Advanced SIMD and SVE permute patterns both split the permute
> operation into a base name and a hilo suffix. That works well, but it
> means that for "@" patterns, we need to pass the permute code twice,
> once for the base
On Wed, Aug 07, 2019 at 07:24:18PM +0100, Richard Sandiford wrote:
> aarch64_classify_vector_mode used properties of a mode to test whether
> the mode was a single Advanced SIMD vector, a single SVE vector, or a
> tuple of SVE vectors. That works well for current trunk and is simpler
> than checki
On Wed, Aug 07, 2019 at 07:19:12PM +0100, Richard Sandiford wrote:
> Some indexed SVE FCMLA operations have a 3-bit register field that
> requires one of Z0-Z7. This patch adds a public "y" constraint for that.
>
> The patch also documents "x", which is again intended to be a public
> constraint.
On Tue, May 28, 2019 at 06:11:29PM +0100, Wilco Dijkstra wrote:
> PR81800 is about the lrint inline giving spurious FE_INEXACT exceptions.
> The previous change for PR81800 didn't fix this: when lrint is disabled
> in the backend, the midend will simply use llrint. This actually makes
> things wor
On Tue, Jul 30, 2019 at 05:59:15PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> The neoversen1 tuning struct gives better performance on the Cortex-A76,
> so use that.
> The only difference from the current tuning is the function and label
> alignment settings.
>
> This gives about 1.3% improveme
On Fri, May 31, 2019 at 12:52:32PM +0100, Wilco Dijkstra wrote:
> With -mcpu=generic the function alignment is currently 8, however almost all
> supported cores prefer 16 or higher, so increase the default to 16:12.
> This gives ~0.2% performance increase on SPECINT2017, while codesize is 0.12%
> l
On Thu, Aug 15, 2019 at 12:28:27PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> On 8/6/19 10:51 AM, Richard Earnshaw (lists) wrote:
> On 18/07/2019 18:18, James Greenhalgh wrote:
> > On Mon, Jun 10, 2019 at 06:21:05PM +0100, Sylvia Taylor wrote:
> >> Greetings,
&g
On Mon, Jul 08, 2019 at 04:41:06PM +0100, Joel Hutton wrote:
> On 01/07/2019 18:03, James Greenhalgh wrote:
>
> >> gcc/testsuite/ChangeLog:
> >>
> >> 2019-06-12 Joel Hutton
> >>
> >> * gcc.target/aarch64/fmul_scvtf_1.c: New test.
On Thu, Aug 15, 2019 at 02:11:25PM +0100, Prathamesh Kulkarni wrote:
> On Thu, 8 Aug 2019 at 11:22, Prathamesh Kulkarni
> wrote:
> >
> > On Thu, 1 Aug 2019 at 15:34, Prathamesh Kulkarni
> > wrote:
> > >
> > > On Thu, 25 Jul 2019 at 11:56, Prathamesh Kulkarni
> > > wrote:
> > > >
> > > > On Wed,
On Wed, Aug 07, 2019 at 07:12:19PM +0100, Richard Sandiford wrote:
> The AArch64 port uses define_splits to prefer moving certain float
> constants via integer registers over loading them from memory. E.g.:
>
> (set (reg:SF X) (const_double:SF C))
>
> splits to:
>
> (set (reg:SI tmp) (c
On Mon, Oct 24, 2016 at 03:27:10PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> When storing a 64-bit immediate that has equal bottom and top halves we
> currently
> synthesize the repeating 32-bit pattern twice and perform a single X-store.
> With this patch we synthesize the 32-bit pattern once i
On Mon, Sep 02, 2019 at 01:16:32PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch implements the __jcvt ACLE intrinsic [1] that maps down to
> the FJCVTZS [2] instruction from Armv8.3-a.
> No fancy mode iterators or nothing. Just a single builtin, UNSPEC and
> define_insn and the associat
On Fri, Aug 23, 2019 at 05:42:30PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> This patch adds feature strings for some of the extensions. This string
> is what is read from /proc/cpuinfo on Linux systems
> and used during -march=native detection.
>
> The strings are taken from the kernel source
On Thu, Aug 22, 2019 at 12:03:33PM +0100, Kyrill Tkachov wrote:
> Hi Dennis,
>
> On 8/21/19 10:27 AM, Dennis Zhang wrote:
> > Hi all,
> >
> > This patch adds '-mcpu' options for following CPUs:
> > Cortex-A77, Cortex-A76AE, Cortex-A65, Cortex-A65AE, and Cortex-A34.
> >
> > Related specifications a
On Mon, Oct 08, 2018 at 05:34:52AM -0500, Martin Liška wrote:
> Hi.
>
> I'm attaching updated version of the patch.
Can't say I'm thrilled by the allocation/free (aarch64_parse_extension
allocates, everyone else has to free) responsibilities here.
If you can clean that up I'd be much happier. Th
On Tue, Oct 30, 2018 at 05:12:58AM -0500, Sameera Deshpande wrote:
> On Fri, 26 Oct 2018 at 13:33, Sameera Deshpande
> wrote:
> >
> > Hi!
> >
> > Please find attached the patch to add a pipeline description for the
> > Qualcomm Saphira core. It is tested with a bootstrap and make check,
> > with
On Thu, Oct 25, 2018 at 05:53:22AM -0500, Martin Liška wrote:
> On 10/24/18 7:48 PM, Martin Sebor wrote:
> > On 10/24/2018 03:52 AM, Martin Liška wrote:
> >> On 10/23/18 6:31 PM, Martin Sebor wrote:
> >>> On 10/22/2018 07:05 AM, Martin Liška wrote:
> >>&
On Tue, Oct 02, 2018 at 11:19:05AM -0500, Richard Henderson wrote:
> The cas insn is a single insn, and if expanded properly need not
> be split after reload. Use the proper inputs for the insn.
OK.
Thanks,
James
>
> * config/aarch64/aarch64.c (aarch64_expand_compare_and_swap):
> F
On Tue, Oct 02, 2018 at 11:19:06AM -0500, Richard Henderson wrote:
> Do not zero-extend the input to the cas for subword operations;
> instead, use the appropriate zero-extending compare insns.
> Correct the predicates and constraints for immediate expected operand.
OK, modulo two very dull style
On Tue, Oct 02, 2018 at 11:19:07AM -0500, Richard Henderson wrote:
> Allow zero as an input; fix constraints; avoid unnecessary split.
OK.
James
>
> * config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove.
> (aarch64_gen_atomic_ldop): Don't call it.
> * config/aarch64/at
On Tue, Oct 02, 2018 at 11:19:08AM -0500, Richard Henderson wrote:
> Fix constraints; avoid unnecessary split. Drop the use of the atomic_op
> iterator in favor of the ATOMIC_LDOP iterator; this is simplier and more
> logical for ldclr aka bic.
OK.
Thanks,
James
>
> * config/aarch64/aarc
On Tue, Oct 02, 2018 at 11:19:09AM -0500, Richard Henderson wrote:
> When the result of an operation is not used, we can ignore the
> result by storing to XZR. For two of the memory models, using
> XZR with LD has a preferred assembler alias, ST.
ST has different semantics to LD, in particular, S
This one needs some other reviewers copied in, who may have missed that
it is not an AARch64 only patch (it looks fine to me).
James
On Tue, Oct 02, 2018 at 11:19:10AM -0500, Richard Henderson wrote:
> * optabs-libfuncs.c (build_libfunc_function_visibility):
> New, split out from...
>
On Tue, Oct 02, 2018 at 11:19:13AM -0500, Richard Henderson wrote:
> The LSE CASP instruction requires values to be placed in even
> register pairs. A solution involving two additional register
> classes was rejected in favor of the much simpler solution of
> simply requiring all TImode values to
On Wed, Oct 31, 2018 at 04:55:26PM -0500, Richard Henderson wrote:
> On 10/31/18 5:51 PM, Will Deacon wrote:
> > Aha, maybe this is the problem. An acquire fence on AArch64 is implemented
> > using a DMB LD instruction, which orders prior reads against subsequent
> > reads and writes. However, the
On Fri, Nov 02, 2018 at 01:37:33PM -0500, Sudakshina Das wrote:
> Hi
>
> This patch is part of a series that enables ARMv8.5-A in GCC and
> adds Branch Target Identification Mechanism.
> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>
> This patch
On Fri, Nov 02, 2018 at 01:37:41PM -0500, Sudakshina Das wrote:
> Hi
>
> This patch is part of a series that enables ARMv8.5-A in GCC and
> adds Branch Target Identification Mechanism.
> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>
> This patch
On Fri, Nov 02, 2018 at 01:38:25PM -0500, Sudakshina Das wrote:
> Hi
>
> This patch is part of a series that enables ARMv8.5-A in GCC and
> adds Branch Target Identification Mechanism.
> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>
> NOTE: This
On Fri, Nov 02, 2018 at 01:38:46PM -0500, Sudakshina Das wrote:
> Hi
>
> This patch is part of a series that enables ARMv8.5-A in GCC and
> adds Branch Target Identification Mechanism.
> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>
> This patch
On Tue, Oct 23, 2018 at 08:17:43AM -0500, Martin Liška wrote:
> Hello.
>
> As a follow up patch I would like to remove redundant string allocation
> on string which is not needed in my opinion.
>
> That bootstrap on aarch64-linux.
OK,
Thanks,
James
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